Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_nand.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_nand.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief NAND HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NAND memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NAND flash memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NAND devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both common and attribute spaces.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NAND flash memory maker and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NAND flash memory by read/write operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
<> 144:ef7eb2e8f9f7 29 to read/write page(s)/spare area(s). These functions use specific device
<> 144:ef7eb2e8f9f7 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
<> 144:ef7eb2e8f9f7 31 structure. The read/write address information is contained by the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 32 structure passed as parameter.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
<> 144:ef7eb2e8f9f7 37 The erase block address information is contained in the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 38 structure passed as parameter.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
<> 144:ef7eb2e8f9f7 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
<> 144:ef7eb2e8f9f7 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (+) You can monitor the NAND device HAL state by calling the function
<> 144:ef7eb2e8f9f7 47 HAL_NAND_GetState()
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
<> 144:ef7eb2e8f9f7 51 If a NAND flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 52 it should be implemented separately.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #ifdef HAL_NAND_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @defgroup NAND NAND
<> 144:ef7eb2e8f9f7 97 * @brief NAND HAL module driver
<> 144:ef7eb2e8f9f7 98 * @{
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /** @defgroup NAND_Private_Constants NAND Private Constants
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @}
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 112 /** @defgroup NAND_Private_Macros NAND Private Macros
<> 144:ef7eb2e8f9f7 113 * @{
<> 144:ef7eb2e8f9f7 114 */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @}
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /** @defgroup NAND_Exported_Functions NAND Exported Functions
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### NAND Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 135 the NAND memory
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 @endverbatim
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @brief Perform NAND memory Initialization sequence
<> 144:ef7eb2e8f9f7 143 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 144 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 145 * @param ComSpace_Timing: pointer to Common space timing structure
<> 144:ef7eb2e8f9f7 146 * @param AttSpace_Timing: pointer to Attribute space timing structure
<> 144:ef7eb2e8f9f7 147 * @retval HAL status
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 /* Check the NAND handle state */
<> 144:ef7eb2e8f9f7 152 if(hnand == NULL)
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 if(hnand->State == HAL_NAND_STATE_RESET)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 160 hnand->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 161 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 162 HAL_NAND_MspInit(hnand);
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Initialize NAND control Interface */
<> 144:ef7eb2e8f9f7 166 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Initialize NAND common space timing Interface */
<> 144:ef7eb2e8f9f7 169 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Initialize NAND attribute space timing Interface */
<> 144:ef7eb2e8f9f7 172 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Enable the NAND device */
<> 144:ef7eb2e8f9f7 175 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 178 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 return HAL_OK;
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @brief Perform NAND memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 185 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 186 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 187 * @retval HAL status
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 190 {
<> 144:ef7eb2e8f9f7 191 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 192 HAL_NAND_MspDeInit(hnand);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Configure the NAND registers with their reset values */
<> 144:ef7eb2e8f9f7 195 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Reset the NAND controller state */
<> 144:ef7eb2e8f9f7 198 hnand->State = HAL_NAND_STATE_RESET;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Release Lock */
<> 144:ef7eb2e8f9f7 201 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 return HAL_OK;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief NAND MSP Init
<> 144:ef7eb2e8f9f7 208 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 209 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 210 * @retval None
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 215 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 216 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 217 the HAL_NAND_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @brief NAND MSP DeInit
<> 144:ef7eb2e8f9f7 223 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 224 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 225 * @retval None
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 230 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 231 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 232 the HAL_NAND_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief This function handles NAND device interrupt request.
<> 144:ef7eb2e8f9f7 239 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 240 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 241 * @retval HAL status
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Check NAND interrupt Rising edge flag */
<> 144:ef7eb2e8f9f7 246 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 249 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Clear NAND interrupt Rising edge pending bit */
<> 144:ef7eb2e8f9f7 252 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Check NAND interrupt Level flag */
<> 144:ef7eb2e8f9f7 256 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 259 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Clear NAND interrupt Level pending bit */
<> 144:ef7eb2e8f9f7 262 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Check NAND interrupt Falling edge flag */
<> 144:ef7eb2e8f9f7 266 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 269 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Clear NAND interrupt Falling edge pending bit */
<> 144:ef7eb2e8f9f7 272 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Check NAND interrupt FIFO empty flag */
<> 144:ef7eb2e8f9f7 276 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 279 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Clear NAND interrupt FIFO empty pending bit */
<> 144:ef7eb2e8f9f7 282 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief NAND interrupt feature callback
<> 144:ef7eb2e8f9f7 289 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 290 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 291 * @retval None
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 296 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 297 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 298 the HAL_NAND_ITCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 307 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 308 *
<> 144:ef7eb2e8f9f7 309 @verbatim
<> 144:ef7eb2e8f9f7 310 ==============================================================================
<> 144:ef7eb2e8f9f7 311 ##### NAND Input and Output functions #####
<> 144:ef7eb2e8f9f7 312 ==============================================================================
<> 144:ef7eb2e8f9f7 313 [..]
<> 144:ef7eb2e8f9f7 314 This section provides functions allowing to use and control the NAND
<> 144:ef7eb2e8f9f7 315 memory
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 @endverbatim
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @brief Read the NAND memory electronic signature
<> 144:ef7eb2e8f9f7 323 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 324 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 325 * @param pNAND_ID: NAND ID structure
<> 144:ef7eb2e8f9f7 326 * @retval HAL status
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 __IO uint32_t data = 0U;
<> 144:ef7eb2e8f9f7 331 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Process Locked */
<> 144:ef7eb2e8f9f7 334 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 337 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Identify the device address */
<> 144:ef7eb2e8f9f7 343 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 else
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 353 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Send Read ID command sequence */
<> 144:ef7eb2e8f9f7 356 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
<> 144:ef7eb2e8f9f7 357 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Read the electronic signature from NAND flash */
<> 144:ef7eb2e8f9f7 360 data = *(__IO uint32_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Return the data read */
<> 144:ef7eb2e8f9f7 363 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
<> 144:ef7eb2e8f9f7 364 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
<> 144:ef7eb2e8f9f7 365 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
<> 144:ef7eb2e8f9f7 366 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 369 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Process unlocked */
<> 144:ef7eb2e8f9f7 372 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 return HAL_OK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief NAND memory reset
<> 144:ef7eb2e8f9f7 379 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 380 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 381 * @retval HAL status
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* Process Locked */
<> 144:ef7eb2e8f9f7 388 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 391 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Identify the device address */
<> 144:ef7eb2e8f9f7 397 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 407 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Send NAND reset command */
<> 144:ef7eb2e8f9f7 410 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFFU;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 414 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Process unlocked */
<> 144:ef7eb2e8f9f7 417 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 return HAL_OK;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @brief Read Page(s) from NAND memory block
<> 144:ef7eb2e8f9f7 425 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 426 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 427 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 428 * @param pBuffer : pointer to destination read buffer
<> 144:ef7eb2e8f9f7 429 * @param NumPageToRead : number of pages to read from block
<> 144:ef7eb2e8f9f7 430 * @retval HAL status
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 __IO uint32_t index = 0U;
<> 144:ef7eb2e8f9f7 435 uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 436 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 437 uint32_t addressoffset = 0U;
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Process Locked */
<> 144:ef7eb2e8f9f7 440 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 443 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Identify the device address */
<> 144:ef7eb2e8f9f7 449 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 else
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 459 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 462 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 463 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 464 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* Page(s) read loop */
<> 144:ef7eb2e8f9f7 467 while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 /* update the buffer size */
<> 144:ef7eb2e8f9f7 470 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Get the address offset */
<> 144:ef7eb2e8f9f7 473 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Send read page command sequence */
<> 144:ef7eb2e8f9f7 476 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
<> 144:ef7eb2e8f9f7 479 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 480 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 481 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 484 if(hnand->Info.BlockNbr >= 1024U)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 492 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Increment read pages number */
<> 144:ef7eb2e8f9f7 498 numpagesread++;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Decrement pages to read */
<> 144:ef7eb2e8f9f7 501 NumPageToRead--;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 504 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 508 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Process unlocked */
<> 144:ef7eb2e8f9f7 511 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 return HAL_OK;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Write Page(s) to NAND memory block
<> 144:ef7eb2e8f9f7 519 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 520 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 521 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 522 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 523 * @param NumPageToWrite : number of pages to write to block
<> 144:ef7eb2e8f9f7 524 * @retval HAL status
<> 144:ef7eb2e8f9f7 525 */
<> 144:ef7eb2e8f9f7 526 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 __IO uint32_t index = 0U;
<> 144:ef7eb2e8f9f7 529 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 530 uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 531 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 532 uint32_t addressoffset = 0U;
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Process Locked */
<> 144:ef7eb2e8f9f7 535 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 538 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Identify the device address */
<> 144:ef7eb2e8f9f7 544 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 545 {
<> 144:ef7eb2e8f9f7 546 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 else
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 554 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 557 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 558 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 559 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Page(s) write loop */
<> 144:ef7eb2e8f9f7 562 while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* update the buffer size */
<> 144:ef7eb2e8f9f7 565 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Get the address offset */
<> 144:ef7eb2e8f9f7 568 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Send write page command sequence */
<> 144:ef7eb2e8f9f7 571 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 572 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
<> 144:ef7eb2e8f9f7 575 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 576 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 577 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 580 if(hnand->Info.BlockNbr >= 1024U)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Write data to memory */
<> 144:ef7eb2e8f9f7 586 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Get tick */
<> 144:ef7eb2e8f9f7 594 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 597 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Increment written pages number */
<> 144:ef7eb2e8f9f7 606 numpageswritten++;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Decrement pages to write */
<> 144:ef7eb2e8f9f7 609 NumPageToWrite--;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 612 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 616 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Process unlocked */
<> 144:ef7eb2e8f9f7 619 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 return HAL_OK;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief Read Spare area(s) from NAND memory
<> 144:ef7eb2e8f9f7 626 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 627 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 628 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 629 * @param pBuffer: pointer to source buffer to write
<> 144:ef7eb2e8f9f7 630 * @param NumSpareAreaToRead: Number of spare area to read
<> 144:ef7eb2e8f9f7 631 * @retval HAL status
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 __IO uint32_t index = 0U;
<> 144:ef7eb2e8f9f7 636 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 637 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 638 uint32_t addressoffset = 0U;
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Process Locked */
<> 144:ef7eb2e8f9f7 641 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 644 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Identify the device address */
<> 144:ef7eb2e8f9f7 650 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 else
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 660 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 663 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 664 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 665 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Spare area(s) read loop */
<> 144:ef7eb2e8f9f7 668 while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 /* update the buffer size */
<> 144:ef7eb2e8f9f7 671 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Get the address offset */
<> 144:ef7eb2e8f9f7 674 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Send read spare area command sequence */
<> 144:ef7eb2e8f9f7 677 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
<> 144:ef7eb2e8f9f7 680 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 681 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 682 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 685 if(hnand->Info.BlockNbr >= 1024U)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 693 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Increment read spare areas number */
<> 144:ef7eb2e8f9f7 699 num_spare_area_read++;
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Decrement spare areas to read */
<> 144:ef7eb2e8f9f7 702 NumSpareAreaToRead--;
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 705 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 709 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Process unlocked */
<> 144:ef7eb2e8f9f7 712 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 return HAL_OK;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /**
<> 144:ef7eb2e8f9f7 718 * @brief Write Spare area(s) to NAND memory
<> 144:ef7eb2e8f9f7 719 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 720 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 721 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 722 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 723 * @param NumSpareAreaTowrite : number of spare areas to write to block
<> 144:ef7eb2e8f9f7 724 * @retval HAL status
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 __IO uint32_t index = 0U;
<> 144:ef7eb2e8f9f7 729 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 730 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 731 NAND_AddressTypeDef nandaddress;
<> 144:ef7eb2e8f9f7 732 uint32_t addressoffset = 0U;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Process Locked */
<> 144:ef7eb2e8f9f7 735 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 738 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Identify the device address */
<> 144:ef7eb2e8f9f7 744 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748 else
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Update the FSMC_NAND controller state */
<> 144:ef7eb2e8f9f7 754 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Save the content of pAddress as it will be modified */
<> 144:ef7eb2e8f9f7 757 nandaddress.Block = pAddress->Block;
<> 144:ef7eb2e8f9f7 758 nandaddress.Page = pAddress->Page;
<> 144:ef7eb2e8f9f7 759 nandaddress.Zone = pAddress->Zone;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Spare area(s) write loop */
<> 144:ef7eb2e8f9f7 762 while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 /* update the buffer size */
<> 144:ef7eb2e8f9f7 765 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /* Get the address offset */
<> 144:ef7eb2e8f9f7 768 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Send write Spare area command sequence */
<> 144:ef7eb2e8f9f7 771 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 772 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
<> 144:ef7eb2e8f9f7 775 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 776 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 777 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 780 if(hnand->Info.BlockNbr >= 1024U)
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Write data to memory */
<> 144:ef7eb2e8f9f7 786 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Get tick */
<> 144:ef7eb2e8f9f7 794 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 797 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /* Increment written spare areas number */
<> 144:ef7eb2e8f9f7 806 num_spare_area_written++;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Decrement spare areas to write */
<> 144:ef7eb2e8f9f7 809 NumSpareAreaTowrite--;
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 812 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 816 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Process unlocked */
<> 144:ef7eb2e8f9f7 819 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 return HAL_OK;
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /**
<> 144:ef7eb2e8f9f7 825 * @brief NAND memory Block erase
<> 144:ef7eb2e8f9f7 826 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 827 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 828 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 829 * @retval HAL status
<> 144:ef7eb2e8f9f7 830 */
<> 144:ef7eb2e8f9f7 831 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 834 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Process Locked */
<> 144:ef7eb2e8f9f7 837 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 840 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Identify the device address */
<> 144:ef7eb2e8f9f7 846 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 else
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 856 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Send Erase block command sequence */
<> 144:ef7eb2e8f9f7 859 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 862 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 863 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 866 if(hnand->Info.BlockNbr >= 1024U)
<> 144:ef7eb2e8f9f7 867 {
<> 144:ef7eb2e8f9f7 868 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 869 }
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 874 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Get tick */
<> 144:ef7eb2e8f9f7 877 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 880 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 /* Process unlocked */
<> 144:ef7eb2e8f9f7 885 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /* Process unlocked */
<> 144:ef7eb2e8f9f7 892 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 return HAL_OK;
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief NAND memory read status
<> 144:ef7eb2e8f9f7 899 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 900 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 901 * @retval NAND status
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 uint32_t data = 0U;
<> 144:ef7eb2e8f9f7 906 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /* Identify the device address */
<> 144:ef7eb2e8f9f7 909 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 910 {
<> 144:ef7eb2e8f9f7 911 deviceaddress = NAND_DEVICE1;
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 else
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 deviceaddress = NAND_DEVICE2;
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Send Read status operation command */
<> 144:ef7eb2e8f9f7 919 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Read status register data */
<> 144:ef7eb2e8f9f7 922 data = *(__IO uint8_t *)deviceaddress;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Return the status */
<> 144:ef7eb2e8f9f7 925 if((data & NAND_ERROR) == NAND_ERROR)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 return NAND_ERROR;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 else if((data & NAND_READY) == NAND_READY)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 return NAND_READY;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 return NAND_BUSY;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief Increment the NAND memory address
<> 144:ef7eb2e8f9f7 939 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 940 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 941 * @param pAddress: pointer to NAND address structure
<> 144:ef7eb2e8f9f7 942 * @retval The new status of the increment address operation. It can be:
<> 144:ef7eb2e8f9f7 943 * - NAND_VALID_ADDRESS: When the new address is valid address
<> 144:ef7eb2e8f9f7 944 * - NAND_INVALID_ADDRESS: When the new address is invalid address
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 uint32_t status = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Increment page address */
<> 144:ef7eb2e8f9f7 951 pAddress->Page++;
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Check NAND address is valid */
<> 144:ef7eb2e8f9f7 954 if(pAddress->Page == hnand->Info.BlockSize)
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 pAddress->Page = 0U;
<> 144:ef7eb2e8f9f7 957 pAddress->Block++;
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 if(pAddress->Block == hnand->Info.ZoneSize)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 pAddress->Block = 0U;
<> 144:ef7eb2e8f9f7 962 pAddress->Zone++;
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 status = NAND_INVALID_ADDRESS;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 return (status);
<> 144:ef7eb2e8f9f7 972 }
<> 144:ef7eb2e8f9f7 973 /**
<> 144:ef7eb2e8f9f7 974 * @}
<> 144:ef7eb2e8f9f7 975 */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 978 * @brief management functions
<> 144:ef7eb2e8f9f7 979 *
<> 144:ef7eb2e8f9f7 980 @verbatim
<> 144:ef7eb2e8f9f7 981 ==============================================================================
<> 144:ef7eb2e8f9f7 982 ##### NAND Control functions #####
<> 144:ef7eb2e8f9f7 983 ==============================================================================
<> 144:ef7eb2e8f9f7 984 [..]
<> 144:ef7eb2e8f9f7 985 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 986 the NAND interface.
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 @endverbatim
<> 144:ef7eb2e8f9f7 989 * @{
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /**
<> 144:ef7eb2e8f9f7 994 * @brief Enables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 995 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 996 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 997 * @retval HAL status
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1002 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1008 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 1011 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1014 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 return HAL_OK;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 1021 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1022 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1023 * @retval HAL status
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1028 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1034 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 1037 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1040 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 return HAL_OK;
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /**
<> 144:ef7eb2e8f9f7 1046 * @brief Disables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 1047 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1048 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1049 * @param ECCval: pointer to ECC value
<> 144:ef7eb2e8f9f7 1050 * @param Timeout: maximum timeout to wait
<> 144:ef7eb2e8f9f7 1051 * @retval HAL status
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1058 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1064 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Get NAND ECC value */
<> 144:ef7eb2e8f9f7 1067 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1070 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 return status;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /**
<> 144:ef7eb2e8f9f7 1076 * @}
<> 144:ef7eb2e8f9f7 1077 */
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 1081 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1082 *
<> 144:ef7eb2e8f9f7 1083 @verbatim
<> 144:ef7eb2e8f9f7 1084 ==============================================================================
<> 144:ef7eb2e8f9f7 1085 ##### NAND State functions #####
<> 144:ef7eb2e8f9f7 1086 ==============================================================================
<> 144:ef7eb2e8f9f7 1087 [..]
<> 144:ef7eb2e8f9f7 1088 This subsection permits to get in run-time the status of the NAND controller
<> 144:ef7eb2e8f9f7 1089 and the data flow.
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 @endverbatim
<> 144:ef7eb2e8f9f7 1092 * @{
<> 144:ef7eb2e8f9f7 1093 */
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /**
<> 144:ef7eb2e8f9f7 1096 * @brief return the NAND state
<> 144:ef7eb2e8f9f7 1097 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1098 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1099 * @retval HAL state
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1102 {
<> 144:ef7eb2e8f9f7 1103 return hnand->State;
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 /**
<> 144:ef7eb2e8f9f7 1107 * @}
<> 144:ef7eb2e8f9f7 1108 */
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /**
<> 144:ef7eb2e8f9f7 1111 * @}
<> 144:ef7eb2e8f9f7 1112 */
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /**
<> 144:ef7eb2e8f9f7 1115 * @}
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 #endif /* HAL_NAND_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @}
<> 144:ef7eb2e8f9f7 1122 */
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/