mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.3
<>	144:ef7eb2e8f9f7	6	* @date 29-June-2016
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	21
<>	144:ef7eb2e8f9f7	22	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	23	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	24
<>	144:ef7eb2e8f9f7	25	(#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
<>	144:ef7eb2e8f9f7	26	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	27	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	28	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	29	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	30	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	31	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	33	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
<>	144:ef7eb2e8f9f7	35	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	37	(+++) Configure the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	38	(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	40	the DMA Tx or Rx Stream
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
<>	144:ef7eb2e8f9f7	43	Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	46	(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	47
<>	144:ef7eb2e8f9f7	48	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	53	=================================
<>	144:ef7eb2e8f9f7	54	[..]
<>	144:ef7eb2e8f9f7	55	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	56	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	57	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	58	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	61	=====================================
<>	144:ef7eb2e8f9f7	62	[..]
<>	144:ef7eb2e8f9f7	63	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	64	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	68	===================================
<>	144:ef7eb2e8f9f7	69	[..]
<>	144:ef7eb2e8f9f7	70	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	71	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	72	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	73	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	74	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	75	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	76	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	77	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	78	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	79	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	80	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	81	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	82	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	83	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	84	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	85	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	86	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	* Interrupt mode IO sequential operation *
<>	144:ef7eb2e8f9f7	89	==============================================
<>	144:ef7eb2e8f9f7	90	[..]
<>	144:ef7eb2e8f9f7	91	(@) These interfaces allow to manage a sequential transfer with a repeated start condition
<>	144:ef7eb2e8f9f7	92	when a direction change during transfer
<>	144:ef7eb2e8f9f7	93	[..]
<>	144:ef7eb2e8f9f7	94	(+) A specific option field manage the different steps of a sequential transfer
<>	144:ef7eb2e8f9f7	95	(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
<>	144:ef7eb2e8f9f7	96	(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
<>	144:ef7eb2e8f9f7	97	(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
<>	144:ef7eb2e8f9f7	98	and data to transfer without a final stop condition
<>	144:ef7eb2e8f9f7	99	(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
<>	144:ef7eb2e8f9f7	100	and with new data to transfer if the direction change or manage only the new data to transfer
<>	144:ef7eb2e8f9f7	101	if no direction change and without a final stop condition in both cases
<>	144:ef7eb2e8f9f7	102	(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
<>	144:ef7eb2e8f9f7	103	and with new data to transfer if the direction change or manage only the new data to transfer
<>	144:ef7eb2e8f9f7	104	if no direction change and with a final stop condition in both cases
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	(+) Differents sequential I2C interfaces are listed below:
<>	144:ef7eb2e8f9f7	107	(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	108	(+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	109	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	110	(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	111	(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	112	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	113	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	114	(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	115	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	116	(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
<>	144:ef7eb2e8f9f7	117	(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<>	144:ef7eb2e8f9f7	118	add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
<>	144:ef7eb2e8f9f7	119	(+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	120	add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
<>	144:ef7eb2e8f9f7	121	(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	122	(+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	123	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	124	(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	125	(+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	126	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	127	(++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	128	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	129	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	130	(++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	131	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	134	=======================================
<>	144:ef7eb2e8f9f7	135	[..]
<>	144:ef7eb2e8f9f7	136	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	137	HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	138	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	139	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	140	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	141	HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	142	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	143	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	144	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	145	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	148	==============================
<>	144:ef7eb2e8f9f7	149	[..]
<>	144:ef7eb2e8f9f7	150	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	151	HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	152	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	153	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	144:ef7eb2e8f9f7	154	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	155	HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	156	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	157	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	144:ef7eb2e8f9f7	158	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	159	HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	160	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	161	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	144:ef7eb2e8f9f7	162	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	163	HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	164	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	165	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	166	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	167	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	168	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	144:ef7eb2e8f9f7	169	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	170	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	173	=================================
<>	144:ef7eb2e8f9f7	174	[..]
<>	144:ef7eb2e8f9f7	175	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	176	HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	177	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	178	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	144:ef7eb2e8f9f7	179	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	180	HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	181	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	182	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	183	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	184	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	185
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	188	==================================
<>	144:ef7eb2e8f9f7	189	[..]
<>	144:ef7eb2e8f9f7	190	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	191
<>	144:ef7eb2e8f9f7	192	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	193	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<>	144:ef7eb2e8f9f7	194	(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
<>	144:ef7eb2e8f9f7	195	(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	196	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	197	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	[..]
<>	144:ef7eb2e8f9f7	200	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	@endverbatim
<>	144:ef7eb2e8f9f7	204	******************************************************************************
<>	144:ef7eb2e8f9f7	205	* @attention
<>	144:ef7eb2e8f9f7	206	*
<>	144:ef7eb2e8f9f7	207	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	208	*
<>	144:ef7eb2e8f9f7	209	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	210	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	211	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	212	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	213	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	214	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	215	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	216	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	217	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	218	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	219	*
<>	144:ef7eb2e8f9f7	220	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	221	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	222	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	223	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	224	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	225	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	226	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	227	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	228	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	229	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	230	*
<>	144:ef7eb2e8f9f7	231	******************************************************************************
<>	144:ef7eb2e8f9f7	232	*/
<>	144:ef7eb2e8f9f7	233
<>	144:ef7eb2e8f9f7	234	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	235	#include "stm32f2xx_hal.h"
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	238	* @{
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	/** @defgroup I2C I2C
<>	144:ef7eb2e8f9f7	242	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	243	* @{
<>	144:ef7eb2e8f9f7	244	*/
<>	144:ef7eb2e8f9f7	245
<>	144:ef7eb2e8f9f7	246	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	249	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	250	/** @addtogroup I2C_Private_Define
<>	144:ef7eb2e8f9f7	251	* @{
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253	#define I2C_TIMEOUT_FLAG ((uint32_t)35U) /!< Timeout 35 ms /
<>	144:ef7eb2e8f9f7	254	#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)25U) /!< Timeout 25 ms /
<>	144:ef7eb2e8f9f7	255	#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) /!< XferOptions default value /
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/* Private define for @ref PreviousState usage */
<>	144:ef7eb2e8f9f7	258	#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX \| HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /!< Mask State define, keep only RX and TX bits /
<>	144:ef7eb2e8f9f7	259	#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /!< Default Value /
<>	144:ef7eb2e8f9f7	260	#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	261	#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	262	#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy TX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	263	#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy RX, combinaison of State LSB and Mode enum /
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	/**
<>	144:ef7eb2e8f9f7	266	* @}
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	270	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	271	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	272	/** @addtogroup I2C_Private_Functions
<>	144:ef7eb2e8f9f7	273	* @{
<>	144:ef7eb2e8f9f7	274	*/
<>	144:ef7eb2e8f9f7	275	/* Private functions to handle DMA transfer */
<>	144:ef7eb2e8f9f7	276	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	277	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	278	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	static void I2C_ITError(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	283	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	284	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	285	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	286	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	287	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	288	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	289	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	290	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	291	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	292	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	293
<>	144:ef7eb2e8f9f7	294	/* Private functions for I2C transfer IRQ handler */
<>	144:ef7eb2e8f9f7	295	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	296	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	297	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	298	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	299	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	300	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	301	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	304	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	305	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	306	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	307	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	308	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	309	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	310	/**
<>	144:ef7eb2e8f9f7	311	* @}
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	315	/** @defgroup I2C_Exported_Functions I2C Exported Functions
<>	144:ef7eb2e8f9f7	316	* @{
<>	144:ef7eb2e8f9f7	317	*/
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	320	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	321	*
<>	144:ef7eb2e8f9f7	322	@verbatim
<>	144:ef7eb2e8f9f7	323	===============================================================================
<>	144:ef7eb2e8f9f7	324	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	325	===============================================================================
<>	144:ef7eb2e8f9f7	326	[..] This subsection provides a set of functions allowing to initialize and
<>	144:ef7eb2e8f9f7	327	de-initialize the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	330	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	333	the selected configuration:
<>	144:ef7eb2e8f9f7	334	(++) Communication Speed
<>	144:ef7eb2e8f9f7	335	(++) Duty cycle
<>	144:ef7eb2e8f9f7	336	(++) Addressing mode
<>	144:ef7eb2e8f9f7	337	(++) Own Address 1
<>	144:ef7eb2e8f9f7	338	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	339	(++) Own Address 2
<>	144:ef7eb2e8f9f7	340	(++) General call mode
<>	144:ef7eb2e8f9f7	341	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	144:ef7eb2e8f9f7	344	of the selected I2Cx peripheral.
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	@endverbatim
<>	144:ef7eb2e8f9f7	347	* @{
<>	144:ef7eb2e8f9f7	348	*/
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/**
<>	144:ef7eb2e8f9f7	351	* @brief Initializes the I2C according to the specified parameters
<>	144:ef7eb2e8f9f7	352	* in the I2C_InitTypeDef and create the associated handle.
<>	144:ef7eb2e8f9f7	353	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	354	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	355	* @retval HAL status
<>	144:ef7eb2e8f9f7	356	*/
<>	144:ef7eb2e8f9f7	357	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	358	{
<>	144:ef7eb2e8f9f7	359	uint32_t freqrange = 0U;
<>	144:ef7eb2e8f9f7	360	uint32_t pclk1 = 0U;
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	363	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	364	{
<>	144:ef7eb2e8f9f7	365	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	366	}
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/* Check the parameters */
<>	144:ef7eb2e8f9f7	369	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	370	assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
<>	144:ef7eb2e8f9f7	371	assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
<>	144:ef7eb2e8f9f7	372	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	373	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	374	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	375	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	376	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	377	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	380	{
<>	144:ef7eb2e8f9f7	381	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	382	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	383	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	384	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	385	}
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	390	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	391
<>	144:ef7eb2e8f9f7	392	/* Get PCLK1 frequency */
<>	144:ef7eb2e8f9f7	393	pclk1 = HAL_RCC_GetPCLK1Freq();
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/* Calculate frequency range */
<>	144:ef7eb2e8f9f7	396	freqrange = I2C_FREQRANGE(pclk1);
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	399	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	400	hi2c->Instance->CR2 = freqrange;
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	/---------------------------- I2Cx TRISE Configuration --------------------/
<>	144:ef7eb2e8f9f7	403	/* Configure I2Cx: Rise Time */
<>	144:ef7eb2e8f9f7	404	hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/---------------------------- I2Cx CCR Configuration ----------------------/
<>	144:ef7eb2e8f9f7	407	/* Configure I2Cx: Speed */
<>	144:ef7eb2e8f9f7	408	hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	411	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	412	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	415	/* Configure I2Cx: Own Address1 and addressing mode */
<>	144:ef7eb2e8f9f7	416	hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	419	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	420	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2);
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	423	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	426	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	427	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	428	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	return HAL_OK;
<>	144:ef7eb2e8f9f7	431	}
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	/**
<>	144:ef7eb2e8f9f7	434	* @brief DeInitializes the I2C peripheral.
<>	144:ef7eb2e8f9f7	435	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	436	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	437	* @retval HAL status
<>	144:ef7eb2e8f9f7	438	*/
<>	144:ef7eb2e8f9f7	439	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	440	{
<>	144:ef7eb2e8f9f7	441	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	442	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	443	{
<>	144:ef7eb2e8f9f7	444	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	445	}
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/* Check the parameters */
<>	144:ef7eb2e8f9f7	448	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	451
<>	144:ef7eb2e8f9f7	452	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	453	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	456	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	459	hi2c->State = HAL_I2C_STATE_RESET;
<>	144:ef7eb2e8f9f7	460	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	461	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	/* Release Lock */
<>	144:ef7eb2e8f9f7	464	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	return HAL_OK;
<>	144:ef7eb2e8f9f7	467	}
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/**
<>	144:ef7eb2e8f9f7	470	* @brief I2C MSP Init.
<>	144:ef7eb2e8f9f7	471	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	472	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	473	* @retval None
<>	144:ef7eb2e8f9f7	474	*/
<>	144:ef7eb2e8f9f7	475	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	476	{
<>	144:ef7eb2e8f9f7	477	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	478	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	479	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	480	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482	}
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	/**
<>	144:ef7eb2e8f9f7	485	* @brief I2C MSP DeInit
<>	144:ef7eb2e8f9f7	486	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	487	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	488	* @retval None
<>	144:ef7eb2e8f9f7	489	*/
<>	144:ef7eb2e8f9f7	490	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	491	{
<>	144:ef7eb2e8f9f7	492	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	493	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	494	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	495	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497	}
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/**
<>	144:ef7eb2e8f9f7	500	* @}
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	504	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	505	*
<>	144:ef7eb2e8f9f7	506	@verbatim
<>	144:ef7eb2e8f9f7	507	===============================================================================
<>	144:ef7eb2e8f9f7	508	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	509	===============================================================================
<>	144:ef7eb2e8f9f7	510	[..]
<>	144:ef7eb2e8f9f7	511	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	512	transfers.
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	515	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	516	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	517	after finishing transfer.
<>	144:ef7eb2e8f9f7	518	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	519	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	520	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	521	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	522	using DMA mode.
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	525	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	526	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	527	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	528	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	529	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	530	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	531	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	534	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	535	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	536	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	537	(++) HAL_I2C_Slave_Receive_IT()
<>	144:ef7eb2e8f9f7	538	(++) HAL_I2C_Master_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	539	(++) HAL_I2C_Master_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	540	(++) HAL_I2C_Slave_Sequential_Transmit_IT()
<>	144:ef7eb2e8f9f7	541	(++) HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	542	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	543	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	544
<>	144:ef7eb2e8f9f7	545	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	546	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	547	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	548	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	549	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	550	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	551	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	554	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	555	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	556	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	557	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	558	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	559	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	560	(++) HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	561	(++) HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	@endverbatim
<>	144:ef7eb2e8f9f7	564	* @{
<>	144:ef7eb2e8f9f7	565	*/
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/**
<>	144:ef7eb2e8f9f7	568	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	569	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	570	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	571	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	572	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	573	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	574	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	575	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	576	* @retval HAL status
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	579	{
<>	144:ef7eb2e8f9f7	580	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	583	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	586	{
<>	144:ef7eb2e8f9f7	587	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	588	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	589	{
<>	144:ef7eb2e8f9f7	590	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	591	}
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	/* Process Locked */
<>	144:ef7eb2e8f9f7	594	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	597	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	598	{
<>	144:ef7eb2e8f9f7	599	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	600	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	601	}
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	/* Disable Pos */
<>	144:ef7eb2e8f9f7	604	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	607	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	608	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	611	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	612	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	613	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	614	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	617	if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	618	{
<>	144:ef7eb2e8f9f7	619	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	620	{
<>	144:ef7eb2e8f9f7	621	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	622	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	623	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	624	}
<>	144:ef7eb2e8f9f7	625	else
<>	144:ef7eb2e8f9f7	626	{
<>	144:ef7eb2e8f9f7	627	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	628	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	629	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	630	}
<>	144:ef7eb2e8f9f7	631	}
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	634	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	637	{
<>	144:ef7eb2e8f9f7	638	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	639	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	640	{
<>	144:ef7eb2e8f9f7	641	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	642	{
<>	144:ef7eb2e8f9f7	643	/* Generate Stop */
<>	144:ef7eb2e8f9f7	644	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	645	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	646	}
<>	144:ef7eb2e8f9f7	647	else
<>	144:ef7eb2e8f9f7	648	{
<>	144:ef7eb2e8f9f7	649	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	650	}
<>	144:ef7eb2e8f9f7	651	}
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/* Write data to DR */
<>	144:ef7eb2e8f9f7	654	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	655	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	656	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	659	{
<>	144:ef7eb2e8f9f7	660	/* Write data to DR */
<>	144:ef7eb2e8f9f7	661	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	662	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	663	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	664	}
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	667	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	668	{
<>	144:ef7eb2e8f9f7	669	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	/* Generate Stop */
<>	144:ef7eb2e8f9f7	672	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	673	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675	else
<>	144:ef7eb2e8f9f7	676	{
<>	144:ef7eb2e8f9f7	677	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	678	}
<>	144:ef7eb2e8f9f7	679	}
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/* Generate Stop */
<>	144:ef7eb2e8f9f7	683	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	686	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	689	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	return HAL_OK;
<>	144:ef7eb2e8f9f7	692	}
<>	144:ef7eb2e8f9f7	693	else
<>	144:ef7eb2e8f9f7	694	{
<>	144:ef7eb2e8f9f7	695	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697	}
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/**
<>	144:ef7eb2e8f9f7	700	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	701	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	702	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	703	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	704	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	705	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	706	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	707	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	708	* @retval HAL status
<>	144:ef7eb2e8f9f7	709	*/
<>	144:ef7eb2e8f9f7	710	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	711	{
<>	144:ef7eb2e8f9f7	712	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	715	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	718	{
<>	144:ef7eb2e8f9f7	719	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	720	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	721	{
<>	144:ef7eb2e8f9f7	722	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	723	}
<>	144:ef7eb2e8f9f7	724
<>	144:ef7eb2e8f9f7	725	/* Process Locked */
<>	144:ef7eb2e8f9f7	726	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	729	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	730	{
<>	144:ef7eb2e8f9f7	731	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	732	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	733	}
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/* Disable Pos */
<>	144:ef7eb2e8f9f7	736	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	739	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	740	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	743	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	744	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	745	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	746	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	/* Send Slave Address */
<>	144:ef7eb2e8f9f7	749	if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	750	{
<>	144:ef7eb2e8f9f7	751	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	752	{
<>	144:ef7eb2e8f9f7	753	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	754	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	755	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757	else
<>	144:ef7eb2e8f9f7	758	{
<>	144:ef7eb2e8f9f7	759	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	760	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	761	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	762	}
<>	144:ef7eb2e8f9f7	763	}
<>	144:ef7eb2e8f9f7	764
<>	144:ef7eb2e8f9f7	765	if(hi2c->XferSize == 0U)
<>	144:ef7eb2e8f9f7	766	{
<>	144:ef7eb2e8f9f7	767	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	768	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/* Generate Stop */
<>	144:ef7eb2e8f9f7	771	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	772	}
<>	144:ef7eb2e8f9f7	773	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	774	{
<>	144:ef7eb2e8f9f7	775	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	776	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	779	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	/* Generate Stop */
<>	144:ef7eb2e8f9f7	782	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	783	}
<>	144:ef7eb2e8f9f7	784	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	785	{
<>	144:ef7eb2e8f9f7	786	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	787	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	/* Enable Pos */
<>	144:ef7eb2e8f9f7	790	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	793	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	794	}
<>	144:ef7eb2e8f9f7	795	else
<>	144:ef7eb2e8f9f7	796	{
<>	144:ef7eb2e8f9f7	797	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	798	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	801	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	802	}
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	805	{
<>	144:ef7eb2e8f9f7	806	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	807	{
<>	144:ef7eb2e8f9f7	808	/* One byte */
<>	144:ef7eb2e8f9f7	809	if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	810	{
<>	144:ef7eb2e8f9f7	811	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	812	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	813	{
<>	144:ef7eb2e8f9f7	814	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	815	{
<>	144:ef7eb2e8f9f7	816	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	817	}
<>	144:ef7eb2e8f9f7	818	else
<>	144:ef7eb2e8f9f7	819	{
<>	144:ef7eb2e8f9f7	820	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/* Read data from DR */
<>	144:ef7eb2e8f9f7	825	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	826	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	827	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	828	}
<>	144:ef7eb2e8f9f7	829	/* Two bytes */
<>	144:ef7eb2e8f9f7	830	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	831	{
<>	144:ef7eb2e8f9f7	832	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	833	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	836	}
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Generate Stop */
<>	144:ef7eb2e8f9f7	839	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Read data from DR */
<>	144:ef7eb2e8f9f7	842	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	843	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	844	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	/* Read data from DR */
<>	144:ef7eb2e8f9f7	847	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	848	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	849	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	850	}
<>	144:ef7eb2e8f9f7	851	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	852	else
<>	144:ef7eb2e8f9f7	853	{
<>	144:ef7eb2e8f9f7	854	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	855	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	856	{
<>	144:ef7eb2e8f9f7	857	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	858	}
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	861	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/* Read data from DR */
<>	144:ef7eb2e8f9f7	864	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	865	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	866	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	869	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	870	{
<>	144:ef7eb2e8f9f7	871	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	872	}
<>	144:ef7eb2e8f9f7	873
<>	144:ef7eb2e8f9f7	874	/* Generate Stop */
<>	144:ef7eb2e8f9f7	875	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	876
<>	144:ef7eb2e8f9f7	877	/* Read data from DR */
<>	144:ef7eb2e8f9f7	878	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	879	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	880	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/* Read data from DR */
<>	144:ef7eb2e8f9f7	883	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	884	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	885	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	886	}
<>	144:ef7eb2e8f9f7	887	}
<>	144:ef7eb2e8f9f7	888	else
<>	144:ef7eb2e8f9f7	889	{
<>	144:ef7eb2e8f9f7	890	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	891	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	892	{
<>	144:ef7eb2e8f9f7	893	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	894	{
<>	144:ef7eb2e8f9f7	895	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	896	}
<>	144:ef7eb2e8f9f7	897	else
<>	144:ef7eb2e8f9f7	898	{
<>	144:ef7eb2e8f9f7	899	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	900	}
<>	144:ef7eb2e8f9f7	901	}
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/* Read data from DR */
<>	144:ef7eb2e8f9f7	904	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	905	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	906	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	909	{
<>	144:ef7eb2e8f9f7	910	/* Read data from DR */
<>	144:ef7eb2e8f9f7	911	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	912	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	913	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	914	}
<>	144:ef7eb2e8f9f7	915	}
<>	144:ef7eb2e8f9f7	916	}
<>	144:ef7eb2e8f9f7	917
<>	144:ef7eb2e8f9f7	918	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	919	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	922	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	return HAL_OK;
<>	144:ef7eb2e8f9f7	925	}
<>	144:ef7eb2e8f9f7	926	else
<>	144:ef7eb2e8f9f7	927	{
<>	144:ef7eb2e8f9f7	928	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	929	}
<>	144:ef7eb2e8f9f7	930	}
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	/**
<>	144:ef7eb2e8f9f7	933	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	934	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	935	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	936	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	937	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	938	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	939	* @retval HAL status
<>	144:ef7eb2e8f9f7	940	*/
<>	144:ef7eb2e8f9f7	941	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	942	{
<>	144:ef7eb2e8f9f7	943	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	946	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	949	{
<>	144:ef7eb2e8f9f7	950	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	951	{
<>	144:ef7eb2e8f9f7	952	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	953	}
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	/* Process Locked */
<>	144:ef7eb2e8f9f7	956	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	959	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	960	{
<>	144:ef7eb2e8f9f7	961	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	962	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	963	}
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	/* Disable Pos */
<>	144:ef7eb2e8f9f7	966	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	969	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	970	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	973	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	974	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	975	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	976	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	977
<>	144:ef7eb2e8f9f7	978	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	979	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	980
<>	144:ef7eb2e8f9f7	981	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	982	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	983	{
<>	144:ef7eb2e8f9f7	984	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	985	}
<>	144:ef7eb2e8f9f7	986
<>	144:ef7eb2e8f9f7	987	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	988	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	991	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	992	{
<>	144:ef7eb2e8f9f7	993	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	994	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	995	{
<>	144:ef7eb2e8f9f7	996	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1000	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1001	}
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1004	{
<>	144:ef7eb2e8f9f7	1005	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	1006	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1007	{
<>	144:ef7eb2e8f9f7	1008	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1009	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1010
<>	144:ef7eb2e8f9f7	1011	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1012	{
<>	144:ef7eb2e8f9f7	1013	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1014	}
<>	144:ef7eb2e8f9f7	1015	else
<>	144:ef7eb2e8f9f7	1016	{
<>	144:ef7eb2e8f9f7	1017	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1018	}
<>	144:ef7eb2e8f9f7	1019	}
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	/* Write data to DR */
<>	144:ef7eb2e8f9f7	1022	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	1023	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1024	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	1027	{
<>	144:ef7eb2e8f9f7	1028	/* Write data to DR */
<>	144:ef7eb2e8f9f7	1029	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	1030	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1031	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1032	}
<>	144:ef7eb2e8f9f7	1033	}
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Wait until AF flag is set */
<>	144:ef7eb2e8f9f7	1036	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1037	{
<>	144:ef7eb2e8f9f7	1038	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1039	}
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	1042	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1045	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1048	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1051	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	return HAL_OK;
<>	144:ef7eb2e8f9f7	1054	}
<>	144:ef7eb2e8f9f7	1055	else
<>	144:ef7eb2e8f9f7	1056	{
<>	144:ef7eb2e8f9f7	1057	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1058	}
<>	144:ef7eb2e8f9f7	1059	}
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/**
<>	144:ef7eb2e8f9f7	1062	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	1063	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1064	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1065	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1066	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1067	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1068	* @retval HAL status
<>	144:ef7eb2e8f9f7	1069	*/
<>	144:ef7eb2e8f9f7	1070	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1071	{
<>	144:ef7eb2e8f9f7	1072	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	1075	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1078	{
<>	144:ef7eb2e8f9f7	1079	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1080	{
<>	144:ef7eb2e8f9f7	1081	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1082	}
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	/* Process Locked */
<>	144:ef7eb2e8f9f7	1085	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1088	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1089	{
<>	144:ef7eb2e8f9f7	1090	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1091	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1092	}
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1095	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1098	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1099	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1102	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1103	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1104	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1105	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1108	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1109
<>	144:ef7eb2e8f9f7	1110	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	1111	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1112	{
<>	144:ef7eb2e8f9f7	1113	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1114	}
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1117	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1120	{
<>	144:ef7eb2e8f9f7	1121	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	1122	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1123	{
<>	144:ef7eb2e8f9f7	1124	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1125	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1126
<>	144:ef7eb2e8f9f7	1127	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	1128	{
<>	144:ef7eb2e8f9f7	1129	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1130	}
<>	144:ef7eb2e8f9f7	1131	else
<>	144:ef7eb2e8f9f7	1132	{
<>	144:ef7eb2e8f9f7	1133	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1134	}
<>	144:ef7eb2e8f9f7	1135	}
<>	144:ef7eb2e8f9f7	1136
<>	144:ef7eb2e8f9f7	1137	/* Read data from DR */
<>	144:ef7eb2e8f9f7	1138	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	1139	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1140	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	1143	{
<>	144:ef7eb2e8f9f7	1144	/* Read data from DR */
<>	144:ef7eb2e8f9f7	1145	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	1146	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1147	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1148	}
<>	144:ef7eb2e8f9f7	1149	}
<>	144:ef7eb2e8f9f7	1150
<>	144:ef7eb2e8f9f7	1151	/* Wait until STOP flag is set */
<>	144:ef7eb2e8f9f7	1152	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1153	{
<>	144:ef7eb2e8f9f7	1154	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1155	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1158	{
<>	144:ef7eb2e8f9f7	1159	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1160	}
<>	144:ef7eb2e8f9f7	1161	else
<>	144:ef7eb2e8f9f7	1162	{
<>	144:ef7eb2e8f9f7	1163	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165	}
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	1168	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1171	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1174	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1177	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	return HAL_OK;
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181	else
<>	144:ef7eb2e8f9f7	1182	{
<>	144:ef7eb2e8f9f7	1183	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1184	}
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186
<>	144:ef7eb2e8f9f7	1187	/**
<>	144:ef7eb2e8f9f7	1188	* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1189	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1190	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1191	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1192	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1193	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1194	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1195	* @retval HAL status
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1198	{
<>	144:ef7eb2e8f9f7	1199	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1202	{
<>	144:ef7eb2e8f9f7	1203	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1204	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1205	do
<>	144:ef7eb2e8f9f7	1206	{
<>	144:ef7eb2e8f9f7	1207	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1208	{
<>	144:ef7eb2e8f9f7	1209	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1210	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1213	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1216	}
<>	144:ef7eb2e8f9f7	1217	}
<>	144:ef7eb2e8f9f7	1218	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/* Process Locked */
<>	144:ef7eb2e8f9f7	1221	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1224	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1225	{
<>	144:ef7eb2e8f9f7	1226	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1227	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1228	}
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1231	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1234	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1235	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1238	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1239	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1240	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1241	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1242	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/* Generate Start */
<>	144:ef7eb2e8f9f7	1245	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1248	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1251	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1252	process unlock */
<>	144:ef7eb2e8f9f7	1253	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1254	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	return HAL_OK;
<>	144:ef7eb2e8f9f7	1257	}
<>	144:ef7eb2e8f9f7	1258	else
<>	144:ef7eb2e8f9f7	1259	{
<>	144:ef7eb2e8f9f7	1260	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1261	}
<>	144:ef7eb2e8f9f7	1262	}
<>	144:ef7eb2e8f9f7	1263
<>	144:ef7eb2e8f9f7	1264	/**
<>	144:ef7eb2e8f9f7	1265	* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1266	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1267	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1268	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1269	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1270	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1271	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1272	* @retval HAL status
<>	144:ef7eb2e8f9f7	1273	*/
<>	144:ef7eb2e8f9f7	1274	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1275	{
<>	144:ef7eb2e8f9f7	1276	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1279	{
<>	144:ef7eb2e8f9f7	1280	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1281	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1282	do
<>	144:ef7eb2e8f9f7	1283	{
<>	144:ef7eb2e8f9f7	1284	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1285	{
<>	144:ef7eb2e8f9f7	1286	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1287	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1288
<>	144:ef7eb2e8f9f7	1289	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1290	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1293	}
<>	144:ef7eb2e8f9f7	1294	}
<>	144:ef7eb2e8f9f7	1295	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/* Process Locked */
<>	144:ef7eb2e8f9f7	1298	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1301	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1302	{
<>	144:ef7eb2e8f9f7	1303	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1304	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1305	}
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1308	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1311	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1312	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1315	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1316	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1317	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1318	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1319	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1322	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Generate Start */
<>	144:ef7eb2e8f9f7	1325	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1328	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1329
<>	144:ef7eb2e8f9f7	1330	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1331	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1332	process unlock */
<>	144:ef7eb2e8f9f7	1333
<>	144:ef7eb2e8f9f7	1334	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1335	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	return HAL_OK;
<>	144:ef7eb2e8f9f7	1338	}
<>	144:ef7eb2e8f9f7	1339	else
<>	144:ef7eb2e8f9f7	1340	{
<>	144:ef7eb2e8f9f7	1341	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343	}
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	/**
<>	144:ef7eb2e8f9f7	1346	* @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1347	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1348	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1349	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1350	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1351	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1352	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1353	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1354	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1355	* @retval HAL status
<>	144:ef7eb2e8f9f7	1356	*/
<>	144:ef7eb2e8f9f7	1357	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1358	{
<>	144:ef7eb2e8f9f7	1359	__IO uint32_t Prev_State = 0x00U;
<>	144:ef7eb2e8f9f7	1360	__IO uint32_t count = 0x00U;
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1363	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1366	{
<>	144:ef7eb2e8f9f7	1367	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1368	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1369	{
<>	144:ef7eb2e8f9f7	1370	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1371	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1372	do
<>	144:ef7eb2e8f9f7	1373	{
<>	144:ef7eb2e8f9f7	1374	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1375	{
<>	144:ef7eb2e8f9f7	1376	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1377	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1380	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1386	}
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Process Locked */
<>	144:ef7eb2e8f9f7	1389	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1392	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1393	{
<>	144:ef7eb2e8f9f7	1394	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1395	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1396	}
<>	144:ef7eb2e8f9f7	1397
<>	144:ef7eb2e8f9f7	1398	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1399	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1402	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1403	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1406	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1407	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1408	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1409	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1410	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	Prev_State = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	/* Generate Start */
<>	144:ef7eb2e8f9f7	1415	if((Prev_State == I2C_STATE_MASTER_BUSY_RX) \|\| (Prev_State == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1416	{
<>	144:ef7eb2e8f9f7	1417	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	1418	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1419	{
<>	144:ef7eb2e8f9f7	1420	/* Generate Start */
<>	144:ef7eb2e8f9f7	1421	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1422	}
<>	144:ef7eb2e8f9f7	1423	else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	1426	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1427	}
<>	144:ef7eb2e8f9f7	1428	}
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1431	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1434	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1435	process unlock */
<>	144:ef7eb2e8f9f7	1436
<>	144:ef7eb2e8f9f7	1437	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1438	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1439
<>	144:ef7eb2e8f9f7	1440	return HAL_OK;
<>	144:ef7eb2e8f9f7	1441	}
<>	144:ef7eb2e8f9f7	1442	else
<>	144:ef7eb2e8f9f7	1443	{
<>	144:ef7eb2e8f9f7	1444	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446	}
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	/**
<>	144:ef7eb2e8f9f7	1449	* @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1450	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1451	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1452	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1453	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1454	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1455	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1456	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1457	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1458	* @retval HAL status
<>	144:ef7eb2e8f9f7	1459	*/
<>	144:ef7eb2e8f9f7	1460	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1461	{
<>	144:ef7eb2e8f9f7	1462	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1465	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1466
<>	144:ef7eb2e8f9f7	1467	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1468	{
<>	144:ef7eb2e8f9f7	1469	/* Check Busy Flag only if FIRST call of Master interface */
<>	144:ef7eb2e8f9f7	1470	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	144:ef7eb2e8f9f7	1471	{
<>	144:ef7eb2e8f9f7	1472	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1473	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1474	do
<>	144:ef7eb2e8f9f7	1475	{
<>	144:ef7eb2e8f9f7	1476	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1477	{
<>	144:ef7eb2e8f9f7	1478	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1479	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1482	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1485	}
<>	144:ef7eb2e8f9f7	1486	}
<>	144:ef7eb2e8f9f7	1487	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/* Process Locked */
<>	144:ef7eb2e8f9f7	1491	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1492
<>	144:ef7eb2e8f9f7	1493	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1494	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1495	{
<>	144:ef7eb2e8f9f7	1496	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1497	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1498	}
<>	144:ef7eb2e8f9f7	1499
<>	144:ef7eb2e8f9f7	1500	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1501	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1502
<>	144:ef7eb2e8f9f7	1503	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1504	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1505	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1506
<>	144:ef7eb2e8f9f7	1507	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1508	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1509	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1510	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1511	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1512	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->PreviousState == I2C_STATE_NONE))
<>	144:ef7eb2e8f9f7	1515	{
<>	144:ef7eb2e8f9f7	1516	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	1517	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME) \|\| (XferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	1518	{
<>	144:ef7eb2e8f9f7	1519	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1520	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Generate Start */
<>	144:ef7eb2e8f9f7	1523	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1524	}
<>	144:ef7eb2e8f9f7	1525	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	144:ef7eb2e8f9f7	1526	{
<>	144:ef7eb2e8f9f7	1527	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1528	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1529
<>	144:ef7eb2e8f9f7	1530	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	1531	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1532	}
<>	144:ef7eb2e8f9f7	1533	}
<>	144:ef7eb2e8f9f7	1534
<>	144:ef7eb2e8f9f7	1535	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1536	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1537
<>	144:ef7eb2e8f9f7	1538	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1539	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1540	process unlock */
<>	144:ef7eb2e8f9f7	1541
<>	144:ef7eb2e8f9f7	1542	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1543	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1544
<>	144:ef7eb2e8f9f7	1545	return HAL_OK;
<>	144:ef7eb2e8f9f7	1546	}
<>	144:ef7eb2e8f9f7	1547	else
<>	144:ef7eb2e8f9f7	1548	{
<>	144:ef7eb2e8f9f7	1549	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1550	}
<>	144:ef7eb2e8f9f7	1551	}
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	/**
<>	144:ef7eb2e8f9f7	1554	* @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1555	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1556	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1557	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1558	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1559	* @retval HAL status
<>	144:ef7eb2e8f9f7	1560	*/
<>	144:ef7eb2e8f9f7	1561	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1562	{
<>	144:ef7eb2e8f9f7	1563	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1564
<>	144:ef7eb2e8f9f7	1565	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1566	{
<>	144:ef7eb2e8f9f7	1567	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1568	{
<>	144:ef7eb2e8f9f7	1569	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1573	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1574	do
<>	144:ef7eb2e8f9f7	1575	{
<>	144:ef7eb2e8f9f7	1576	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1577	{
<>	144:ef7eb2e8f9f7	1578	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1579	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1582	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1583
<>	144:ef7eb2e8f9f7	1584	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1585	}
<>	144:ef7eb2e8f9f7	1586	}
<>	144:ef7eb2e8f9f7	1587	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1588
<>	144:ef7eb2e8f9f7	1589	/* Process Locked */
<>	144:ef7eb2e8f9f7	1590	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1593	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1594	{
<>	144:ef7eb2e8f9f7	1595	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1596	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1597	}
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1600	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1603	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1604	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1605
<>	144:ef7eb2e8f9f7	1606	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1607	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1608	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1609	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1610	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1611
<>	144:ef7eb2e8f9f7	1612	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1613	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1614
<>	144:ef7eb2e8f9f7	1615	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1616	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1619	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1620	process unlock */
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1623	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	return HAL_OK;
<>	144:ef7eb2e8f9f7	1626	}
<>	144:ef7eb2e8f9f7	1627	else
<>	144:ef7eb2e8f9f7	1628	{
<>	144:ef7eb2e8f9f7	1629	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1630	}
<>	144:ef7eb2e8f9f7	1631	}
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	/**
<>	144:ef7eb2e8f9f7	1634	* @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1635	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1636	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1637	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1638	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1639	* @retval HAL status
<>	144:ef7eb2e8f9f7	1640	*/
<>	144:ef7eb2e8f9f7	1641	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1642	{
<>	144:ef7eb2e8f9f7	1643	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1646	{
<>	144:ef7eb2e8f9f7	1647	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1648	{
<>	144:ef7eb2e8f9f7	1649	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1650	}
<>	144:ef7eb2e8f9f7	1651
<>	144:ef7eb2e8f9f7	1652	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1653	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1654	do
<>	144:ef7eb2e8f9f7	1655	{
<>	144:ef7eb2e8f9f7	1656	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1659	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1662	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1665	}
<>	144:ef7eb2e8f9f7	1666	}
<>	144:ef7eb2e8f9f7	1667	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	/* Process Locked */
<>	144:ef7eb2e8f9f7	1670	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1673	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1674	{
<>	144:ef7eb2e8f9f7	1675	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1676	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1677	}
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1680	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1683	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1684	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1687	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1688	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	1689	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1690	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1691
<>	144:ef7eb2e8f9f7	1692	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1693	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1696	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1699	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1700	process unlock */
<>	144:ef7eb2e8f9f7	1701
<>	144:ef7eb2e8f9f7	1702	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1703	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1704
<>	144:ef7eb2e8f9f7	1705	return HAL_OK;
<>	144:ef7eb2e8f9f7	1706	}
<>	144:ef7eb2e8f9f7	1707	else
<>	144:ef7eb2e8f9f7	1708	{
<>	144:ef7eb2e8f9f7	1709	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1710	}
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/**
<>	144:ef7eb2e8f9f7	1714	* @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1715	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1716	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1717	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	1718	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1719	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1720	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1721	* @retval HAL status
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1724	{
<>	144:ef7eb2e8f9f7	1725	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1726	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1729	{
<>	144:ef7eb2e8f9f7	1730	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1731	{
<>	144:ef7eb2e8f9f7	1732	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1733	}
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/* Process Locked */
<>	144:ef7eb2e8f9f7	1736	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1737
<>	144:ef7eb2e8f9f7	1738	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1739	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1740	{
<>	144:ef7eb2e8f9f7	1741	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1742	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1743	}
<>	144:ef7eb2e8f9f7	1744
<>	144:ef7eb2e8f9f7	1745	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1746	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1747
<>	144:ef7eb2e8f9f7	1748	hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
<>	144:ef7eb2e8f9f7	1749	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1750	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1751
<>	144:ef7eb2e8f9f7	1752	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1753	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1754	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1755	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1756	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1757
<>	144:ef7eb2e8f9f7	1758	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1759	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1762	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1765	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1766	process unlock */
<>	144:ef7eb2e8f9f7	1767
<>	144:ef7eb2e8f9f7	1768	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1769	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	return HAL_OK;
<>	144:ef7eb2e8f9f7	1772	}
<>	144:ef7eb2e8f9f7	1773	else
<>	144:ef7eb2e8f9f7	1774	{
<>	144:ef7eb2e8f9f7	1775	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1776	}
<>	144:ef7eb2e8f9f7	1777	}
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	/**
<>	144:ef7eb2e8f9f7	1780	* @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1781	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1782	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1783	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1784	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1785	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1786	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	1787	* @retval HAL status
<>	144:ef7eb2e8f9f7	1788	*/
<>	144:ef7eb2e8f9f7	1789	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	144:ef7eb2e8f9f7	1790	{
<>	144:ef7eb2e8f9f7	1791	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1792	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1795	{
<>	144:ef7eb2e8f9f7	1796	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1797	{
<>	144:ef7eb2e8f9f7	1798	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1799	}
<>	144:ef7eb2e8f9f7	1800
<>	144:ef7eb2e8f9f7	1801	/* Process Locked */
<>	144:ef7eb2e8f9f7	1802	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1805	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1806	{
<>	144:ef7eb2e8f9f7	1807	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1808	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1809	}
<>	144:ef7eb2e8f9f7	1810
<>	144:ef7eb2e8f9f7	1811	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1812	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1813
<>	144:ef7eb2e8f9f7	1814	hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
<>	144:ef7eb2e8f9f7	1815	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1816	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1817
<>	144:ef7eb2e8f9f7	1818	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1819	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1820	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1821	hi2c->XferOptions = XferOptions;
<>	144:ef7eb2e8f9f7	1822	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1823
<>	144:ef7eb2e8f9f7	1824	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1825	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1826
<>	144:ef7eb2e8f9f7	1827	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1828	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1831	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1832	process unlock */
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1835	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1836
<>	144:ef7eb2e8f9f7	1837	return HAL_OK;
<>	144:ef7eb2e8f9f7	1838	}
<>	144:ef7eb2e8f9f7	1839	else
<>	144:ef7eb2e8f9f7	1840	{
<>	144:ef7eb2e8f9f7	1841	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1842	}
<>	144:ef7eb2e8f9f7	1843	}
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	/**
<>	144:ef7eb2e8f9f7	1846	* @brief Enable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1847	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1848	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1849	* @retval HAL status
<>	144:ef7eb2e8f9f7	1850	*/
<>	144:ef7eb2e8f9f7	1851	HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1852	{
<>	144:ef7eb2e8f9f7	1853	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1854	{
<>	144:ef7eb2e8f9f7	1855	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	1856
<>	144:ef7eb2e8f9f7	1857	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1858	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1859	{
<>	144:ef7eb2e8f9f7	1860	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1861	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1862	}
<>	144:ef7eb2e8f9f7	1863
<>	144:ef7eb2e8f9f7	1864	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1865	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1866
<>	144:ef7eb2e8f9f7	1867	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1868	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	return HAL_OK;
<>	144:ef7eb2e8f9f7	1871	}
<>	144:ef7eb2e8f9f7	1872	else
<>	144:ef7eb2e8f9f7	1873	{
<>	144:ef7eb2e8f9f7	1874	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1875	}
<>	144:ef7eb2e8f9f7	1876	}
<>	144:ef7eb2e8f9f7	1877
<>	144:ef7eb2e8f9f7	1878	/**
<>	144:ef7eb2e8f9f7	1879	* @brief Disable the Address listen mode with Interrupt.
<>	144:ef7eb2e8f9f7	1880	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1881	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1882	* @retval HAL status
<>	144:ef7eb2e8f9f7	1883	*/
<>	144:ef7eb2e8f9f7	1884	HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	1885	{
<>	144:ef7eb2e8f9f7	1886	/* Declaration of tmp to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	1887	uint32_t tmp;
<>	144:ef7eb2e8f9f7	1888
<>	144:ef7eb2e8f9f7	1889	/* Disable Address listen mode only if a transfer is not ongoing */
<>	144:ef7eb2e8f9f7	1890	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	144:ef7eb2e8f9f7	1891	{
<>	144:ef7eb2e8f9f7	1892	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	144:ef7eb2e8f9f7	1893	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	1894	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1895	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1898	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1901	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1902
<>	144:ef7eb2e8f9f7	1903	return HAL_OK;
<>	144:ef7eb2e8f9f7	1904	}
<>	144:ef7eb2e8f9f7	1905	else
<>	144:ef7eb2e8f9f7	1906	{
<>	144:ef7eb2e8f9f7	1907	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1908	}
<>	144:ef7eb2e8f9f7	1909	}
<>	144:ef7eb2e8f9f7	1910
<>	144:ef7eb2e8f9f7	1911	/**
<>	144:ef7eb2e8f9f7	1912	* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1913	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1914	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1915	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	1916	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1917	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1918	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1919	* @retval HAL status
<>	144:ef7eb2e8f9f7	1920	*/
<>	144:ef7eb2e8f9f7	1921	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1922	{
<>	144:ef7eb2e8f9f7	1923	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	1924
<>	144:ef7eb2e8f9f7	1925	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1926	{
<>	144:ef7eb2e8f9f7	1927	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1928	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	1929	do
<>	144:ef7eb2e8f9f7	1930	{
<>	144:ef7eb2e8f9f7	1931	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	1932	{
<>	144:ef7eb2e8f9f7	1933	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	1934	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1935
<>	144:ef7eb2e8f9f7	1936	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1937	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1938
<>	144:ef7eb2e8f9f7	1939	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1940	}
<>	144:ef7eb2e8f9f7	1941	}
<>	144:ef7eb2e8f9f7	1942	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	/* Process Locked */
<>	144:ef7eb2e8f9f7	1945	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1946
<>	144:ef7eb2e8f9f7	1947	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	1948	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1949	{
<>	144:ef7eb2e8f9f7	1950	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	1951	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	1952	}
<>	144:ef7eb2e8f9f7	1953
<>	144:ef7eb2e8f9f7	1954	/* Disable Pos */
<>	144:ef7eb2e8f9f7	1955	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	1956
<>	144:ef7eb2e8f9f7	1957	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	1958	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1959	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1960
<>	144:ef7eb2e8f9f7	1961	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	1962	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1963	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	1964	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	1965	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1966	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	1967
<>	144:ef7eb2e8f9f7	1968	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1969	{
<>	144:ef7eb2e8f9f7	1970	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1971	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1972
<>	144:ef7eb2e8f9f7	1973	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1974	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	1975
<>	144:ef7eb2e8f9f7	1976	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	1977	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1978	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1979	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	1980	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	1983	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	1986	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1987
<>	144:ef7eb2e8f9f7	1988	/* Generate Start */
<>	144:ef7eb2e8f9f7	1989	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1990
<>	144:ef7eb2e8f9f7	1991	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1992	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1995	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1996	process unlock */
<>	144:ef7eb2e8f9f7	1997
<>	144:ef7eb2e8f9f7	1998	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	1999	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2000
<>	144:ef7eb2e8f9f7	2001	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2002	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2003	}
<>	144:ef7eb2e8f9f7	2004	else
<>	144:ef7eb2e8f9f7	2005	{
<>	144:ef7eb2e8f9f7	2006	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2007	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2008
<>	144:ef7eb2e8f9f7	2009	/* Generate Start */
<>	144:ef7eb2e8f9f7	2010	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2011
<>	144:ef7eb2e8f9f7	2012	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2013	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2014
<>	144:ef7eb2e8f9f7	2015	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2016	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2017	process unlock */
<>	144:ef7eb2e8f9f7	2018
<>	144:ef7eb2e8f9f7	2019	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2020	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2021	}
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	return HAL_OK;
<>	144:ef7eb2e8f9f7	2024	}
<>	144:ef7eb2e8f9f7	2025	else
<>	144:ef7eb2e8f9f7	2026	{
<>	144:ef7eb2e8f9f7	2027	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2028	}
<>	144:ef7eb2e8f9f7	2029	}
<>	144:ef7eb2e8f9f7	2030
<>	144:ef7eb2e8f9f7	2031	/**
<>	144:ef7eb2e8f9f7	2032	* @brief Receive in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2033	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2034	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2035	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	2036	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2037	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2038	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2039	* @retval HAL status
<>	144:ef7eb2e8f9f7	2040	*/
<>	144:ef7eb2e8f9f7	2041	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2042	{
<>	144:ef7eb2e8f9f7	2043	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2044
<>	144:ef7eb2e8f9f7	2045	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2046	{
<>	144:ef7eb2e8f9f7	2047	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2048	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2049	do
<>	144:ef7eb2e8f9f7	2050	{
<>	144:ef7eb2e8f9f7	2051	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2052	{
<>	144:ef7eb2e8f9f7	2053	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2054	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2055
<>	144:ef7eb2e8f9f7	2056	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2057	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2060	}
<>	144:ef7eb2e8f9f7	2061	}
<>	144:ef7eb2e8f9f7	2062	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2063
<>	144:ef7eb2e8f9f7	2064	/* Process Locked */
<>	144:ef7eb2e8f9f7	2065	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2068	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2069	{
<>	144:ef7eb2e8f9f7	2070	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2071	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2072	}
<>	144:ef7eb2e8f9f7	2073
<>	144:ef7eb2e8f9f7	2074	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2075	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2076
<>	144:ef7eb2e8f9f7	2077	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2078	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	2079	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2080
<>	144:ef7eb2e8f9f7	2081	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2082	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2083	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2084	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2085	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2086	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2087
<>	144:ef7eb2e8f9f7	2088	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2089	{
<>	144:ef7eb2e8f9f7	2090	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2091	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2092
<>	144:ef7eb2e8f9f7	2093	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2094	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2095
<>	144:ef7eb2e8f9f7	2096	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2097	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2098	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2099	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2100	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2101
<>	144:ef7eb2e8f9f7	2102	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2103	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2104
<>	144:ef7eb2e8f9f7	2105	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2106	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2107
<>	144:ef7eb2e8f9f7	2108	/* Generate Start */
<>	144:ef7eb2e8f9f7	2109	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2110
<>	144:ef7eb2e8f9f7	2111	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2112	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2113
<>	144:ef7eb2e8f9f7	2114	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2115	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2116	process unlock */
<>	144:ef7eb2e8f9f7	2117
<>	144:ef7eb2e8f9f7	2118	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	2119	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2122	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2123	}
<>	144:ef7eb2e8f9f7	2124	else
<>	144:ef7eb2e8f9f7	2125	{
<>	144:ef7eb2e8f9f7	2126	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2127	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	/* Generate Start */
<>	144:ef7eb2e8f9f7	2130	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2133	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2136	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2137	process unlock */
<>	144:ef7eb2e8f9f7	2138
<>	144:ef7eb2e8f9f7	2139	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2140	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2141	}
<>	144:ef7eb2e8f9f7	2142
<>	144:ef7eb2e8f9f7	2143	return HAL_OK;
<>	144:ef7eb2e8f9f7	2144	}
<>	144:ef7eb2e8f9f7	2145	else
<>	144:ef7eb2e8f9f7	2146	{
<>	144:ef7eb2e8f9f7	2147	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2148	}
<>	144:ef7eb2e8f9f7	2149	}
<>	144:ef7eb2e8f9f7	2150
<>	144:ef7eb2e8f9f7	2151	/**
<>	144:ef7eb2e8f9f7	2152	* @brief Abort a master I2C process communication with Interrupt.
<>	144:ef7eb2e8f9f7	2153	* @note This abort can be called only if state is ready
<>	144:ef7eb2e8f9f7	2154	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2155	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2156	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	2157	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2158	* @retval HAL status
<>	144:ef7eb2e8f9f7	2159	*/
<>	144:ef7eb2e8f9f7	2160	HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<>	144:ef7eb2e8f9f7	2161	{
<>	144:ef7eb2e8f9f7	2162	/* Abort Master transfer during Receive or Transmit process */
<>	144:ef7eb2e8f9f7	2163	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	144:ef7eb2e8f9f7	2164	{
<>	144:ef7eb2e8f9f7	2165	/* Process Locked */
<>	144:ef7eb2e8f9f7	2166	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2169	hi2c->State = HAL_I2C_STATE_ABORT;
<>	144:ef7eb2e8f9f7	2170
<>	144:ef7eb2e8f9f7	2171	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2172	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2173
<>	144:ef7eb2e8f9f7	2174	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2175	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2176
<>	144:ef7eb2e8f9f7	2177	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2180	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2181
<>	144:ef7eb2e8f9f7	2182	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2183	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2184
<>	144:ef7eb2e8f9f7	2185	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	2186	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	2187
<>	144:ef7eb2e8f9f7	2188	return HAL_OK;
<>	144:ef7eb2e8f9f7	2189	}
<>	144:ef7eb2e8f9f7	2190	else
<>	144:ef7eb2e8f9f7	2191	{
<>	144:ef7eb2e8f9f7	2192	/* Wrong usage of abort function */
<>	144:ef7eb2e8f9f7	2193	/* This function should be used only in case of abort monitored by master device */
<>	144:ef7eb2e8f9f7	2194	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2195	}
<>	144:ef7eb2e8f9f7	2196	}
<>	144:ef7eb2e8f9f7	2197
<>	144:ef7eb2e8f9f7	2198	/**
<>	144:ef7eb2e8f9f7	2199	* @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2200	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2201	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2202	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2203	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2204	* @retval HAL status
<>	144:ef7eb2e8f9f7	2205	*/
<>	144:ef7eb2e8f9f7	2206	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2207	{
<>	144:ef7eb2e8f9f7	2208	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2209
<>	144:ef7eb2e8f9f7	2210	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2211	{
<>	144:ef7eb2e8f9f7	2212	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2213	{
<>	144:ef7eb2e8f9f7	2214	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2215	}
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2218	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2219	do
<>	144:ef7eb2e8f9f7	2220	{
<>	144:ef7eb2e8f9f7	2221	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2222	{
<>	144:ef7eb2e8f9f7	2223	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2224	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2225
<>	144:ef7eb2e8f9f7	2226	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2227	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2228
<>	144:ef7eb2e8f9f7	2229	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2230	}
<>	144:ef7eb2e8f9f7	2231	}
<>	144:ef7eb2e8f9f7	2232	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2233
<>	144:ef7eb2e8f9f7	2234	/* Process Locked */
<>	144:ef7eb2e8f9f7	2235	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2236
<>	144:ef7eb2e8f9f7	2237	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2238	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2239	{
<>	144:ef7eb2e8f9f7	2240	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2241	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2242	}
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2245	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2246
<>	144:ef7eb2e8f9f7	2247	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2248	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2249	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2250
<>	144:ef7eb2e8f9f7	2251	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2252	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2253	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2254	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2255	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2256
<>	144:ef7eb2e8f9f7	2257	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2258	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2259
<>	144:ef7eb2e8f9f7	2260	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2261	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2262
<>	144:ef7eb2e8f9f7	2263	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2264	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2265	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2266	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2267	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2268
<>	144:ef7eb2e8f9f7	2269	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2270	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2271
<>	144:ef7eb2e8f9f7	2272	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2273	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2274
<>	144:ef7eb2e8f9f7	2275	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2276	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2277
<>	144:ef7eb2e8f9f7	2278	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2279	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2280	process unlock */
<>	144:ef7eb2e8f9f7	2281	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	2282	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2283
<>	144:ef7eb2e8f9f7	2284	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2285	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2286
<>	144:ef7eb2e8f9f7	2287	return HAL_OK;
<>	144:ef7eb2e8f9f7	2288	}
<>	144:ef7eb2e8f9f7	2289	else
<>	144:ef7eb2e8f9f7	2290	{
<>	144:ef7eb2e8f9f7	2291	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2292	}
<>	144:ef7eb2e8f9f7	2293	}
<>	144:ef7eb2e8f9f7	2294
<>	144:ef7eb2e8f9f7	2295	/**
<>	144:ef7eb2e8f9f7	2296	* @brief Receive in slave mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2297	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2298	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2299	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2300	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2301	* @retval HAL status
<>	144:ef7eb2e8f9f7	2302	*/
<>	144:ef7eb2e8f9f7	2303	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2304	{
<>	144:ef7eb2e8f9f7	2305	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2306
<>	144:ef7eb2e8f9f7	2307	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2308	{
<>	144:ef7eb2e8f9f7	2309	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2310	{
<>	144:ef7eb2e8f9f7	2311	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2312	}
<>	144:ef7eb2e8f9f7	2313
<>	144:ef7eb2e8f9f7	2314	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2315	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2316	do
<>	144:ef7eb2e8f9f7	2317	{
<>	144:ef7eb2e8f9f7	2318	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2319	{
<>	144:ef7eb2e8f9f7	2320	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2321	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2322
<>	144:ef7eb2e8f9f7	2323	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2324	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2325
<>	144:ef7eb2e8f9f7	2326	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2327	}
<>	144:ef7eb2e8f9f7	2328	}
<>	144:ef7eb2e8f9f7	2329	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2330
<>	144:ef7eb2e8f9f7	2331	/* Process Locked */
<>	144:ef7eb2e8f9f7	2332	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2333
<>	144:ef7eb2e8f9f7	2334	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2335	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2336	{
<>	144:ef7eb2e8f9f7	2337	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2338	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2339	}
<>	144:ef7eb2e8f9f7	2340
<>	144:ef7eb2e8f9f7	2341	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2342	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2343
<>	144:ef7eb2e8f9f7	2344	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2345	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	2346	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2347
<>	144:ef7eb2e8f9f7	2348	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2349	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2350	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2351	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2352	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2353
<>	144:ef7eb2e8f9f7	2354	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	2355	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	2356
<>	144:ef7eb2e8f9f7	2357	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	2358	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	2359
<>	144:ef7eb2e8f9f7	2360	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	2361	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2362	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2363	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	2364	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	2365
<>	144:ef7eb2e8f9f7	2366	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	2367	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	2368
<>	144:ef7eb2e8f9f7	2369	/* Enable Address Acknowledge */
<>	144:ef7eb2e8f9f7	2370	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2371
<>	144:ef7eb2e8f9f7	2372	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2373	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2374
<>	144:ef7eb2e8f9f7	2375	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2376	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2377	process unlock */
<>	144:ef7eb2e8f9f7	2378	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	2379	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2380
<>	144:ef7eb2e8f9f7	2381	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	2382	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2383
<>	144:ef7eb2e8f9f7	2384	return HAL_OK;
<>	144:ef7eb2e8f9f7	2385	}
<>	144:ef7eb2e8f9f7	2386	else
<>	144:ef7eb2e8f9f7	2387	{
<>	144:ef7eb2e8f9f7	2388	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2389	}
<>	144:ef7eb2e8f9f7	2390	}
<>	144:ef7eb2e8f9f7	2391	/**
<>	144:ef7eb2e8f9f7	2392	* @brief Write an amount of data in blocking mode to a specific memory address
<>	144:ef7eb2e8f9f7	2393	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2394	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2395	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2396	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2397	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2398	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2399	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2400	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2401	* @retval HAL status
<>	144:ef7eb2e8f9f7	2402	*/
<>	144:ef7eb2e8f9f7	2403	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2404	{
<>	144:ef7eb2e8f9f7	2405	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2406
<>	144:ef7eb2e8f9f7	2407	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2408	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2409
<>	144:ef7eb2e8f9f7	2410	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2411	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2412
<>	144:ef7eb2e8f9f7	2413	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2414	{
<>	144:ef7eb2e8f9f7	2415	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2416	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2417	{
<>	144:ef7eb2e8f9f7	2418	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420
<>	144:ef7eb2e8f9f7	2421	/* Process Locked */
<>	144:ef7eb2e8f9f7	2422	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2423
<>	144:ef7eb2e8f9f7	2424	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2425	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2426	{
<>	144:ef7eb2e8f9f7	2427	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2428	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2429	}
<>	144:ef7eb2e8f9f7	2430
<>	144:ef7eb2e8f9f7	2431	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2432	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2433
<>	144:ef7eb2e8f9f7	2434	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2435	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2436	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2439	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2440	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2441	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2442	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2443
<>	144:ef7eb2e8f9f7	2444	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2445	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2446	{
<>	144:ef7eb2e8f9f7	2447	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2448	{
<>	144:ef7eb2e8f9f7	2449	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2450	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2451	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2452	}
<>	144:ef7eb2e8f9f7	2453	else
<>	144:ef7eb2e8f9f7	2454	{
<>	144:ef7eb2e8f9f7	2455	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2456	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2457	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2458	}
<>	144:ef7eb2e8f9f7	2459	}
<>	144:ef7eb2e8f9f7	2460
<>	144:ef7eb2e8f9f7	2461	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2462	{
<>	144:ef7eb2e8f9f7	2463	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	2464	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2465	{
<>	144:ef7eb2e8f9f7	2466	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2467	{
<>	144:ef7eb2e8f9f7	2468	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2469	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2470	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472	else
<>	144:ef7eb2e8f9f7	2473	{
<>	144:ef7eb2e8f9f7	2474	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2475	}
<>	144:ef7eb2e8f9f7	2476	}
<>	144:ef7eb2e8f9f7	2477
<>	144:ef7eb2e8f9f7	2478	/* Write data to DR */
<>	144:ef7eb2e8f9f7	2479	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	2480	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2481	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2482
<>	144:ef7eb2e8f9f7	2483	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	2484	{
<>	144:ef7eb2e8f9f7	2485	/* Write data to DR */
<>	144:ef7eb2e8f9f7	2486	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	2487	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2488	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2489	}
<>	144:ef7eb2e8f9f7	2490	}
<>	144:ef7eb2e8f9f7	2491
<>	144:ef7eb2e8f9f7	2492	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2493	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2494	{
<>	144:ef7eb2e8f9f7	2495	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2496	{
<>	144:ef7eb2e8f9f7	2497	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2498	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2499	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2500	}
<>	144:ef7eb2e8f9f7	2501	else
<>	144:ef7eb2e8f9f7	2502	{
<>	144:ef7eb2e8f9f7	2503	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2504	}
<>	144:ef7eb2e8f9f7	2505	}
<>	144:ef7eb2e8f9f7	2506
<>	144:ef7eb2e8f9f7	2507	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2508	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2509
<>	144:ef7eb2e8f9f7	2510	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2511	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2514	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2515
<>	144:ef7eb2e8f9f7	2516	return HAL_OK;
<>	144:ef7eb2e8f9f7	2517	}
<>	144:ef7eb2e8f9f7	2518	else
<>	144:ef7eb2e8f9f7	2519	{
<>	144:ef7eb2e8f9f7	2520	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2521	}
<>	144:ef7eb2e8f9f7	2522	}
<>	144:ef7eb2e8f9f7	2523
<>	144:ef7eb2e8f9f7	2524	/**
<>	144:ef7eb2e8f9f7	2525	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	2526	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2527	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2528	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2529	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2530	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2531	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2532	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2533	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2534	* @retval HAL status
<>	144:ef7eb2e8f9f7	2535	*/
<>	144:ef7eb2e8f9f7	2536	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2537	{
<>	144:ef7eb2e8f9f7	2538	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2539
<>	144:ef7eb2e8f9f7	2540	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2541	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2542
<>	144:ef7eb2e8f9f7	2543	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2544	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2545
<>	144:ef7eb2e8f9f7	2546	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2547	{
<>	144:ef7eb2e8f9f7	2548	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2549	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2550	{
<>	144:ef7eb2e8f9f7	2551	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2552	}
<>	144:ef7eb2e8f9f7	2553
<>	144:ef7eb2e8f9f7	2554	/* Process Locked */
<>	144:ef7eb2e8f9f7	2555	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2556
<>	144:ef7eb2e8f9f7	2557	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2558	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2559	{
<>	144:ef7eb2e8f9f7	2560	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2561	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2562	}
<>	144:ef7eb2e8f9f7	2563
<>	144:ef7eb2e8f9f7	2564	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2565	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2566
<>	144:ef7eb2e8f9f7	2567	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2568	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2569	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2572	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2573	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2574	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2575	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	2576
<>	144:ef7eb2e8f9f7	2577	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	2578	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2579	{
<>	144:ef7eb2e8f9f7	2580	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2581	{
<>	144:ef7eb2e8f9f7	2582	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2583	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2584	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2585	}
<>	144:ef7eb2e8f9f7	2586	else
<>	144:ef7eb2e8f9f7	2587	{
<>	144:ef7eb2e8f9f7	2588	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2589	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2590	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2591	}
<>	144:ef7eb2e8f9f7	2592	}
<>	144:ef7eb2e8f9f7	2593
<>	144:ef7eb2e8f9f7	2594	if(hi2c->XferSize == 0U)
<>	144:ef7eb2e8f9f7	2595	{
<>	144:ef7eb2e8f9f7	2596	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2597	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2598
<>	144:ef7eb2e8f9f7	2599	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2600	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2601	}
<>	144:ef7eb2e8f9f7	2602	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	2603	{
<>	144:ef7eb2e8f9f7	2604	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2605	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2606
<>	144:ef7eb2e8f9f7	2607	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2608	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2609
<>	144:ef7eb2e8f9f7	2610	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2611	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2612	}
<>	144:ef7eb2e8f9f7	2613	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	2614	{
<>	144:ef7eb2e8f9f7	2615	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2616	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	/* Enable Pos */
<>	144:ef7eb2e8f9f7	2619	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2620
<>	144:ef7eb2e8f9f7	2621	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2622	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2623	}
<>	144:ef7eb2e8f9f7	2624	else
<>	144:ef7eb2e8f9f7	2625	{
<>	144:ef7eb2e8f9f7	2626	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2627	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2628	}
<>	144:ef7eb2e8f9f7	2629
<>	144:ef7eb2e8f9f7	2630	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2631	{
<>	144:ef7eb2e8f9f7	2632	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	2633	{
<>	144:ef7eb2e8f9f7	2634	/* One byte */
<>	144:ef7eb2e8f9f7	2635	if(hi2c->XferSize== 1U)
<>	144:ef7eb2e8f9f7	2636	{
<>	144:ef7eb2e8f9f7	2637	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2638	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2639	{
<>	144:ef7eb2e8f9f7	2640	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2641	{
<>	144:ef7eb2e8f9f7	2642	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2643	}
<>	144:ef7eb2e8f9f7	2644	else
<>	144:ef7eb2e8f9f7	2645	{
<>	144:ef7eb2e8f9f7	2646	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2647	}
<>	144:ef7eb2e8f9f7	2648	}
<>	144:ef7eb2e8f9f7	2649
<>	144:ef7eb2e8f9f7	2650	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2651	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2652	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2653	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2654	}
<>	144:ef7eb2e8f9f7	2655	/* Two bytes */
<>	144:ef7eb2e8f9f7	2656	else if(Size == 2U)
<>	144:ef7eb2e8f9f7	2657	{
<>	144:ef7eb2e8f9f7	2658	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2659	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2660	{
<>	144:ef7eb2e8f9f7	2661	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2662	}
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2665	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2666
<>	144:ef7eb2e8f9f7	2667	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2668	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2669	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2670	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2671
<>	144:ef7eb2e8f9f7	2672	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2673	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2674	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2675	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2676	}
<>	144:ef7eb2e8f9f7	2677	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	2678	else
<>	144:ef7eb2e8f9f7	2679	{
<>	144:ef7eb2e8f9f7	2680	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2681	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2682	{
<>	144:ef7eb2e8f9f7	2683	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2684	}
<>	144:ef7eb2e8f9f7	2685
<>	144:ef7eb2e8f9f7	2686	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	2687	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2688
<>	144:ef7eb2e8f9f7	2689	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2690	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2691	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2692	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2693
<>	144:ef7eb2e8f9f7	2694	/* Wait until BTF flag is set */
<>	144:ef7eb2e8f9f7	2695	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2696	{
<>	144:ef7eb2e8f9f7	2697	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2698	}
<>	144:ef7eb2e8f9f7	2699
<>	144:ef7eb2e8f9f7	2700	/* Generate Stop */
<>	144:ef7eb2e8f9f7	2701	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2702
<>	144:ef7eb2e8f9f7	2703	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2704	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2705	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2706	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2707
<>	144:ef7eb2e8f9f7	2708	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2709	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2710	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2711	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2712	}
<>	144:ef7eb2e8f9f7	2713	}
<>	144:ef7eb2e8f9f7	2714	else
<>	144:ef7eb2e8f9f7	2715	{
<>	144:ef7eb2e8f9f7	2716	/* Wait until RXNE flag is set */
<>	144:ef7eb2e8f9f7	2717	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2718	{
<>	144:ef7eb2e8f9f7	2719	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2720	{
<>	144:ef7eb2e8f9f7	2721	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2722	}
<>	144:ef7eb2e8f9f7	2723	else
<>	144:ef7eb2e8f9f7	2724	{
<>	144:ef7eb2e8f9f7	2725	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2726	}
<>	144:ef7eb2e8f9f7	2727	}
<>	144:ef7eb2e8f9f7	2728
<>	144:ef7eb2e8f9f7	2729	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2730	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2731	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2732	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2733
<>	144:ef7eb2e8f9f7	2734	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	2735	{
<>	144:ef7eb2e8f9f7	2736	/* Read data from DR */
<>	144:ef7eb2e8f9f7	2737	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	2738	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	2739	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2740	}
<>	144:ef7eb2e8f9f7	2741	}
<>	144:ef7eb2e8f9f7	2742	}
<>	144:ef7eb2e8f9f7	2743
<>	144:ef7eb2e8f9f7	2744	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2745	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	2746
<>	144:ef7eb2e8f9f7	2747	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2748	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2749
<>	144:ef7eb2e8f9f7	2750	return HAL_OK;
<>	144:ef7eb2e8f9f7	2751	}
<>	144:ef7eb2e8f9f7	2752	else
<>	144:ef7eb2e8f9f7	2753	{
<>	144:ef7eb2e8f9f7	2754	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2755	}
<>	144:ef7eb2e8f9f7	2756	}
<>	144:ef7eb2e8f9f7	2757
<>	144:ef7eb2e8f9f7	2758	/**
<>	144:ef7eb2e8f9f7	2759	* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	2760	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2761	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2762	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2763	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2764	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2765	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2766	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2767	* @retval HAL status
<>	144:ef7eb2e8f9f7	2768	*/
<>	144:ef7eb2e8f9f7	2769	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2770	{
<>	144:ef7eb2e8f9f7	2771	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2772
<>	144:ef7eb2e8f9f7	2773	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2774	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2775
<>	144:ef7eb2e8f9f7	2776	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2777	{
<>	144:ef7eb2e8f9f7	2778	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2779	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2780	do
<>	144:ef7eb2e8f9f7	2781	{
<>	144:ef7eb2e8f9f7	2782	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2785	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2786
<>	144:ef7eb2e8f9f7	2787	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2788	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2789
<>	144:ef7eb2e8f9f7	2790	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2791	}
<>	144:ef7eb2e8f9f7	2792	}
<>	144:ef7eb2e8f9f7	2793	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2794
<>	144:ef7eb2e8f9f7	2795	/* Process Locked */
<>	144:ef7eb2e8f9f7	2796	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2797
<>	144:ef7eb2e8f9f7	2798	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2799	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2800	{
<>	144:ef7eb2e8f9f7	2801	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2802	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2803	}
<>	144:ef7eb2e8f9f7	2804
<>	144:ef7eb2e8f9f7	2805	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2806	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2807
<>	144:ef7eb2e8f9f7	2808	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2809	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2810	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2811
<>	144:ef7eb2e8f9f7	2812	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2813	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2814	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2815	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2816	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2817	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2818	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2819	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2820	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2821
<>	144:ef7eb2e8f9f7	2822	/* Generate Start */
<>	144:ef7eb2e8f9f7	2823	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2824
<>	144:ef7eb2e8f9f7	2825	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2826	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2827
<>	144:ef7eb2e8f9f7	2828	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2829	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2830	process unlock */
<>	144:ef7eb2e8f9f7	2831
<>	144:ef7eb2e8f9f7	2832	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2833	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2834
<>	144:ef7eb2e8f9f7	2835	return HAL_OK;
<>	144:ef7eb2e8f9f7	2836	}
<>	144:ef7eb2e8f9f7	2837	else
<>	144:ef7eb2e8f9f7	2838	{
<>	144:ef7eb2e8f9f7	2839	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2840	}
<>	144:ef7eb2e8f9f7	2841	}
<>	144:ef7eb2e8f9f7	2842
<>	144:ef7eb2e8f9f7	2843	/**
<>	144:ef7eb2e8f9f7	2844	* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	2845	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2846	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2847	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2848	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2849	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2850	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2851	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2852	* @retval HAL status
<>	144:ef7eb2e8f9f7	2853	*/
<>	144:ef7eb2e8f9f7	2854	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2855	{
<>	144:ef7eb2e8f9f7	2856	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2857
<>	144:ef7eb2e8f9f7	2858	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2859	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2860
<>	144:ef7eb2e8f9f7	2861	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2862	{
<>	144:ef7eb2e8f9f7	2863	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2864	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2865	do
<>	144:ef7eb2e8f9f7	2866	{
<>	144:ef7eb2e8f9f7	2867	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2868	{
<>	144:ef7eb2e8f9f7	2869	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2870	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2871
<>	144:ef7eb2e8f9f7	2872	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2873	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2874
<>	144:ef7eb2e8f9f7	2875	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2876	}
<>	144:ef7eb2e8f9f7	2877	}
<>	144:ef7eb2e8f9f7	2878	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2879
<>	144:ef7eb2e8f9f7	2880	/* Process Locked */
<>	144:ef7eb2e8f9f7	2881	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2882
<>	144:ef7eb2e8f9f7	2883	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2884	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2885	{
<>	144:ef7eb2e8f9f7	2886	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2887	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2888	}
<>	144:ef7eb2e8f9f7	2889
<>	144:ef7eb2e8f9f7	2890	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2891	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2892
<>	144:ef7eb2e8f9f7	2893	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2894	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2895	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2896
<>	144:ef7eb2e8f9f7	2897	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2898	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2899	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2900	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2901	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2902	hi2c->Devaddress = DevAddress;
<>	144:ef7eb2e8f9f7	2903	hi2c->Memaddress = MemAddress;
<>	144:ef7eb2e8f9f7	2904	hi2c->MemaddSize = MemAddSize;
<>	144:ef7eb2e8f9f7	2905	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	2906
<>	144:ef7eb2e8f9f7	2907	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2908	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2909
<>	144:ef7eb2e8f9f7	2910	/* Generate Start */
<>	144:ef7eb2e8f9f7	2911	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2914	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2915
<>	144:ef7eb2e8f9f7	2916	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2917	{
<>	144:ef7eb2e8f9f7	2918	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	2919	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	2920	process unlock */
<>	144:ef7eb2e8f9f7	2921
<>	144:ef7eb2e8f9f7	2922	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2923	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2924	}
<>	144:ef7eb2e8f9f7	2925	return HAL_OK;
<>	144:ef7eb2e8f9f7	2926	}
<>	144:ef7eb2e8f9f7	2927	else
<>	144:ef7eb2e8f9f7	2928	{
<>	144:ef7eb2e8f9f7	2929	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2930	}
<>	144:ef7eb2e8f9f7	2931	}
<>	144:ef7eb2e8f9f7	2932
<>	144:ef7eb2e8f9f7	2933	/**
<>	144:ef7eb2e8f9f7	2934	* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	2935	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2936	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2937	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2938	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2939	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2940	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2941	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2942	* @retval HAL status
<>	144:ef7eb2e8f9f7	2943	*/
<>	144:ef7eb2e8f9f7	2944	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2945	{
<>	144:ef7eb2e8f9f7	2946	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	2949
<>	144:ef7eb2e8f9f7	2950	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	2951	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2952
<>	144:ef7eb2e8f9f7	2953	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2954	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2955
<>	144:ef7eb2e8f9f7	2956	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2957	{
<>	144:ef7eb2e8f9f7	2958	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	2959	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	2960	do
<>	144:ef7eb2e8f9f7	2961	{
<>	144:ef7eb2e8f9f7	2962	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	2963	{
<>	144:ef7eb2e8f9f7	2964	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	2965	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2966
<>	144:ef7eb2e8f9f7	2967	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2968	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2969
<>	144:ef7eb2e8f9f7	2970	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2971	}
<>	144:ef7eb2e8f9f7	2972	}
<>	144:ef7eb2e8f9f7	2973	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2974
<>	144:ef7eb2e8f9f7	2975	/* Process Locked */
<>	144:ef7eb2e8f9f7	2976	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2977
<>	144:ef7eb2e8f9f7	2978	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	2979	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	2980	{
<>	144:ef7eb2e8f9f7	2981	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	2982	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	2983	}
<>	144:ef7eb2e8f9f7	2984
<>	144:ef7eb2e8f9f7	2985	/* Disable Pos */
<>	144:ef7eb2e8f9f7	2986	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2987
<>	144:ef7eb2e8f9f7	2988	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2989	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2990	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2991
<>	144:ef7eb2e8f9f7	2992	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2993	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2994	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2995	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	2996	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	2997
<>	144:ef7eb2e8f9f7	2998	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2999	{
<>	144:ef7eb2e8f9f7	3000	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	3001	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	3002
<>	144:ef7eb2e8f9f7	3003	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3004	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	3005
<>	144:ef7eb2e8f9f7	3006	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	3007	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3008	hi2c->hdmatx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3009	hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3010	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	3011
<>	144:ef7eb2e8f9f7	3012	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3013	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3014
<>	144:ef7eb2e8f9f7	3015	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3016	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3017	{
<>	144:ef7eb2e8f9f7	3018	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3019	{
<>	144:ef7eb2e8f9f7	3020	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3021	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3022	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3023	}
<>	144:ef7eb2e8f9f7	3024	else
<>	144:ef7eb2e8f9f7	3025	{
<>	144:ef7eb2e8f9f7	3026	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3027	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3028	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3029	}
<>	144:ef7eb2e8f9f7	3030	}
<>	144:ef7eb2e8f9f7	3031
<>	144:ef7eb2e8f9f7	3032	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3033	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3034
<>	144:ef7eb2e8f9f7	3035	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3036	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3037
<>	144:ef7eb2e8f9f7	3038	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	3039	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	3040	process unlock */
<>	144:ef7eb2e8f9f7	3041	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	3042	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3043
<>	144:ef7eb2e8f9f7	3044	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3045	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3046	}
<>	144:ef7eb2e8f9f7	3047	return HAL_OK;
<>	144:ef7eb2e8f9f7	3048	}
<>	144:ef7eb2e8f9f7	3049	else
<>	144:ef7eb2e8f9f7	3050	{
<>	144:ef7eb2e8f9f7	3051	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3052	}
<>	144:ef7eb2e8f9f7	3053	}
<>	144:ef7eb2e8f9f7	3054
<>	144:ef7eb2e8f9f7	3055	/**
<>	144:ef7eb2e8f9f7	3056	* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
<>	144:ef7eb2e8f9f7	3057	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3058	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3059	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3060	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3061	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3062	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	3063	* @param Size Amount of data to be read
<>	144:ef7eb2e8f9f7	3064	* @retval HAL status
<>	144:ef7eb2e8f9f7	3065	*/
<>	144:ef7eb2e8f9f7	3066	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	3067	{
<>	144:ef7eb2e8f9f7	3068	uint32_t tickstart = 0x00U;
<>	144:ef7eb2e8f9f7	3069
<>	144:ef7eb2e8f9f7	3070	/* Init tickstart for timeout management*/
<>	144:ef7eb2e8f9f7	3071	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3072
<>	144:ef7eb2e8f9f7	3073	__IO uint32_t count = 0U;
<>	144:ef7eb2e8f9f7	3074
<>	144:ef7eb2e8f9f7	3075	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3076	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	3077
<>	144:ef7eb2e8f9f7	3078	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3079	{
<>	144:ef7eb2e8f9f7	3080	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3081	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	144:ef7eb2e8f9f7	3082	do
<>	144:ef7eb2e8f9f7	3083	{
<>	144:ef7eb2e8f9f7	3084	if(count-- == 0U)
<>	144:ef7eb2e8f9f7	3085	{
<>	144:ef7eb2e8f9f7	3086	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3087	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3088
<>	144:ef7eb2e8f9f7	3089	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3090	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3091
<>	144:ef7eb2e8f9f7	3092	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3093	}
<>	144:ef7eb2e8f9f7	3094	}
<>	144:ef7eb2e8f9f7	3095	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	3096
<>	144:ef7eb2e8f9f7	3097	/* Process Locked */
<>	144:ef7eb2e8f9f7	3098	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3099
<>	144:ef7eb2e8f9f7	3100	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	3101	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	3102	{
<>	144:ef7eb2e8f9f7	3103	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	3104	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	3105	}
<>	144:ef7eb2e8f9f7	3106
<>	144:ef7eb2e8f9f7	3107	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3108	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3109
<>	144:ef7eb2e8f9f7	3110	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	3111	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	3112	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3113
<>	144:ef7eb2e8f9f7	3114	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	3115	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	3116	hi2c->XferCount = Size;
<>	144:ef7eb2e8f9f7	3117	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3118	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3119
<>	144:ef7eb2e8f9f7	3120	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	3121	{
<>	144:ef7eb2e8f9f7	3122	/* Set the I2C DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	3123	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	144:ef7eb2e8f9f7	3124
<>	144:ef7eb2e8f9f7	3125	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	3126	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	144:ef7eb2e8f9f7	3127
<>	144:ef7eb2e8f9f7	3128	/* Set the unused DMA callbacks to NULL */
<>	144:ef7eb2e8f9f7	3129	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3130	hi2c->hdmarx->XferM1CpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3131	hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
<>	144:ef7eb2e8f9f7	3132	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	3133
<>	144:ef7eb2e8f9f7	3134	/* Enable the DMA Stream */
<>	144:ef7eb2e8f9f7	3135	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	144:ef7eb2e8f9f7	3136
<>	144:ef7eb2e8f9f7	3137	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3138	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3139	{
<>	144:ef7eb2e8f9f7	3140	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3141	{
<>	144:ef7eb2e8f9f7	3142	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3143	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3144	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3145	}
<>	144:ef7eb2e8f9f7	3146	else
<>	144:ef7eb2e8f9f7	3147	{
<>	144:ef7eb2e8f9f7	3148	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3149	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3150	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3151	}
<>	144:ef7eb2e8f9f7	3152	}
<>	144:ef7eb2e8f9f7	3153
<>	144:ef7eb2e8f9f7	3154	if(Size == 1U)
<>	144:ef7eb2e8f9f7	3155	{
<>	144:ef7eb2e8f9f7	3156	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3157	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3158	}
<>	144:ef7eb2e8f9f7	3159	else
<>	144:ef7eb2e8f9f7	3160	{
<>	144:ef7eb2e8f9f7	3161	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	3162	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	3163	}
<>	144:ef7eb2e8f9f7	3164
<>	144:ef7eb2e8f9f7	3165	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3166	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3167
<>	144:ef7eb2e8f9f7	3168	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3169	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3170
<>	144:ef7eb2e8f9f7	3171	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	3172	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	3173	process unlock */
<>	144:ef7eb2e8f9f7	3174	/* Enable ERR interrupt */
<>	144:ef7eb2e8f9f7	3175	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3176
<>	144:ef7eb2e8f9f7	3177	/* Enable DMA Request */
<>	144:ef7eb2e8f9f7	3178	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3179	}
<>	144:ef7eb2e8f9f7	3180	else
<>	144:ef7eb2e8f9f7	3181	{
<>	144:ef7eb2e8f9f7	3182	/* Send Slave Address and Memory Address */
<>	144:ef7eb2e8f9f7	3183	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3184	{
<>	144:ef7eb2e8f9f7	3185	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	3186	{
<>	144:ef7eb2e8f9f7	3187	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3188	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3189	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3190	}
<>	144:ef7eb2e8f9f7	3191	else
<>	144:ef7eb2e8f9f7	3192	{
<>	144:ef7eb2e8f9f7	3193	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3194	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3195	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3196	}
<>	144:ef7eb2e8f9f7	3197	}
<>	144:ef7eb2e8f9f7	3198
<>	144:ef7eb2e8f9f7	3199	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	3200	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3201
<>	144:ef7eb2e8f9f7	3202	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3203	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3204
<>	144:ef7eb2e8f9f7	3205	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3206
<>	144:ef7eb2e8f9f7	3207	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3208	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3209	}
<>	144:ef7eb2e8f9f7	3210
<>	144:ef7eb2e8f9f7	3211	return HAL_OK;
<>	144:ef7eb2e8f9f7	3212	}
<>	144:ef7eb2e8f9f7	3213	else
<>	144:ef7eb2e8f9f7	3214	{
<>	144:ef7eb2e8f9f7	3215	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3216	}
<>	144:ef7eb2e8f9f7	3217	}
<>	144:ef7eb2e8f9f7	3218
<>	144:ef7eb2e8f9f7	3219	/**
<>	144:ef7eb2e8f9f7	3220	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	3221	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	3222	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3223	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3224	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3225	* @param Trials Number of trials
<>	144:ef7eb2e8f9f7	3226	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3227	* @retval HAL status
<>	144:ef7eb2e8f9f7	3228	*/
<>	144:ef7eb2e8f9f7	3229	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3230	{
<>	144:ef7eb2e8f9f7	3231	uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	/* Get tick */
<>	144:ef7eb2e8f9f7	3234	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3235
<>	144:ef7eb2e8f9f7	3236	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3237	{
<>	144:ef7eb2e8f9f7	3238	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3239	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3240	{
<>	144:ef7eb2e8f9f7	3241	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3242	}
<>	144:ef7eb2e8f9f7	3243
<>	144:ef7eb2e8f9f7	3244	/* Process Locked */
<>	144:ef7eb2e8f9f7	3245	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3246
<>	144:ef7eb2e8f9f7	3247	/* Check if the I2C is already enabled */
<>	144:ef7eb2e8f9f7	3248	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	3249	{
<>	144:ef7eb2e8f9f7	3250	/* Enable I2C peripheral */
<>	144:ef7eb2e8f9f7	3251	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	3252	}
<>	144:ef7eb2e8f9f7	3253
<>	144:ef7eb2e8f9f7	3254	/* Disable Pos */
<>	144:ef7eb2e8f9f7	3255	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3256
<>	144:ef7eb2e8f9f7	3257	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3258	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3259	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	3260
<>	144:ef7eb2e8f9f7	3261	do
<>	144:ef7eb2e8f9f7	3262	{
<>	144:ef7eb2e8f9f7	3263	/* Generate Start */
<>	144:ef7eb2e8f9f7	3264	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3265
<>	144:ef7eb2e8f9f7	3266	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	3267	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3268	{
<>	144:ef7eb2e8f9f7	3269	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3270	}
<>	144:ef7eb2e8f9f7	3271
<>	144:ef7eb2e8f9f7	3272	/* Send slave address */
<>	144:ef7eb2e8f9f7	3273	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	3274
<>	144:ef7eb2e8f9f7	3275	/* Wait until ADDR or AF flag are set */
<>	144:ef7eb2e8f9f7	3276	/* Get tick */
<>	144:ef7eb2e8f9f7	3277	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3278
<>	144:ef7eb2e8f9f7	3279	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3280	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3281	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3282	while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	3283	{
<>	144:ef7eb2e8f9f7	3284	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3285	{
<>	144:ef7eb2e8f9f7	3286	hi2c->State = HAL_I2C_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	3287	}
<>	144:ef7eb2e8f9f7	3288	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3289	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3290	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3291	}
<>	144:ef7eb2e8f9f7	3292
<>	144:ef7eb2e8f9f7	3293	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3294
<>	144:ef7eb2e8f9f7	3295	/* Check if the ADDR flag has been set */
<>	144:ef7eb2e8f9f7	3296	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	3297	{
<>	144:ef7eb2e8f9f7	3298	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3299	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3300
<>	144:ef7eb2e8f9f7	3301	/* Clear ADDR Flag */
<>	144:ef7eb2e8f9f7	3302	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3303
<>	144:ef7eb2e8f9f7	3304	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3305	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3306	{
<>	144:ef7eb2e8f9f7	3307	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3308	}
<>	144:ef7eb2e8f9f7	3309
<>	144:ef7eb2e8f9f7	3310	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3311
<>	144:ef7eb2e8f9f7	3312	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3313	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3314
<>	144:ef7eb2e8f9f7	3315	return HAL_OK;
<>	144:ef7eb2e8f9f7	3316	}
<>	144:ef7eb2e8f9f7	3317	else
<>	144:ef7eb2e8f9f7	3318	{
<>	144:ef7eb2e8f9f7	3319	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3320	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3321
<>	144:ef7eb2e8f9f7	3322	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	3323	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3324
<>	144:ef7eb2e8f9f7	3325	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	3326	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3327	{
<>	144:ef7eb2e8f9f7	3328	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3329	}
<>	144:ef7eb2e8f9f7	3330	}
<>	144:ef7eb2e8f9f7	3331	}while(I2C_Trials++ < Trials);
<>	144:ef7eb2e8f9f7	3332
<>	144:ef7eb2e8f9f7	3333	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3334
<>	144:ef7eb2e8f9f7	3335	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3336	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3337
<>	144:ef7eb2e8f9f7	3338	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3339	}
<>	144:ef7eb2e8f9f7	3340	else
<>	144:ef7eb2e8f9f7	3341	{
<>	144:ef7eb2e8f9f7	3342	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3343	}
<>	144:ef7eb2e8f9f7	3344	}
<>	144:ef7eb2e8f9f7	3345
<>	144:ef7eb2e8f9f7	3346	/**
<>	144:ef7eb2e8f9f7	3347	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	3348	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3349	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3350	* @retval None
<>	144:ef7eb2e8f9f7	3351	*/
<>	144:ef7eb2e8f9f7	3352	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3353	{
<>	144:ef7eb2e8f9f7	3354	uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
<>	144:ef7eb2e8f9f7	3355	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3356	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3357
<>	144:ef7eb2e8f9f7	3358	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3359
<>	144:ef7eb2e8f9f7	3360	/* Master or Memory mode selected */
<>	144:ef7eb2e8f9f7	3361	if((CurrentMode == HAL_I2C_MODE_MASTER) \|\| (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	3362	{
<>	144:ef7eb2e8f9f7	3363	/* SB Set ----------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3364	if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3365	{
<>	144:ef7eb2e8f9f7	3366	I2C_Master_SB(hi2c);
<>	144:ef7eb2e8f9f7	3367	}
<>	144:ef7eb2e8f9f7	3368	/* ADD10 Set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3369	else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3370	{
<>	144:ef7eb2e8f9f7	3371	I2C_Master_ADD10(hi2c);
<>	144:ef7eb2e8f9f7	3372	}
<>	144:ef7eb2e8f9f7	3373	/* ADDR Set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3374	else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3375	{
<>	144:ef7eb2e8f9f7	3376	I2C_Master_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3377	}
<>	144:ef7eb2e8f9f7	3378
<>	144:ef7eb2e8f9f7	3379	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3380	if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3381	{
<>	144:ef7eb2e8f9f7	3382	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3383	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3384	{
<>	144:ef7eb2e8f9f7	3385	I2C_MasterTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3386	}
<>	144:ef7eb2e8f9f7	3387	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3388	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3389	{
<>	144:ef7eb2e8f9f7	3390	I2C_MasterTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3391	}
<>	144:ef7eb2e8f9f7	3392	}
<>	144:ef7eb2e8f9f7	3393	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3394	else
<>	144:ef7eb2e8f9f7	3395	{
<>	144:ef7eb2e8f9f7	3396	/* RXNE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3397	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3398	{
<>	144:ef7eb2e8f9f7	3399	I2C_MasterReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3400	}
<>	144:ef7eb2e8f9f7	3401	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3402	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3403	{
<>	144:ef7eb2e8f9f7	3404	I2C_MasterReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3405	}
<>	144:ef7eb2e8f9f7	3406	}
<>	144:ef7eb2e8f9f7	3407	}
<>	144:ef7eb2e8f9f7	3408	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	3409	else
<>	144:ef7eb2e8f9f7	3410	{
<>	144:ef7eb2e8f9f7	3411	/* ADDR set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3412	if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3413	{
<>	144:ef7eb2e8f9f7	3414	I2C_Slave_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3415	}
<>	144:ef7eb2e8f9f7	3416	/* STOPF set --------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3417	else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3418	{
<>	144:ef7eb2e8f9f7	3419	I2C_Slave_STOPF(hi2c);
<>	144:ef7eb2e8f9f7	3420	}
<>	144:ef7eb2e8f9f7	3421	/* I2C in mode Transmitter -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3422	else if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3423	{
<>	144:ef7eb2e8f9f7	3424	/* TXE set and BTF reset -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3425	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3426	{
<>	144:ef7eb2e8f9f7	3427	I2C_SlaveTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3428	}
<>	144:ef7eb2e8f9f7	3429	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3430	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3431	{
<>	144:ef7eb2e8f9f7	3432	I2C_SlaveTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3433	}
<>	144:ef7eb2e8f9f7	3434	}
<>	144:ef7eb2e8f9f7	3435	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3436	else
<>	144:ef7eb2e8f9f7	3437	{
<>	144:ef7eb2e8f9f7	3438	/* RXNE set and BTF reset ----------------------------------------------*/
<>	144:ef7eb2e8f9f7	3439	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3440	{
<>	144:ef7eb2e8f9f7	3441	I2C_SlaveReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3442	}
<>	144:ef7eb2e8f9f7	3443	/* BTF set -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3444	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3445	{
<>	144:ef7eb2e8f9f7	3446	I2C_SlaveReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3447	}
<>	144:ef7eb2e8f9f7	3448	}
<>	144:ef7eb2e8f9f7	3449	}
<>	144:ef7eb2e8f9f7	3450	}
<>	144:ef7eb2e8f9f7	3451
<>	144:ef7eb2e8f9f7	3452	/**
<>	144:ef7eb2e8f9f7	3453	* @brief This function handles I2C error interrupt request.
<>	144:ef7eb2e8f9f7	3454	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3455	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3456	* @retval None
<>	144:ef7eb2e8f9f7	3457	*/
<>	144:ef7eb2e8f9f7	3458	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3459	{
<>	144:ef7eb2e8f9f7	3460	uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
<>	144:ef7eb2e8f9f7	3461	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	144:ef7eb2e8f9f7	3462	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	144:ef7eb2e8f9f7	3463
<>	144:ef7eb2e8f9f7	3464	/* I2C Bus error interrupt occurred ----------------------------------------*/
<>	144:ef7eb2e8f9f7	3465	if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3466	{
<>	144:ef7eb2e8f9f7	3467	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	3468
<>	144:ef7eb2e8f9f7	3469	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	3470	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	144:ef7eb2e8f9f7	3471	}
<>	144:ef7eb2e8f9f7	3472
<>	144:ef7eb2e8f9f7	3473	/* I2C Arbitration Loss error interrupt occurred ---------------------------*/
<>	144:ef7eb2e8f9f7	3474	if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3475	{
<>	144:ef7eb2e8f9f7	3476	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	3477
<>	144:ef7eb2e8f9f7	3478	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	3479	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	3480	}
<>	144:ef7eb2e8f9f7	3481
<>	144:ef7eb2e8f9f7	3482	/* I2C Acknowledge failure error interrupt occurred ------------------------*/
<>	144:ef7eb2e8f9f7	3483	if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3484	{
<>	144:ef7eb2e8f9f7	3485	tmp1 = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3486	tmp2 = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3487	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3488	tmp4 = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	3489	if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
<>	144:ef7eb2e8f9f7	3490	((tmp3 == HAL_I2C_STATE_BUSY_TX) \|\| (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| \
<>	144:ef7eb2e8f9f7	3491	((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
<>	144:ef7eb2e8f9f7	3492	{
<>	144:ef7eb2e8f9f7	3493	I2C_Slave_AF(hi2c);
<>	144:ef7eb2e8f9f7	3494	}
<>	144:ef7eb2e8f9f7	3495	else
<>	144:ef7eb2e8f9f7	3496	{
<>	144:ef7eb2e8f9f7	3497	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	3498
<>	144:ef7eb2e8f9f7	3499	/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
<>	144:ef7eb2e8f9f7	3500	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	144:ef7eb2e8f9f7	3501	{
<>	144:ef7eb2e8f9f7	3502	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3503	SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
<>	144:ef7eb2e8f9f7	3504	}
<>	144:ef7eb2e8f9f7	3505
<>	144:ef7eb2e8f9f7	3506	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	3507	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3508	}
<>	144:ef7eb2e8f9f7	3509	}
<>	144:ef7eb2e8f9f7	3510
<>	144:ef7eb2e8f9f7	3511	/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
<>	144:ef7eb2e8f9f7	3512	if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3513	{
<>	144:ef7eb2e8f9f7	3514	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	3515	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	3516	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	3517	}
<>	144:ef7eb2e8f9f7	3518
<>	144:ef7eb2e8f9f7	3519	/* Call the Error Callback in case of Error detected -----------------------*/
<>	144:ef7eb2e8f9f7	3520	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3521	{
<>	144:ef7eb2e8f9f7	3522	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	3523	}
<>	144:ef7eb2e8f9f7	3524	}
<>	144:ef7eb2e8f9f7	3525
<>	144:ef7eb2e8f9f7	3526	/**
<>	144:ef7eb2e8f9f7	3527	* @brief Master Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3528	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3529	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3530	* @retval None
<>	144:ef7eb2e8f9f7	3531	*/
<>	144:ef7eb2e8f9f7	3532	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3533	{
<>	144:ef7eb2e8f9f7	3534	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3535	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3536
<>	144:ef7eb2e8f9f7	3537	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3538	the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3539	*/
<>	144:ef7eb2e8f9f7	3540	}
<>	144:ef7eb2e8f9f7	3541
<>	144:ef7eb2e8f9f7	3542	/**
<>	144:ef7eb2e8f9f7	3543	* @brief Master Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3544	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3545	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3546	* @retval None
<>	144:ef7eb2e8f9f7	3547	*/
<>	144:ef7eb2e8f9f7	3548	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3549	{
<>	144:ef7eb2e8f9f7	3550	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3551	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3552
<>	144:ef7eb2e8f9f7	3553	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3554	the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3555	*/
<>	144:ef7eb2e8f9f7	3556	}
<>	144:ef7eb2e8f9f7	3557
<>	144:ef7eb2e8f9f7	3558	/** @brief Slave Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3559	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3560	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3561	* @retval None
<>	144:ef7eb2e8f9f7	3562	*/
<>	144:ef7eb2e8f9f7	3563	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3564	{
<>	144:ef7eb2e8f9f7	3565	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3566	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3567
<>	144:ef7eb2e8f9f7	3568	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3569	the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3570	*/
<>	144:ef7eb2e8f9f7	3571	}
<>	144:ef7eb2e8f9f7	3572
<>	144:ef7eb2e8f9f7	3573	/**
<>	144:ef7eb2e8f9f7	3574	* @brief Slave Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3575	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3576	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3577	* @retval None
<>	144:ef7eb2e8f9f7	3578	*/
<>	144:ef7eb2e8f9f7	3579	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3580	{
<>	144:ef7eb2e8f9f7	3581	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3582	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3583
<>	144:ef7eb2e8f9f7	3584	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3585	the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3586	*/
<>	144:ef7eb2e8f9f7	3587	}
<>	144:ef7eb2e8f9f7	3588
<>	144:ef7eb2e8f9f7	3589	/**
<>	144:ef7eb2e8f9f7	3590	* @brief Slave Address Match callback.
<>	144:ef7eb2e8f9f7	3591	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3592	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3593	* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
<>	144:ef7eb2e8f9f7	3594	* @param AddrMatchCode Address Match Code
<>	144:ef7eb2e8f9f7	3595	* @retval None
<>	144:ef7eb2e8f9f7	3596	*/
<>	144:ef7eb2e8f9f7	3597	__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<>	144:ef7eb2e8f9f7	3598	{
<>	144:ef7eb2e8f9f7	3599	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3600	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3601	UNUSED(TransferDirection);
<>	144:ef7eb2e8f9f7	3602	UNUSED(AddrMatchCode);
<>	144:ef7eb2e8f9f7	3603
<>	144:ef7eb2e8f9f7	3604	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3605	the HAL_I2C_AddrCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3606	*/
<>	144:ef7eb2e8f9f7	3607	}
<>	144:ef7eb2e8f9f7	3608
<>	144:ef7eb2e8f9f7	3609	/**
<>	144:ef7eb2e8f9f7	3610	* @brief Listen Complete callback.
<>	144:ef7eb2e8f9f7	3611	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3612	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3613	* @retval None
<>	144:ef7eb2e8f9f7	3614	*/
<>	144:ef7eb2e8f9f7	3615	__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3616	{
<>	144:ef7eb2e8f9f7	3617	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3618	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3619
<>	144:ef7eb2e8f9f7	3620	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3621	the HAL_I2C_ListenCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3622	*/
<>	144:ef7eb2e8f9f7	3623	}
<>	144:ef7eb2e8f9f7	3624
<>	144:ef7eb2e8f9f7	3625	/**
<>	144:ef7eb2e8f9f7	3626	* @brief Memory Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3627	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3628	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3629	* @retval None
<>	144:ef7eb2e8f9f7	3630	*/
<>	144:ef7eb2e8f9f7	3631	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3632	{
<>	144:ef7eb2e8f9f7	3633	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3634	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3635
<>	144:ef7eb2e8f9f7	3636	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3637	the HAL_I2C_MemTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3638	*/
<>	144:ef7eb2e8f9f7	3639	}
<>	144:ef7eb2e8f9f7	3640
<>	144:ef7eb2e8f9f7	3641	/**
<>	144:ef7eb2e8f9f7	3642	* @brief Memory Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3643	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3644	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3645	* @retval None
<>	144:ef7eb2e8f9f7	3646	*/
<>	144:ef7eb2e8f9f7	3647	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3648	{
<>	144:ef7eb2e8f9f7	3649	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3650	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3651
<>	144:ef7eb2e8f9f7	3652	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3653	the HAL_I2C_MemRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3654	*/
<>	144:ef7eb2e8f9f7	3655	}
<>	144:ef7eb2e8f9f7	3656
<>	144:ef7eb2e8f9f7	3657	/**
<>	144:ef7eb2e8f9f7	3658	* @brief I2C error callback.
<>	144:ef7eb2e8f9f7	3659	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3660	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3661	* @retval None
<>	144:ef7eb2e8f9f7	3662	*/
<>	144:ef7eb2e8f9f7	3663	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3664	{
<>	144:ef7eb2e8f9f7	3665	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3666	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3667
<>	144:ef7eb2e8f9f7	3668	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3669	the HAL_I2C_ErrorCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3670	*/
<>	144:ef7eb2e8f9f7	3671	}
<>	144:ef7eb2e8f9f7	3672
<>	144:ef7eb2e8f9f7	3673	/**
<>	144:ef7eb2e8f9f7	3674	* @brief I2C abort callback.
<>	144:ef7eb2e8f9f7	3675	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3676	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3677	* @retval None
<>	144:ef7eb2e8f9f7	3678	*/
<>	144:ef7eb2e8f9f7	3679	__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3680	{
<>	144:ef7eb2e8f9f7	3681	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3682	UNUSED(hi2c);
<>	144:ef7eb2e8f9f7	3683
<>	144:ef7eb2e8f9f7	3684	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	3685	the HAL_I2C_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3686	*/
<>	144:ef7eb2e8f9f7	3687	}
<>	144:ef7eb2e8f9f7	3688
<>	144:ef7eb2e8f9f7	3689	/**
<>	144:ef7eb2e8f9f7	3690	* @}
<>	144:ef7eb2e8f9f7	3691	*/
<>	144:ef7eb2e8f9f7	3692
<>	144:ef7eb2e8f9f7	3693	/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<>	144:ef7eb2e8f9f7	3694	* @brief Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	3695	*
<>	144:ef7eb2e8f9f7	3696	@verbatim
<>	144:ef7eb2e8f9f7	3697	===============================================================================
<>	144:ef7eb2e8f9f7	3698	##### Peripheral State, Mode and Error functions #####
<>	144:ef7eb2e8f9f7	3699	===============================================================================
<>	144:ef7eb2e8f9f7	3700	[..]
<>	144:ef7eb2e8f9f7	3701	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	3702	and the data flow.
<>	144:ef7eb2e8f9f7	3703
<>	144:ef7eb2e8f9f7	3704	@endverbatim
<>	144:ef7eb2e8f9f7	3705	* @{
<>	144:ef7eb2e8f9f7	3706	*/
<>	144:ef7eb2e8f9f7	3707
<>	144:ef7eb2e8f9f7	3708	/**
<>	144:ef7eb2e8f9f7	3709	* @brief Return the I2C handle state.
<>	144:ef7eb2e8f9f7	3710	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3711	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3712	* @retval HAL state
<>	144:ef7eb2e8f9f7	3713	*/
<>	144:ef7eb2e8f9f7	3714	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3715	{
<>	144:ef7eb2e8f9f7	3716	/* Return I2C handle state */
<>	144:ef7eb2e8f9f7	3717	return hi2c->State;
<>	144:ef7eb2e8f9f7	3718	}
<>	144:ef7eb2e8f9f7	3719
<>	144:ef7eb2e8f9f7	3720	/**
<>	144:ef7eb2e8f9f7	3721	* @brief Return the I2C Master, Slave, Memory or no mode.
<>	144:ef7eb2e8f9f7	3722	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3723	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3724	* @retval HAL mode
<>	144:ef7eb2e8f9f7	3725	*/
<>	144:ef7eb2e8f9f7	3726	HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3727	{
<>	144:ef7eb2e8f9f7	3728	return hi2c->Mode;
<>	144:ef7eb2e8f9f7	3729	}
<>	144:ef7eb2e8f9f7	3730
<>	144:ef7eb2e8f9f7	3731	/**
<>	144:ef7eb2e8f9f7	3732	* @brief Return the I2C error code
<>	144:ef7eb2e8f9f7	3733	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3734	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3735	* @retval I2C Error Code
<>	144:ef7eb2e8f9f7	3736	*/
<>	144:ef7eb2e8f9f7	3737	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3738	{
<>	144:ef7eb2e8f9f7	3739	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	3740	}
<>	144:ef7eb2e8f9f7	3741
<>	144:ef7eb2e8f9f7	3742	/**
<>	144:ef7eb2e8f9f7	3743	* @}
<>	144:ef7eb2e8f9f7	3744	*/
<>	144:ef7eb2e8f9f7	3745
<>	144:ef7eb2e8f9f7	3746	/**
<>	144:ef7eb2e8f9f7	3747	* @brief Handle TXE flag for Master
<>	144:ef7eb2e8f9f7	3748	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3749	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3750	* @retval HAL status
<>	144:ef7eb2e8f9f7	3751	*/
<>	144:ef7eb2e8f9f7	3752	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3753	{
<>	144:ef7eb2e8f9f7	3754	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3755	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	3756	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3757	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3758
<>	144:ef7eb2e8f9f7	3759	if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
<>	144:ef7eb2e8f9f7	3760	{
<>	144:ef7eb2e8f9f7	3761	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3762	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3763	{
<>	144:ef7eb2e8f9f7	3764	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3765
<>	144:ef7eb2e8f9f7	3766	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	3767	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3768	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3769
<>	144:ef7eb2e8f9f7	3770	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3771	}
<>	144:ef7eb2e8f9f7	3772	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3773	{
<>	144:ef7eb2e8f9f7	3774	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3775	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3776
<>	144:ef7eb2e8f9f7	3777	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3778	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3779
<>	144:ef7eb2e8f9f7	3780	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3781	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3782
<>	144:ef7eb2e8f9f7	3783	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3784	{
<>	144:ef7eb2e8f9f7	3785	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3786	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3787	}
<>	144:ef7eb2e8f9f7	3788	else
<>	144:ef7eb2e8f9f7	3789	{
<>	144:ef7eb2e8f9f7	3790	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3791	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3792	}
<>	144:ef7eb2e8f9f7	3793	}
<>	144:ef7eb2e8f9f7	3794	}
<>	144:ef7eb2e8f9f7	3795	else if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| \
<>	144:ef7eb2e8f9f7	3796	((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	3797	{
<>	144:ef7eb2e8f9f7	3798	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3799	{
<>	144:ef7eb2e8f9f7	3800	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3801	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3802	}
<>	144:ef7eb2e8f9f7	3803	else
<>	144:ef7eb2e8f9f7	3804	{
<>	144:ef7eb2e8f9f7	3805	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3806	{
<>	144:ef7eb2e8f9f7	3807	if(hi2c->EventCount == 0)
<>	144:ef7eb2e8f9f7	3808	{
<>	144:ef7eb2e8f9f7	3809	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	3810	if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	3811	{
<>	144:ef7eb2e8f9f7	3812	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	3813	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3814
<>	144:ef7eb2e8f9f7	3815	hi2c->EventCount += 2;
<>	144:ef7eb2e8f9f7	3816	}
<>	144:ef7eb2e8f9f7	3817	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	3818	else
<>	144:ef7eb2e8f9f7	3819	{
<>	144:ef7eb2e8f9f7	3820	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	3821	hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3822
<>	144:ef7eb2e8f9f7	3823	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3824	}
<>	144:ef7eb2e8f9f7	3825	}
<>	144:ef7eb2e8f9f7	3826	else if(hi2c->EventCount == 1)
<>	144:ef7eb2e8f9f7	3827	{
<>	144:ef7eb2e8f9f7	3828	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	3829	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	144:ef7eb2e8f9f7	3830
<>	144:ef7eb2e8f9f7	3831	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	3832	}
<>	144:ef7eb2e8f9f7	3833	else if(hi2c->EventCount == 2)
<>	144:ef7eb2e8f9f7	3834	{
<>	144:ef7eb2e8f9f7	3835	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3836	{
<>	144:ef7eb2e8f9f7	3837	/* Generate Restart */
<>	144:ef7eb2e8f9f7	3838	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3839	}
<>	144:ef7eb2e8f9f7	3840	else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3841	{
<>	144:ef7eb2e8f9f7	3842	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3843	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3844	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3845	}
<>	144:ef7eb2e8f9f7	3846	}
<>	144:ef7eb2e8f9f7	3847	}
<>	144:ef7eb2e8f9f7	3848	else
<>	144:ef7eb2e8f9f7	3849	{
<>	144:ef7eb2e8f9f7	3850	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3851	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3852	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3853	}
<>	144:ef7eb2e8f9f7	3854	}
<>	144:ef7eb2e8f9f7	3855	}
<>	144:ef7eb2e8f9f7	3856	return HAL_OK;
<>	144:ef7eb2e8f9f7	3857	}
<>	144:ef7eb2e8f9f7	3858
<>	144:ef7eb2e8f9f7	3859	/**
<>	144:ef7eb2e8f9f7	3860	* @brief Handle BTF flag for Master transmitter
<>	144:ef7eb2e8f9f7	3861	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3862	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3863	* @retval HAL status
<>	144:ef7eb2e8f9f7	3864	*/
<>	144:ef7eb2e8f9f7	3865	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3866	{
<>	144:ef7eb2e8f9f7	3867	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	3868	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	3869
<>	144:ef7eb2e8f9f7	3870	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	3871	{
<>	144:ef7eb2e8f9f7	3872	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	3873	{
<>	144:ef7eb2e8f9f7	3874	/* Write data to DR */
<>	144:ef7eb2e8f9f7	3875	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	3876	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3877	}
<>	144:ef7eb2e8f9f7	3878	else
<>	144:ef7eb2e8f9f7	3879	{
<>	144:ef7eb2e8f9f7	3880	/* Call TxCpltCallback() directly if no stop mode is set */
<>	144:ef7eb2e8f9f7	3881	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	3882	{
<>	144:ef7eb2e8f9f7	3883	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3884
<>	144:ef7eb2e8f9f7	3885	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	144:ef7eb2e8f9f7	3886	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3887	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3888
<>	144:ef7eb2e8f9f7	3889	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3890	}
<>	144:ef7eb2e8f9f7	3891	else /* Generate Stop condition then Call TxCpltCallback() */
<>	144:ef7eb2e8f9f7	3892	{
<>	144:ef7eb2e8f9f7	3893	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3894	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3895
<>	144:ef7eb2e8f9f7	3896	/* Generate Stop */
<>	144:ef7eb2e8f9f7	3897	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3898
<>	144:ef7eb2e8f9f7	3899	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3900	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3901
<>	144:ef7eb2e8f9f7	3902	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3903	{
<>	144:ef7eb2e8f9f7	3904	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3905
<>	144:ef7eb2e8f9f7	3906	HAL_I2C_MemTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3907	}
<>	144:ef7eb2e8f9f7	3908	else
<>	144:ef7eb2e8f9f7	3909	{
<>	144:ef7eb2e8f9f7	3910	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3911
<>	144:ef7eb2e8f9f7	3912	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3913	}
<>	144:ef7eb2e8f9f7	3914	}
<>	144:ef7eb2e8f9f7	3915	}
<>	144:ef7eb2e8f9f7	3916	}
<>	144:ef7eb2e8f9f7	3917	return HAL_OK;
<>	144:ef7eb2e8f9f7	3918	}
<>	144:ef7eb2e8f9f7	3919
<>	144:ef7eb2e8f9f7	3920	/**
<>	144:ef7eb2e8f9f7	3921	* @brief Handle RXNE flag for Master
<>	144:ef7eb2e8f9f7	3922	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3923	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3924	* @retval HAL status
<>	144:ef7eb2e8f9f7	3925	*/
<>	144:ef7eb2e8f9f7	3926	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3927	{
<>	144:ef7eb2e8f9f7	3928	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3929	{
<>	144:ef7eb2e8f9f7	3930	uint32_t tmp = 0U;
<>	144:ef7eb2e8f9f7	3931
<>	144:ef7eb2e8f9f7	3932	tmp = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3933	if(tmp > 3U)
<>	144:ef7eb2e8f9f7	3934	{
<>	144:ef7eb2e8f9f7	3935	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3936	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3937	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3938	}
<>	144:ef7eb2e8f9f7	3939	else if((tmp == 2U) \|\| (tmp == 3U))
<>	144:ef7eb2e8f9f7	3940	{
<>	144:ef7eb2e8f9f7	3941	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	3942	{
<>	144:ef7eb2e8f9f7	3943	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3944	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3945
<>	144:ef7eb2e8f9f7	3946	/* Enable Pos */
<>	144:ef7eb2e8f9f7	3947	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3948	}
<>	144:ef7eb2e8f9f7	3949	else
<>	144:ef7eb2e8f9f7	3950	{
<>	144:ef7eb2e8f9f7	3951	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	3952	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3953	}
<>	144:ef7eb2e8f9f7	3954
<>	144:ef7eb2e8f9f7	3955	/* Disable BUF interrupt */
<>	144:ef7eb2e8f9f7	3956	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3957	}
<>	144:ef7eb2e8f9f7	3958	else
<>	144:ef7eb2e8f9f7	3959	{
<>	144:ef7eb2e8f9f7	3960	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	3961	{
<>	144:ef7eb2e8f9f7	3962	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	3963	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3964	}
<>	144:ef7eb2e8f9f7	3965	else
<>	144:ef7eb2e8f9f7	3966	{
<>	144:ef7eb2e8f9f7	3967	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	3968	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3969	}
<>	144:ef7eb2e8f9f7	3970
<>	144:ef7eb2e8f9f7	3971	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	3972	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	3973
<>	144:ef7eb2e8f9f7	3974	/* Read data from DR */
<>	144:ef7eb2e8f9f7	3975	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	3976	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	3977
<>	144:ef7eb2e8f9f7	3978	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3979
<>	144:ef7eb2e8f9f7	3980	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	3981	{
<>	144:ef7eb2e8f9f7	3982	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	3983	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3984	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3985	}
<>	144:ef7eb2e8f9f7	3986	else
<>	144:ef7eb2e8f9f7	3987	{
<>	144:ef7eb2e8f9f7	3988	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	3989	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	3990	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	3991	}
<>	144:ef7eb2e8f9f7	3992	}
<>	144:ef7eb2e8f9f7	3993	}
<>	144:ef7eb2e8f9f7	3994	return HAL_OK;
<>	144:ef7eb2e8f9f7	3995	}
<>	144:ef7eb2e8f9f7	3996
<>	144:ef7eb2e8f9f7	3997	/**
<>	144:ef7eb2e8f9f7	3998	* @brief Handle BTF flag for Master receiver
<>	144:ef7eb2e8f9f7	3999	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4000	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4001	* @retval HAL status
<>	144:ef7eb2e8f9f7	4002	*/
<>	144:ef7eb2e8f9f7	4003	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4004	{
<>	144:ef7eb2e8f9f7	4005	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4006	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4007
<>	144:ef7eb2e8f9f7	4008	if(hi2c->XferCount == 3U)
<>	144:ef7eb2e8f9f7	4009	{
<>	144:ef7eb2e8f9f7	4010	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4011	{
<>	144:ef7eb2e8f9f7	4012	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4013	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4014	}
<>	144:ef7eb2e8f9f7	4015
<>	144:ef7eb2e8f9f7	4016	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4017	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4018	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4019	}
<>	144:ef7eb2e8f9f7	4020	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4021	{
<>	144:ef7eb2e8f9f7	4022	/* Prepare next transfer or stop current transfer */
<>	144:ef7eb2e8f9f7	4023	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4024	{
<>	144:ef7eb2e8f9f7	4025	if(CurrentXferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4026	{
<>	144:ef7eb2e8f9f7	4027	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4028	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4029	}
<>	144:ef7eb2e8f9f7	4030	else
<>	144:ef7eb2e8f9f7	4031	{
<>	144:ef7eb2e8f9f7	4032	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4033	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4034	}
<>	144:ef7eb2e8f9f7	4035	}
<>	144:ef7eb2e8f9f7	4036	else
<>	144:ef7eb2e8f9f7	4037	{
<>	144:ef7eb2e8f9f7	4038	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4039	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4040	}
<>	144:ef7eb2e8f9f7	4041
<>	144:ef7eb2e8f9f7	4042	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4043	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4044	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4045
<>	144:ef7eb2e8f9f7	4046	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4047	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4048	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4049
<>	144:ef7eb2e8f9f7	4050	/* Disable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	4051	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4052
<>	144:ef7eb2e8f9f7	4053	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4054
<>	144:ef7eb2e8f9f7	4055	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4056	{
<>	144:ef7eb2e8f9f7	4057	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4058	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4059
<>	144:ef7eb2e8f9f7	4060	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4061	}
<>	144:ef7eb2e8f9f7	4062	else
<>	144:ef7eb2e8f9f7	4063	{
<>	144:ef7eb2e8f9f7	4064	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<>	144:ef7eb2e8f9f7	4065	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4066
<>	144:ef7eb2e8f9f7	4067	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4068	}
<>	144:ef7eb2e8f9f7	4069	}
<>	144:ef7eb2e8f9f7	4070	else
<>	144:ef7eb2e8f9f7	4071	{
<>	144:ef7eb2e8f9f7	4072	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4073	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4074	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4075	}
<>	144:ef7eb2e8f9f7	4076	return HAL_OK;
<>	144:ef7eb2e8f9f7	4077	}
<>	144:ef7eb2e8f9f7	4078
<>	144:ef7eb2e8f9f7	4079	/**
<>	144:ef7eb2e8f9f7	4080	* @brief Handle SB flag for Master
<>	144:ef7eb2e8f9f7	4081	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4082	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4083	* @retval HAL status
<>	144:ef7eb2e8f9f7	4084	*/
<>	144:ef7eb2e8f9f7	4085	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4086	{
<>	144:ef7eb2e8f9f7	4087	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4088	{
<>	144:ef7eb2e8f9f7	4089	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	4090	{
<>	144:ef7eb2e8f9f7	4091	/* Send slave address */
<>	144:ef7eb2e8f9f7	4092	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4093	}
<>	144:ef7eb2e8f9f7	4094	else
<>	144:ef7eb2e8f9f7	4095	{
<>	144:ef7eb2e8f9f7	4096	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4097	}
<>	144:ef7eb2e8f9f7	4098	}
<>	144:ef7eb2e8f9f7	4099	else
<>	144:ef7eb2e8f9f7	4100	{
<>	144:ef7eb2e8f9f7	4101	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4102	{
<>	144:ef7eb2e8f9f7	4103	/* Send slave 7 Bits address */
<>	144:ef7eb2e8f9f7	4104	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4105	{
<>	144:ef7eb2e8f9f7	4106	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4107	}
<>	144:ef7eb2e8f9f7	4108	else
<>	144:ef7eb2e8f9f7	4109	{
<>	144:ef7eb2e8f9f7	4110	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4111	}
<>	144:ef7eb2e8f9f7	4112	}
<>	144:ef7eb2e8f9f7	4113	else
<>	144:ef7eb2e8f9f7	4114	{
<>	144:ef7eb2e8f9f7	4115	if(hi2c->EventCount == 0U)
<>	144:ef7eb2e8f9f7	4116	{
<>	144:ef7eb2e8f9f7	4117	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4118	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4119	}
<>	144:ef7eb2e8f9f7	4120	else if(hi2c->EventCount == 1U)
<>	144:ef7eb2e8f9f7	4121	{
<>	144:ef7eb2e8f9f7	4122	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4123	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4124	}
<>	144:ef7eb2e8f9f7	4125	}
<>	144:ef7eb2e8f9f7	4126	}
<>	144:ef7eb2e8f9f7	4127
<>	144:ef7eb2e8f9f7	4128	return HAL_OK;
<>	144:ef7eb2e8f9f7	4129	}
<>	144:ef7eb2e8f9f7	4130
<>	144:ef7eb2e8f9f7	4131	/**
<>	144:ef7eb2e8f9f7	4132	* @brief Handle ADD10 flag for Master
<>	144:ef7eb2e8f9f7	4133	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4134	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4135	* @retval HAL status
<>	144:ef7eb2e8f9f7	4136	*/
<>	144:ef7eb2e8f9f7	4137	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4138	{
<>	144:ef7eb2e8f9f7	4139	/* Send slave address */
<>	144:ef7eb2e8f9f7	4140	hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
<>	144:ef7eb2e8f9f7	4141
<>	144:ef7eb2e8f9f7	4142	return HAL_OK;
<>	144:ef7eb2e8f9f7	4143	}
<>	144:ef7eb2e8f9f7	4144
<>	144:ef7eb2e8f9f7	4145	/**
<>	144:ef7eb2e8f9f7	4146	* @brief Handle ADDR flag for Master
<>	144:ef7eb2e8f9f7	4147	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4148	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4149	* @retval HAL status
<>	144:ef7eb2e8f9f7	4150	*/
<>	144:ef7eb2e8f9f7	4151	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4152	{
<>	144:ef7eb2e8f9f7	4153	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4154	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	4155	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4156	uint32_t Prev_State = hi2c->PreviousState;
<>	144:ef7eb2e8f9f7	4157
<>	144:ef7eb2e8f9f7	4158	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	4159	{
<>	144:ef7eb2e8f9f7	4160	if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	4161	{
<>	144:ef7eb2e8f9f7	4162	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4163	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4164	}
<>	144:ef7eb2e8f9f7	4165	else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
<>	144:ef7eb2e8f9f7	4166	{
<>	144:ef7eb2e8f9f7	4167	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4168	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4169
<>	144:ef7eb2e8f9f7	4170	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4171	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4172
<>	144:ef7eb2e8f9f7	4173	hi2c->EventCount++;
<>	144:ef7eb2e8f9f7	4174	}
<>	144:ef7eb2e8f9f7	4175	else
<>	144:ef7eb2e8f9f7	4176	{
<>	144:ef7eb2e8f9f7	4177	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	4178	{
<>	144:ef7eb2e8f9f7	4179	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4180	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4181
<>	144:ef7eb2e8f9f7	4182	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4183	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4184	}
<>	144:ef7eb2e8f9f7	4185	else if(hi2c->XferCount == 1U)
<>	144:ef7eb2e8f9f7	4186	{
<>	144:ef7eb2e8f9f7	4187	if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
<>	144:ef7eb2e8f9f7	4188	{
<>	144:ef7eb2e8f9f7	4189	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4190	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4191
<>	144:ef7eb2e8f9f7	4192	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4193	{
<>	144:ef7eb2e8f9f7	4194	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4195	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4196
<>	144:ef7eb2e8f9f7	4197	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4198	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4199	}
<>	144:ef7eb2e8f9f7	4200	else
<>	144:ef7eb2e8f9f7	4201	{
<>	144:ef7eb2e8f9f7	4202	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4203	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4204
<>	144:ef7eb2e8f9f7	4205	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4206	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4207	}
<>	144:ef7eb2e8f9f7	4208	}
<>	144:ef7eb2e8f9f7	4209	/* Prepare next transfer or stop current transfer */
<>	144:ef7eb2e8f9f7	4210	else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
<>	144:ef7eb2e8f9f7	4211	&& (Prev_State != I2C_STATE_MASTER_BUSY_RX))
<>	144:ef7eb2e8f9f7	4212	{
<>	144:ef7eb2e8f9f7	4213	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4214	{
<>	144:ef7eb2e8f9f7	4215	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4216	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4217	}
<>	144:ef7eb2e8f9f7	4218	else
<>	144:ef7eb2e8f9f7	4219	{
<>	144:ef7eb2e8f9f7	4220	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4221	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4222	}
<>	144:ef7eb2e8f9f7	4223
<>	144:ef7eb2e8f9f7	4224	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4225	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4226	}
<>	144:ef7eb2e8f9f7	4227	else
<>	144:ef7eb2e8f9f7	4228	{
<>	144:ef7eb2e8f9f7	4229	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4230	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4231
<>	144:ef7eb2e8f9f7	4232	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4233	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4234
<>	144:ef7eb2e8f9f7	4235	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4236	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4237	}
<>	144:ef7eb2e8f9f7	4238	}
<>	144:ef7eb2e8f9f7	4239	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4240	{
<>	144:ef7eb2e8f9f7	4241	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	144:ef7eb2e8f9f7	4242	{
<>	144:ef7eb2e8f9f7	4243	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4244	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4245
<>	144:ef7eb2e8f9f7	4246	/* Enable Pos */
<>	144:ef7eb2e8f9f7	4247	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4248	}
<>	144:ef7eb2e8f9f7	4249	else
<>	144:ef7eb2e8f9f7	4250	{
<>	144:ef7eb2e8f9f7	4251	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4252	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4253	}
<>	144:ef7eb2e8f9f7	4254
<>	144:ef7eb2e8f9f7	4255	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4256	{
<>	144:ef7eb2e8f9f7	4257	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	4258	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	4259	}
<>	144:ef7eb2e8f9f7	4260
<>	144:ef7eb2e8f9f7	4261	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4262	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4263	}
<>	144:ef7eb2e8f9f7	4264	else
<>	144:ef7eb2e8f9f7	4265	{
<>	144:ef7eb2e8f9f7	4266	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4267	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4268
<>	144:ef7eb2e8f9f7	4269	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4270	{
<>	144:ef7eb2e8f9f7	4271	/* Enable Last DMA bit */
<>	144:ef7eb2e8f9f7	4272	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	4273	}
<>	144:ef7eb2e8f9f7	4274
<>	144:ef7eb2e8f9f7	4275	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4276	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4277	}
<>	144:ef7eb2e8f9f7	4278
<>	144:ef7eb2e8f9f7	4279	/* Reset Event counter */
<>	144:ef7eb2e8f9f7	4280	hi2c->EventCount = 0U;
<>	144:ef7eb2e8f9f7	4281	}
<>	144:ef7eb2e8f9f7	4282	}
<>	144:ef7eb2e8f9f7	4283	else
<>	144:ef7eb2e8f9f7	4284	{
<>	144:ef7eb2e8f9f7	4285	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4286	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4287	}
<>	144:ef7eb2e8f9f7	4288
<>	144:ef7eb2e8f9f7	4289	return HAL_OK;
<>	144:ef7eb2e8f9f7	4290	}
<>	144:ef7eb2e8f9f7	4291
<>	144:ef7eb2e8f9f7	4292	/**
<>	144:ef7eb2e8f9f7	4293	* @brief Handle TXE flag for Slave
<>	144:ef7eb2e8f9f7	4294	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4295	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4296	* @retval HAL status
<>	144:ef7eb2e8f9f7	4297	*/
<>	144:ef7eb2e8f9f7	4298	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4299	{
<>	144:ef7eb2e8f9f7	4300	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4301	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4302
<>	144:ef7eb2e8f9f7	4303	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4304	{
<>	144:ef7eb2e8f9f7	4305	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4306	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4307	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4308
<>	144:ef7eb2e8f9f7	4309	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4310	{
<>	144:ef7eb2e8f9f7	4311	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4312	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4313
<>	144:ef7eb2e8f9f7	4314	/* Set state at HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4315	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	4316	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4317
<>	144:ef7eb2e8f9f7	4318	/* Call the Tx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4319	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4320	}
<>	144:ef7eb2e8f9f7	4321	}
<>	144:ef7eb2e8f9f7	4322	return HAL_OK;
<>	144:ef7eb2e8f9f7	4323	}
<>	144:ef7eb2e8f9f7	4324
<>	144:ef7eb2e8f9f7	4325	/**
<>	144:ef7eb2e8f9f7	4326	* @brief Handle BTF flag for Slave transmitter
<>	144:ef7eb2e8f9f7	4327	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4328	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4329	* @retval HAL status
<>	144:ef7eb2e8f9f7	4330	*/
<>	144:ef7eb2e8f9f7	4331	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4332	{
<>	144:ef7eb2e8f9f7	4333	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4334	{
<>	144:ef7eb2e8f9f7	4335	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4336	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4337	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4338	}
<>	144:ef7eb2e8f9f7	4339	return HAL_OK;
<>	144:ef7eb2e8f9f7	4340	}
<>	144:ef7eb2e8f9f7	4341
<>	144:ef7eb2e8f9f7	4342	/**
<>	144:ef7eb2e8f9f7	4343	* @brief Handle RXNE flag for Slave
<>	144:ef7eb2e8f9f7	4344	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4345	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4346	* @retval HAL status
<>	144:ef7eb2e8f9f7	4347	*/
<>	144:ef7eb2e8f9f7	4348	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4349	{
<>	144:ef7eb2e8f9f7	4350	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4351	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4352
<>	144:ef7eb2e8f9f7	4353	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4354	{
<>	144:ef7eb2e8f9f7	4355	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4356	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4357	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4358
<>	144:ef7eb2e8f9f7	4359	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4360	{
<>	144:ef7eb2e8f9f7	4361	/* Last Byte is received, disable Interrupt */
<>	144:ef7eb2e8f9f7	4362	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4363
<>	144:ef7eb2e8f9f7	4364	/* Set state at HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4365	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
<>	144:ef7eb2e8f9f7	4366	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4367
<>	144:ef7eb2e8f9f7	4368	/* Call the Rx complete callback to inform upper layer of the end of receive process */
<>	144:ef7eb2e8f9f7	4369	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4370	}
<>	144:ef7eb2e8f9f7	4371	}
<>	144:ef7eb2e8f9f7	4372	return HAL_OK;
<>	144:ef7eb2e8f9f7	4373	}
<>	144:ef7eb2e8f9f7	4374
<>	144:ef7eb2e8f9f7	4375	/**
<>	144:ef7eb2e8f9f7	4376	* @brief Handle BTF flag for Slave receiver
<>	144:ef7eb2e8f9f7	4377	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4378	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4379	* @retval HAL status
<>	144:ef7eb2e8f9f7	4380	*/
<>	144:ef7eb2e8f9f7	4381	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4382	{
<>	144:ef7eb2e8f9f7	4383	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4384	{
<>	144:ef7eb2e8f9f7	4385	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4386	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4387	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4388	}
<>	144:ef7eb2e8f9f7	4389	return HAL_OK;
<>	144:ef7eb2e8f9f7	4390	}
<>	144:ef7eb2e8f9f7	4391
<>	144:ef7eb2e8f9f7	4392	/**
<>	144:ef7eb2e8f9f7	4393	* @brief Handle ADD flag for Slave
<>	144:ef7eb2e8f9f7	4394	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4395	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4396	* @retval HAL status
<>	144:ef7eb2e8f9f7	4397	*/
<>	144:ef7eb2e8f9f7	4398	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4399	{
<>	144:ef7eb2e8f9f7	4400	uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
<>	144:ef7eb2e8f9f7	4401	uint16_t SlaveAddrCode = 0U;
<>	144:ef7eb2e8f9f7	4402
<>	144:ef7eb2e8f9f7	4403	/* Transfer Direction requested by Master */
<>	144:ef7eb2e8f9f7	4404	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
<>	144:ef7eb2e8f9f7	4405	{
<>	144:ef7eb2e8f9f7	4406	TransferDirection = I2C_DIRECTION_TRANSMIT;
<>	144:ef7eb2e8f9f7	4407	}
<>	144:ef7eb2e8f9f7	4408
<>	144:ef7eb2e8f9f7	4409	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
<>	144:ef7eb2e8f9f7	4410	{
<>	144:ef7eb2e8f9f7	4411	SlaveAddrCode = hi2c->Init.OwnAddress1;
<>	144:ef7eb2e8f9f7	4412	}
<>	144:ef7eb2e8f9f7	4413	else
<>	144:ef7eb2e8f9f7	4414	{
<>	144:ef7eb2e8f9f7	4415	SlaveAddrCode = hi2c->Init.OwnAddress2;
<>	144:ef7eb2e8f9f7	4416	}
<>	144:ef7eb2e8f9f7	4417
<>	144:ef7eb2e8f9f7	4418	/* Call Slave Addr callback */
<>	144:ef7eb2e8f9f7	4419	HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
<>	144:ef7eb2e8f9f7	4420
<>	144:ef7eb2e8f9f7	4421	return HAL_OK;
<>	144:ef7eb2e8f9f7	4422	}
<>	144:ef7eb2e8f9f7	4423
<>	144:ef7eb2e8f9f7	4424	/**
<>	144:ef7eb2e8f9f7	4425	* @brief Handle STOPF flag for Slave
<>	144:ef7eb2e8f9f7	4426	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4427	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4428	* @retval HAL status
<>	144:ef7eb2e8f9f7	4429	*/
<>	144:ef7eb2e8f9f7	4430	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4431	{
<>	144:ef7eb2e8f9f7	4432	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4433	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4434
<>	144:ef7eb2e8f9f7	4435	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4436	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4437
<>	144:ef7eb2e8f9f7	4438	/* Clear STOPF flag */
<>	144:ef7eb2e8f9f7	4439	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4440
<>	144:ef7eb2e8f9f7	4441	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4442	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4443
<>	144:ef7eb2e8f9f7	4444	/* If a DMA is ongoing, Update handle size context */
<>	144:ef7eb2e8f9f7	4445	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4446	{
<>	144:ef7eb2e8f9f7	4447	if((hi2c->State == HAL_I2C_STATE_BUSY_RX) \|\| (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4448	{
<>	144:ef7eb2e8f9f7	4449	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	4450	}
<>	144:ef7eb2e8f9f7	4451	else
<>	144:ef7eb2e8f9f7	4452	{
<>	144:ef7eb2e8f9f7	4453	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	4454	}
<>	144:ef7eb2e8f9f7	4455	}
<>	144:ef7eb2e8f9f7	4456
<>	144:ef7eb2e8f9f7	4457	/* All data are not transferred, so set error code accordingly */
<>	144:ef7eb2e8f9f7	4458	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4459	{
<>	144:ef7eb2e8f9f7	4460	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4461	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	4462	{
<>	144:ef7eb2e8f9f7	4463	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4464	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4465	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4466	}
<>	144:ef7eb2e8f9f7	4467
<>	144:ef7eb2e8f9f7	4468	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4469	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	4470	{
<>	144:ef7eb2e8f9f7	4471	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4472	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4473	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4474	}
<>	144:ef7eb2e8f9f7	4475
<>	144:ef7eb2e8f9f7	4476	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	144:ef7eb2e8f9f7	4477	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	4478	}
<>	144:ef7eb2e8f9f7	4479
<>	144:ef7eb2e8f9f7	4480	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	4481	{
<>	144:ef7eb2e8f9f7	4482	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4483	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	4484	}
<>	144:ef7eb2e8f9f7	4485	else
<>	144:ef7eb2e8f9f7	4486	{
<>	144:ef7eb2e8f9f7	4487	if((CurrentState == HAL_I2C_STATE_LISTEN ) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) \|\| \
<>	144:ef7eb2e8f9f7	4488	(CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	144:ef7eb2e8f9f7	4489	{
<>	144:ef7eb2e8f9f7	4490	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4491	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4492	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4493	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4494
<>	144:ef7eb2e8f9f7	4495	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4496	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4497	}
<>	144:ef7eb2e8f9f7	4498	else
<>	144:ef7eb2e8f9f7	4499	{
<>	144:ef7eb2e8f9f7	4500	if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX))
<>	144:ef7eb2e8f9f7	4501	{
<>	144:ef7eb2e8f9f7	4502	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4503	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4504	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4505
<>	144:ef7eb2e8f9f7	4506	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4507	}
<>	144:ef7eb2e8f9f7	4508	}
<>	144:ef7eb2e8f9f7	4509	}
<>	144:ef7eb2e8f9f7	4510	return HAL_OK;
<>	144:ef7eb2e8f9f7	4511	}
<>	144:ef7eb2e8f9f7	4512
<>	144:ef7eb2e8f9f7	4513	/**
<>	144:ef7eb2e8f9f7	4514	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4515	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4516	* @retval HAL status
<>	144:ef7eb2e8f9f7	4517	*/
<>	144:ef7eb2e8f9f7	4518	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4519	{
<>	144:ef7eb2e8f9f7	4520	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4521	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4522	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4523
<>	144:ef7eb2e8f9f7	4524	if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME)) && \
<>	144:ef7eb2e8f9f7	4525	(CurrentState == HAL_I2C_STATE_LISTEN))
<>	144:ef7eb2e8f9f7	4526	{
<>	144:ef7eb2e8f9f7	4527	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4528
<>	144:ef7eb2e8f9f7	4529	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4530	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4531
<>	144:ef7eb2e8f9f7	4532	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4533	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4534
<>	144:ef7eb2e8f9f7	4535	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4536	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4537
<>	144:ef7eb2e8f9f7	4538	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4539	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4540	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4541
<>	144:ef7eb2e8f9f7	4542	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4543	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4544	}
<>	144:ef7eb2e8f9f7	4545	else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	4546	{
<>	144:ef7eb2e8f9f7	4547	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4548	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	144:ef7eb2e8f9f7	4549	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4550	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4551
<>	144:ef7eb2e8f9f7	4552	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4553	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4554
<>	144:ef7eb2e8f9f7	4555	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	4556	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4557
<>	144:ef7eb2e8f9f7	4558	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	4559	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4560
<>	144:ef7eb2e8f9f7	4561	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4562	}
<>	144:ef7eb2e8f9f7	4563	else
<>	144:ef7eb2e8f9f7	4564	{
<>	144:ef7eb2e8f9f7	4565	/* Clear AF flag only */
<>	144:ef7eb2e8f9f7	4566	/* State Listen, but XferOptions == FIRST or NEXT */
<>	144:ef7eb2e8f9f7	4567	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	4568	}
<>	144:ef7eb2e8f9f7	4569
<>	144:ef7eb2e8f9f7	4570	return HAL_OK;
<>	144:ef7eb2e8f9f7	4571	}
<>	144:ef7eb2e8f9f7	4572
<>	144:ef7eb2e8f9f7	4573	/**
<>	144:ef7eb2e8f9f7	4574	* @brief I2C interrupts error process
<>	144:ef7eb2e8f9f7	4575	* @param hi2c I2C handle.
<>	144:ef7eb2e8f9f7	4576	* @retval None
<>	144:ef7eb2e8f9f7	4577	*/
<>	144:ef7eb2e8f9f7	4578	static void I2C_ITError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4579	{
<>	144:ef7eb2e8f9f7	4580	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4581	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	4582
<>	144:ef7eb2e8f9f7	4583	if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	144:ef7eb2e8f9f7	4584	{
<>	144:ef7eb2e8f9f7	4585	/* keep HAL_I2C_STATE_LISTEN */
<>	144:ef7eb2e8f9f7	4586	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4587	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	144:ef7eb2e8f9f7	4588	}
<>	144:ef7eb2e8f9f7	4589	else
<>	144:ef7eb2e8f9f7	4590	{
<>	144:ef7eb2e8f9f7	4591	/* If state is an abort treatment on going, don't change state */
<>	144:ef7eb2e8f9f7	4592	/* This change will be do later */
<>	144:ef7eb2e8f9f7	4593	if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
<>	144:ef7eb2e8f9f7	4594	{
<>	144:ef7eb2e8f9f7	4595	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4596	}
<>	144:ef7eb2e8f9f7	4597	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4598	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4599	}
<>	144:ef7eb2e8f9f7	4600
<>	144:ef7eb2e8f9f7	4601	/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
<>	144:ef7eb2e8f9f7	4602	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	4603
<>	144:ef7eb2e8f9f7	4604	/* Abort DMA transfer */
<>	144:ef7eb2e8f9f7	4605	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	144:ef7eb2e8f9f7	4606	{
<>	144:ef7eb2e8f9f7	4607	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	4608
<>	144:ef7eb2e8f9f7	4609	if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
<>	144:ef7eb2e8f9f7	4610	{
<>	144:ef7eb2e8f9f7	4611	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4612	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4613	hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4614
<>	144:ef7eb2e8f9f7	4615	if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4616	{
<>	144:ef7eb2e8f9f7	4617	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	144:ef7eb2e8f9f7	4618	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	4619
<>	144:ef7eb2e8f9f7	4620	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4621
<>	144:ef7eb2e8f9f7	4622	/* Call Directly XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4623	hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<>	144:ef7eb2e8f9f7	4624	}
<>	144:ef7eb2e8f9f7	4625	}
<>	144:ef7eb2e8f9f7	4626	else
<>	144:ef7eb2e8f9f7	4627	{
<>	144:ef7eb2e8f9f7	4628	/* Set the DMA Abort callback :
<>	144:ef7eb2e8f9f7	4629	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	4630	hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<>	144:ef7eb2e8f9f7	4631
<>	144:ef7eb2e8f9f7	4632	if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	4633	{
<>	144:ef7eb2e8f9f7	4634	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4635	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	4636	{
<>	144:ef7eb2e8f9f7	4637	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4638	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4639	}
<>	144:ef7eb2e8f9f7	4640
<>	144:ef7eb2e8f9f7	4641	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	144:ef7eb2e8f9f7	4642	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	4643
<>	144:ef7eb2e8f9f7	4644	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4645
<>	144:ef7eb2e8f9f7	4646	/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	4647	hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<>	144:ef7eb2e8f9f7	4648	}
<>	144:ef7eb2e8f9f7	4649	}
<>	144:ef7eb2e8f9f7	4650	}
<>	144:ef7eb2e8f9f7	4651	else if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	4652	{
<>	144:ef7eb2e8f9f7	4653	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4654	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	4655
<>	144:ef7eb2e8f9f7	4656	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4657	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	4658	{
<>	144:ef7eb2e8f9f7	4659	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4660	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4661	}
<>	144:ef7eb2e8f9f7	4662
<>	144:ef7eb2e8f9f7	4663	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	144:ef7eb2e8f9f7	4664	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	4665
<>	144:ef7eb2e8f9f7	4666	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	4667	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4668	}
<>	144:ef7eb2e8f9f7	4669	else
<>	144:ef7eb2e8f9f7	4670	{
<>	144:ef7eb2e8f9f7	4671	/* Store Last receive data if any */
<>	144:ef7eb2e8f9f7	4672	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	144:ef7eb2e8f9f7	4673	{
<>	144:ef7eb2e8f9f7	4674	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4675	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4676	}
<>	144:ef7eb2e8f9f7	4677
<>	144:ef7eb2e8f9f7	4678	/* Call user error callback */
<>	144:ef7eb2e8f9f7	4679	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	4680	}
<>	144:ef7eb2e8f9f7	4681	/* STOP Flag is not set after a NACK reception */
<>	144:ef7eb2e8f9f7	4682	/* So may inform upper layer that listen phase is stopped */
<>	144:ef7eb2e8f9f7	4683	/* during NACK error treatment */
<>	144:ef7eb2e8f9f7	4684	if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
<>	144:ef7eb2e8f9f7	4685	{
<>	144:ef7eb2e8f9f7	4686	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	144:ef7eb2e8f9f7	4687	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	4688	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4689	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4690
<>	144:ef7eb2e8f9f7	4691	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	144:ef7eb2e8f9f7	4692	HAL_I2C_ListenCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4693	}
<>	144:ef7eb2e8f9f7	4694	}
<>	144:ef7eb2e8f9f7	4695
<>	144:ef7eb2e8f9f7	4696	/**
<>	144:ef7eb2e8f9f7	4697	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4698	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4699	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4700	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4701	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4702	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4703	* @retval HAL status
<>	144:ef7eb2e8f9f7	4704	*/
<>	144:ef7eb2e8f9f7	4705	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4706	{
<>	144:ef7eb2e8f9f7	4707	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4708	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4709
<>	144:ef7eb2e8f9f7	4710	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4711	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4712	{
<>	144:ef7eb2e8f9f7	4713	/* Generate Start */
<>	144:ef7eb2e8f9f7	4714	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4715	}
<>	144:ef7eb2e8f9f7	4716	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<>	144:ef7eb2e8f9f7	4717	{
<>	144:ef7eb2e8f9f7	4718	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4719	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4720	}
<>	144:ef7eb2e8f9f7	4721
<>	144:ef7eb2e8f9f7	4722	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4723	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4724	{
<>	144:ef7eb2e8f9f7	4725	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4726	}
<>	144:ef7eb2e8f9f7	4727
<>	144:ef7eb2e8f9f7	4728	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4729	{
<>	144:ef7eb2e8f9f7	4730	/* Send slave address */
<>	144:ef7eb2e8f9f7	4731	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4732	}
<>	144:ef7eb2e8f9f7	4733	else
<>	144:ef7eb2e8f9f7	4734	{
<>	144:ef7eb2e8f9f7	4735	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4736	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4737
<>	144:ef7eb2e8f9f7	4738	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4739	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4740	{
<>	144:ef7eb2e8f9f7	4741	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4742	{
<>	144:ef7eb2e8f9f7	4743	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4744	}
<>	144:ef7eb2e8f9f7	4745	else
<>	144:ef7eb2e8f9f7	4746	{
<>	144:ef7eb2e8f9f7	4747	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4748	}
<>	144:ef7eb2e8f9f7	4749	}
<>	144:ef7eb2e8f9f7	4750
<>	144:ef7eb2e8f9f7	4751	/* Send slave address */
<>	144:ef7eb2e8f9f7	4752	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4753	}
<>	144:ef7eb2e8f9f7	4754
<>	144:ef7eb2e8f9f7	4755	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4756	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4757	{
<>	144:ef7eb2e8f9f7	4758	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4759	{
<>	144:ef7eb2e8f9f7	4760	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4761	}
<>	144:ef7eb2e8f9f7	4762	else
<>	144:ef7eb2e8f9f7	4763	{
<>	144:ef7eb2e8f9f7	4764	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4765	}
<>	144:ef7eb2e8f9f7	4766	}
<>	144:ef7eb2e8f9f7	4767
<>	144:ef7eb2e8f9f7	4768	return HAL_OK;
<>	144:ef7eb2e8f9f7	4769	}
<>	144:ef7eb2e8f9f7	4770
<>	144:ef7eb2e8f9f7	4771	/**
<>	144:ef7eb2e8f9f7	4772	* @brief Master sends target device address for read request.
<>	144:ef7eb2e8f9f7	4773	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4774	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4775	* @param DevAddress Target device address: The device 7 bits address value
<>	144:ef7eb2e8f9f7	4776	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4777	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4778	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4779	* @retval HAL status
<>	144:ef7eb2e8f9f7	4780	*/
<>	144:ef7eb2e8f9f7	4781	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4782	{
<>	144:ef7eb2e8f9f7	4783	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	4784	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	144:ef7eb2e8f9f7	4785
<>	144:ef7eb2e8f9f7	4786	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4787	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4788
<>	144:ef7eb2e8f9f7	4789	/* Generate Start condition if first transfer */
<>	144:ef7eb2e8f9f7	4790	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	144:ef7eb2e8f9f7	4791	{
<>	144:ef7eb2e8f9f7	4792	/* Generate Start */
<>	144:ef7eb2e8f9f7	4793	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4794	}
<>	144:ef7eb2e8f9f7	4795	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	144:ef7eb2e8f9f7	4796	{
<>	144:ef7eb2e8f9f7	4797	/* Generate ReStart */
<>	144:ef7eb2e8f9f7	4798	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4799	}
<>	144:ef7eb2e8f9f7	4800
<>	144:ef7eb2e8f9f7	4801	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4802	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4803	{
<>	144:ef7eb2e8f9f7	4804	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4805	}
<>	144:ef7eb2e8f9f7	4806
<>	144:ef7eb2e8f9f7	4807	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4808	{
<>	144:ef7eb2e8f9f7	4809	/* Send slave address */
<>	144:ef7eb2e8f9f7	4810	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4811	}
<>	144:ef7eb2e8f9f7	4812	else
<>	144:ef7eb2e8f9f7	4813	{
<>	144:ef7eb2e8f9f7	4814	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4815	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4816
<>	144:ef7eb2e8f9f7	4817	/* Wait until ADD10 flag is set */
<>	144:ef7eb2e8f9f7	4818	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4819	{
<>	144:ef7eb2e8f9f7	4820	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4821	{
<>	144:ef7eb2e8f9f7	4822	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4823	}
<>	144:ef7eb2e8f9f7	4824	else
<>	144:ef7eb2e8f9f7	4825	{
<>	144:ef7eb2e8f9f7	4826	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4827	}
<>	144:ef7eb2e8f9f7	4828	}
<>	144:ef7eb2e8f9f7	4829
<>	144:ef7eb2e8f9f7	4830	/* Send slave address */
<>	144:ef7eb2e8f9f7	4831	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4832
<>	144:ef7eb2e8f9f7	4833	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4834	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4835	{
<>	144:ef7eb2e8f9f7	4836	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4837	{
<>	144:ef7eb2e8f9f7	4838	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4839	}
<>	144:ef7eb2e8f9f7	4840	else
<>	144:ef7eb2e8f9f7	4841	{
<>	144:ef7eb2e8f9f7	4842	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4843	}
<>	144:ef7eb2e8f9f7	4844	}
<>	144:ef7eb2e8f9f7	4845
<>	144:ef7eb2e8f9f7	4846	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4847	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4848
<>	144:ef7eb2e8f9f7	4849	/* Generate Restart */
<>	144:ef7eb2e8f9f7	4850	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4851
<>	144:ef7eb2e8f9f7	4852	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4853	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4854	{
<>	144:ef7eb2e8f9f7	4855	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4856	}
<>	144:ef7eb2e8f9f7	4857
<>	144:ef7eb2e8f9f7	4858	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4859	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4860	}
<>	144:ef7eb2e8f9f7	4861
<>	144:ef7eb2e8f9f7	4862	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4863	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4864	{
<>	144:ef7eb2e8f9f7	4865	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4866	{
<>	144:ef7eb2e8f9f7	4867	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4868	}
<>	144:ef7eb2e8f9f7	4869	else
<>	144:ef7eb2e8f9f7	4870	{
<>	144:ef7eb2e8f9f7	4871	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4872	}
<>	144:ef7eb2e8f9f7	4873	}
<>	144:ef7eb2e8f9f7	4874
<>	144:ef7eb2e8f9f7	4875	return HAL_OK;
<>	144:ef7eb2e8f9f7	4876	}
<>	144:ef7eb2e8f9f7	4877
<>	144:ef7eb2e8f9f7	4878	/**
<>	144:ef7eb2e8f9f7	4879	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	4880	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4881	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4882	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4883	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4884	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4885	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4886	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4887	* @retval HAL status
<>	144:ef7eb2e8f9f7	4888	*/
<>	144:ef7eb2e8f9f7	4889	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4890	{
<>	144:ef7eb2e8f9f7	4891	/* Generate Start */
<>	144:ef7eb2e8f9f7	4892	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4893
<>	144:ef7eb2e8f9f7	4894	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4895	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4896	{
<>	144:ef7eb2e8f9f7	4897	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4898	}
<>	144:ef7eb2e8f9f7	4899
<>	144:ef7eb2e8f9f7	4900	/* Send slave address */
<>	144:ef7eb2e8f9f7	4901	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4902
<>	144:ef7eb2e8f9f7	4903	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4904	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4905	{
<>	144:ef7eb2e8f9f7	4906	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4907	{
<>	144:ef7eb2e8f9f7	4908	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4909	}
<>	144:ef7eb2e8f9f7	4910	else
<>	144:ef7eb2e8f9f7	4911	{
<>	144:ef7eb2e8f9f7	4912	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4913	}
<>	144:ef7eb2e8f9f7	4914	}
<>	144:ef7eb2e8f9f7	4915
<>	144:ef7eb2e8f9f7	4916	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4917	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4918
<>	144:ef7eb2e8f9f7	4919	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4920	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4921	{
<>	144:ef7eb2e8f9f7	4922	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4923	{
<>	144:ef7eb2e8f9f7	4924	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4925	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4926	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4927	}
<>	144:ef7eb2e8f9f7	4928	else
<>	144:ef7eb2e8f9f7	4929	{
<>	144:ef7eb2e8f9f7	4930	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4931	}
<>	144:ef7eb2e8f9f7	4932	}
<>	144:ef7eb2e8f9f7	4933
<>	144:ef7eb2e8f9f7	4934	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	4935	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	4936	{
<>	144:ef7eb2e8f9f7	4937	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	4938	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4939	}
<>	144:ef7eb2e8f9f7	4940	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	4941	else
<>	144:ef7eb2e8f9f7	4942	{
<>	144:ef7eb2e8f9f7	4943	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	4944	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	4945
<>	144:ef7eb2e8f9f7	4946	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	4947	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4948	{
<>	144:ef7eb2e8f9f7	4949	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4950	{
<>	144:ef7eb2e8f9f7	4951	/* Generate Stop */
<>	144:ef7eb2e8f9f7	4952	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4953	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4954	}
<>	144:ef7eb2e8f9f7	4955	else
<>	144:ef7eb2e8f9f7	4956	{
<>	144:ef7eb2e8f9f7	4957	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4958	}
<>	144:ef7eb2e8f9f7	4959	}
<>	144:ef7eb2e8f9f7	4960
<>	144:ef7eb2e8f9f7	4961	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	4962	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	4963	}
<>	144:ef7eb2e8f9f7	4964
<>	144:ef7eb2e8f9f7	4965	return HAL_OK;
<>	144:ef7eb2e8f9f7	4966	}
<>	144:ef7eb2e8f9f7	4967
<>	144:ef7eb2e8f9f7	4968	/**
<>	144:ef7eb2e8f9f7	4969	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	4970	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	4971	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4972	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4973	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4974	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4975	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	4976	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4977	* @retval HAL status
<>	144:ef7eb2e8f9f7	4978	*/
<>	144:ef7eb2e8f9f7	4979	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4980	{
<>	144:ef7eb2e8f9f7	4981	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	4982	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	4983
<>	144:ef7eb2e8f9f7	4984	/* Generate Start */
<>	144:ef7eb2e8f9f7	4985	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4986
<>	144:ef7eb2e8f9f7	4987	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	4988	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4989	{
<>	144:ef7eb2e8f9f7	4990	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4991	}
<>	144:ef7eb2e8f9f7	4992
<>	144:ef7eb2e8f9f7	4993	/* Send slave address */
<>	144:ef7eb2e8f9f7	4994	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4995
<>	144:ef7eb2e8f9f7	4996	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	4997	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4998	{
<>	144:ef7eb2e8f9f7	4999	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5000	{
<>	144:ef7eb2e8f9f7	5001	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5002	}
<>	144:ef7eb2e8f9f7	5003	else
<>	144:ef7eb2e8f9f7	5004	{
<>	144:ef7eb2e8f9f7	5005	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5006	}
<>	144:ef7eb2e8f9f7	5007	}
<>	144:ef7eb2e8f9f7	5008
<>	144:ef7eb2e8f9f7	5009	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	5010	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	5011
<>	144:ef7eb2e8f9f7	5012	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5013	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5014	{
<>	144:ef7eb2e8f9f7	5015	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5016	{
<>	144:ef7eb2e8f9f7	5017	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5018	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5019	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5020	}
<>	144:ef7eb2e8f9f7	5021	else
<>	144:ef7eb2e8f9f7	5022	{
<>	144:ef7eb2e8f9f7	5023	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5024	}
<>	144:ef7eb2e8f9f7	5025	}
<>	144:ef7eb2e8f9f7	5026
<>	144:ef7eb2e8f9f7	5027	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	5028	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	5029	{
<>	144:ef7eb2e8f9f7	5030	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	5031	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5032	}
<>	144:ef7eb2e8f9f7	5033	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	5034	else
<>	144:ef7eb2e8f9f7	5035	{
<>	144:ef7eb2e8f9f7	5036	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	5037	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	5038
<>	144:ef7eb2e8f9f7	5039	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5040	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5041	{
<>	144:ef7eb2e8f9f7	5042	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5043	{
<>	144:ef7eb2e8f9f7	5044	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5045	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5046	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5047	}
<>	144:ef7eb2e8f9f7	5048	else
<>	144:ef7eb2e8f9f7	5049	{
<>	144:ef7eb2e8f9f7	5050	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5051	}
<>	144:ef7eb2e8f9f7	5052	}
<>	144:ef7eb2e8f9f7	5053
<>	144:ef7eb2e8f9f7	5054	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	5055	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5056	}
<>	144:ef7eb2e8f9f7	5057
<>	144:ef7eb2e8f9f7	5058	/* Wait until TXE flag is set */
<>	144:ef7eb2e8f9f7	5059	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5060	{
<>	144:ef7eb2e8f9f7	5061	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5062	{
<>	144:ef7eb2e8f9f7	5063	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5064	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5065	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5066	}
<>	144:ef7eb2e8f9f7	5067	else
<>	144:ef7eb2e8f9f7	5068	{
<>	144:ef7eb2e8f9f7	5069	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5070	}
<>	144:ef7eb2e8f9f7	5071	}
<>	144:ef7eb2e8f9f7	5072
<>	144:ef7eb2e8f9f7	5073	/* Generate Restart */
<>	144:ef7eb2e8f9f7	5074	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	5075
<>	144:ef7eb2e8f9f7	5076	/* Wait until SB flag is set */
<>	144:ef7eb2e8f9f7	5077	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5078	{
<>	144:ef7eb2e8f9f7	5079	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5080	}
<>	144:ef7eb2e8f9f7	5081
<>	144:ef7eb2e8f9f7	5082	/* Send slave address */
<>	144:ef7eb2e8f9f7	5083	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	5084
<>	144:ef7eb2e8f9f7	5085	/* Wait until ADDR flag is set */
<>	144:ef7eb2e8f9f7	5086	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5087	{
<>	144:ef7eb2e8f9f7	5088	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5089	{
<>	144:ef7eb2e8f9f7	5090	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5091	}
<>	144:ef7eb2e8f9f7	5092	else
<>	144:ef7eb2e8f9f7	5093	{
<>	144:ef7eb2e8f9f7	5094	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5095	}
<>	144:ef7eb2e8f9f7	5096	}
<>	144:ef7eb2e8f9f7	5097
<>	144:ef7eb2e8f9f7	5098	return HAL_OK;
<>	144:ef7eb2e8f9f7	5099	}
<>	144:ef7eb2e8f9f7	5100
<>	144:ef7eb2e8f9f7	5101	/**
<>	144:ef7eb2e8f9f7	5102	* @brief DMA I2C process complete callback.
<>	144:ef7eb2e8f9f7	5103	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5104	* @retval None
<>	144:ef7eb2e8f9f7	5105	*/
<>	144:ef7eb2e8f9f7	5106	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5107	{
<>	144:ef7eb2e8f9f7	5108	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	5109
<>	144:ef7eb2e8f9f7	5110	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	144:ef7eb2e8f9f7	5111	uint32_t CurrentState = hi2c->State;
<>	144:ef7eb2e8f9f7	5112	uint32_t CurrentMode = hi2c->Mode;
<>	144:ef7eb2e8f9f7	5113
<>	144:ef7eb2e8f9f7	5114	if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
<>	144:ef7eb2e8f9f7	5115	{
<>	144:ef7eb2e8f9f7	5116	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	5117	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	5118
<>	144:ef7eb2e8f9f7	5119	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5120
<>	144:ef7eb2e8f9f7	5121	/* Enable EVT and ERR interrupt */
<>	144:ef7eb2e8f9f7	5122	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	5123	}
<>	144:ef7eb2e8f9f7	5124	else
<>	144:ef7eb2e8f9f7	5125	{
<>	144:ef7eb2e8f9f7	5126	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5127	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5128
<>	144:ef7eb2e8f9f7	5129	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5130	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5131
<>	144:ef7eb2e8f9f7	5132	/* Disable Last DMA */
<>	144:ef7eb2e8f9f7	5133	hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	5134
<>	144:ef7eb2e8f9f7	5135	/* Disable DMA Request */
<>	144:ef7eb2e8f9f7	5136	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	5137
<>	144:ef7eb2e8f9f7	5138	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5139
<>	144:ef7eb2e8f9f7	5140	/* Check if Errors has been detected during transfer */
<>	144:ef7eb2e8f9f7	5141	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	5142	{
<>	144:ef7eb2e8f9f7	5143	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5144	}
<>	144:ef7eb2e8f9f7	5145	else
<>	144:ef7eb2e8f9f7	5146	{
<>	144:ef7eb2e8f9f7	5147	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5148
<>	144:ef7eb2e8f9f7	5149	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	5150	{
<>	144:ef7eb2e8f9f7	5151	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5152
<>	144:ef7eb2e8f9f7	5153	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5154	}
<>	144:ef7eb2e8f9f7	5155	else
<>	144:ef7eb2e8f9f7	5156	{
<>	144:ef7eb2e8f9f7	5157	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5158
<>	144:ef7eb2e8f9f7	5159	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5160	}
<>	144:ef7eb2e8f9f7	5161	}
<>	144:ef7eb2e8f9f7	5162	}
<>	144:ef7eb2e8f9f7	5163	}
<>	144:ef7eb2e8f9f7	5164
<>	144:ef7eb2e8f9f7	5165	/**
<>	144:ef7eb2e8f9f7	5166	* @brief DMA I2C communication error callback.
<>	144:ef7eb2e8f9f7	5167	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5168	* @retval None
<>	144:ef7eb2e8f9f7	5169	*/
<>	144:ef7eb2e8f9f7	5170	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5171	{
<>	144:ef7eb2e8f9f7	5172	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	5173
<>	144:ef7eb2e8f9f7	5174	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5175	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5176
<>	144:ef7eb2e8f9f7	5177	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5178
<>	144:ef7eb2e8f9f7	5179	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5180	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5181
<>	144:ef7eb2e8f9f7	5182	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
<>	144:ef7eb2e8f9f7	5183
<>	144:ef7eb2e8f9f7	5184	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5185	}
<>	144:ef7eb2e8f9f7	5186
<>	144:ef7eb2e8f9f7	5187	/**
<>	144:ef7eb2e8f9f7	5188	* @brief DMA I2C communication abort callback
<>	144:ef7eb2e8f9f7	5189	* (To be called at end of DMA Abort procedure).
<>	144:ef7eb2e8f9f7	5190	* @param hdma: DMA handle.
<>	144:ef7eb2e8f9f7	5191	* @retval None
<>	144:ef7eb2e8f9f7	5192	*/
<>	144:ef7eb2e8f9f7	5193	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5194	{
<>	144:ef7eb2e8f9f7	5195	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	5196
<>	144:ef7eb2e8f9f7	5197	/* Disable Acknowledge */
<>	144:ef7eb2e8f9f7	5198	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5199
<>	144:ef7eb2e8f9f7	5200	hi2c->XferCount = 0U;
<>	144:ef7eb2e8f9f7	5201
<>	144:ef7eb2e8f9f7	5202	/* Reset XferAbortCallback */
<>	144:ef7eb2e8f9f7	5203	hi2c->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5204	hi2c->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	5205
<>	144:ef7eb2e8f9f7	5206	/* Check if come from abort from user */
<>	144:ef7eb2e8f9f7	5207	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	144:ef7eb2e8f9f7	5208	{
<>	144:ef7eb2e8f9f7	5209	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5210	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5211	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	5212
<>	144:ef7eb2e8f9f7	5213	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	144:ef7eb2e8f9f7	5214	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	5215
<>	144:ef7eb2e8f9f7	5216	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5217	HAL_I2C_AbortCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	5218	}
<>	144:ef7eb2e8f9f7	5219	else
<>	144:ef7eb2e8f9f7	5220	{
<>	144:ef7eb2e8f9f7	5221	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5222	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5223
<>	144:ef7eb2e8f9f7	5224	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	144:ef7eb2e8f9f7	5225	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	5226
<>	144:ef7eb2e8f9f7	5227	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	144:ef7eb2e8f9f7	5228	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5229	}
<>	144:ef7eb2e8f9f7	5230	}
<>	144:ef7eb2e8f9f7	5231
<>	144:ef7eb2e8f9f7	5232	/**
<>	144:ef7eb2e8f9f7	5233	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	5234	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5235	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5236	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5237	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	5238	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5239	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5240	* @retval HAL status
<>	144:ef7eb2e8f9f7	5241	*/
<>	144:ef7eb2e8f9f7	5242	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5243	{
<>	144:ef7eb2e8f9f7	5244	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	5245	while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	5246	{
<>	144:ef7eb2e8f9f7	5247	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5248	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5249	{
<>	144:ef7eb2e8f9f7	5250	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5251	{
<>	144:ef7eb2e8f9f7	5252	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5253	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5254	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	5255
<>	144:ef7eb2e8f9f7	5256	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5257	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5258
<>	144:ef7eb2e8f9f7	5259	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5260	}
<>	144:ef7eb2e8f9f7	5261	}
<>	144:ef7eb2e8f9f7	5262	}
<>	144:ef7eb2e8f9f7	5263
<>	144:ef7eb2e8f9f7	5264	return HAL_OK;
<>	144:ef7eb2e8f9f7	5265	}
<>	144:ef7eb2e8f9f7	5266
<>	144:ef7eb2e8f9f7	5267	/**
<>	144:ef7eb2e8f9f7	5268	* @brief This function handles I2C Communication Timeout for Master addressing phase.
<>	144:ef7eb2e8f9f7	5269	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5270	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5271	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5272	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5273	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5274	* @retval HAL status
<>	144:ef7eb2e8f9f7	5275	*/
<>	144:ef7eb2e8f9f7	5276	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5277	{
<>	144:ef7eb2e8f9f7	5278	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
<>	144:ef7eb2e8f9f7	5279	{
<>	144:ef7eb2e8f9f7	5280	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5281	{
<>	144:ef7eb2e8f9f7	5282	/* Generate Stop */
<>	144:ef7eb2e8f9f7	5283	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5284
<>	144:ef7eb2e8f9f7	5285	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	5286	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5287
<>	144:ef7eb2e8f9f7	5288	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5289	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5290	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5291
<>	144:ef7eb2e8f9f7	5292	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5293	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5294
<>	144:ef7eb2e8f9f7	5295	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5296	}
<>	144:ef7eb2e8f9f7	5297
<>	144:ef7eb2e8f9f7	5298	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5299	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5300	{
<>	144:ef7eb2e8f9f7	5301	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5302	{
<>	144:ef7eb2e8f9f7	5303	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5304	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5305
<>	144:ef7eb2e8f9f7	5306	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5307	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5308
<>	144:ef7eb2e8f9f7	5309	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5310	}
<>	144:ef7eb2e8f9f7	5311	}
<>	144:ef7eb2e8f9f7	5312	}
<>	144:ef7eb2e8f9f7	5313	return HAL_OK;
<>	144:ef7eb2e8f9f7	5314	}
<>	144:ef7eb2e8f9f7	5315
<>	144:ef7eb2e8f9f7	5316	/**
<>	144:ef7eb2e8f9f7	5317	* @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
<>	144:ef7eb2e8f9f7	5318	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5319	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5320	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5321	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5322	* @retval HAL status
<>	144:ef7eb2e8f9f7	5323	*/
<>	144:ef7eb2e8f9f7	5324	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5325	{
<>	144:ef7eb2e8f9f7	5326	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	5327	{
<>	144:ef7eb2e8f9f7	5328	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5329	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5330	{
<>	144:ef7eb2e8f9f7	5331	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5332	}
<>	144:ef7eb2e8f9f7	5333
<>	144:ef7eb2e8f9f7	5334	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5335	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5336	{
<>	144:ef7eb2e8f9f7	5337	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5338	{
<>	144:ef7eb2e8f9f7	5339	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5340	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5341	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5342
<>	144:ef7eb2e8f9f7	5343	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5344	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5345
<>	144:ef7eb2e8f9f7	5346	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5347	}
<>	144:ef7eb2e8f9f7	5348	}
<>	144:ef7eb2e8f9f7	5349	}
<>	144:ef7eb2e8f9f7	5350	return HAL_OK;
<>	144:ef7eb2e8f9f7	5351	}
<>	144:ef7eb2e8f9f7	5352
<>	144:ef7eb2e8f9f7	5353	/**
<>	144:ef7eb2e8f9f7	5354	* @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
<>	144:ef7eb2e8f9f7	5355	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5356	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5357	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5358	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5359	* @retval HAL status
<>	144:ef7eb2e8f9f7	5360	*/
<>	144:ef7eb2e8f9f7	5361	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5362	{
<>	144:ef7eb2e8f9f7	5363	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
<>	144:ef7eb2e8f9f7	5364	{
<>	144:ef7eb2e8f9f7	5365	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5366	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5367	{
<>	144:ef7eb2e8f9f7	5368	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5369	}
<>	144:ef7eb2e8f9f7	5370
<>	144:ef7eb2e8f9f7	5371	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5372	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5373	{
<>	144:ef7eb2e8f9f7	5374	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5375	{
<>	144:ef7eb2e8f9f7	5376	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5377	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5378	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5379
<>	144:ef7eb2e8f9f7	5380	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5381	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5382
<>	144:ef7eb2e8f9f7	5383	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5384	}
<>	144:ef7eb2e8f9f7	5385	}
<>	144:ef7eb2e8f9f7	5386	}
<>	144:ef7eb2e8f9f7	5387	return HAL_OK;
<>	144:ef7eb2e8f9f7	5388	}
<>	144:ef7eb2e8f9f7	5389
<>	144:ef7eb2e8f9f7	5390	/**
<>	144:ef7eb2e8f9f7	5391	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	5392	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5393	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5394	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5395	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5396	* @retval HAL status
<>	144:ef7eb2e8f9f7	5397	*/
<>	144:ef7eb2e8f9f7	5398	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5399	{
<>	144:ef7eb2e8f9f7	5400	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	5401	{
<>	144:ef7eb2e8f9f7	5402	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5403	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5404	{
<>	144:ef7eb2e8f9f7	5405	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5406	}
<>	144:ef7eb2e8f9f7	5407
<>	144:ef7eb2e8f9f7	5408	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5409	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5410	{
<>	144:ef7eb2e8f9f7	5411	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5412	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5413	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5414
<>	144:ef7eb2e8f9f7	5415	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5416	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5417
<>	144:ef7eb2e8f9f7	5418	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5419	}
<>	144:ef7eb2e8f9f7	5420	}
<>	144:ef7eb2e8f9f7	5421	return HAL_OK;
<>	144:ef7eb2e8f9f7	5422	}
<>	144:ef7eb2e8f9f7	5423
<>	144:ef7eb2e8f9f7	5424	/**
<>	144:ef7eb2e8f9f7	5425	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	5426	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5427	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5428	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	5429	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5430	* @retval HAL status
<>	144:ef7eb2e8f9f7	5431	*/
<>	144:ef7eb2e8f9f7	5432	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5433	{
<>	144:ef7eb2e8f9f7	5434
<>	144:ef7eb2e8f9f7	5435	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	5436	{
<>	144:ef7eb2e8f9f7	5437	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	5438	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	5439	{
<>	144:ef7eb2e8f9f7	5440	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	5441	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	5442
<>	144:ef7eb2e8f9f7	5443	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	5444	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5445	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5446
<>	144:ef7eb2e8f9f7	5447	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5448	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5449
<>	144:ef7eb2e8f9f7	5450	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5451	}
<>	144:ef7eb2e8f9f7	5452
<>	144:ef7eb2e8f9f7	5453	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5454	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5455	{
<>	144:ef7eb2e8f9f7	5456	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5457	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5458
<>	144:ef7eb2e8f9f7	5459	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5460	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5461
<>	144:ef7eb2e8f9f7	5462	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5463	}
<>	144:ef7eb2e8f9f7	5464	}
<>	144:ef7eb2e8f9f7	5465	return HAL_OK;
<>	144:ef7eb2e8f9f7	5466	}
<>	144:ef7eb2e8f9f7	5467
<>	144:ef7eb2e8f9f7	5468	/**
<>	144:ef7eb2e8f9f7	5469	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	5470	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5471	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5472	* @retval HAL status
<>	144:ef7eb2e8f9f7	5473	*/
<>	144:ef7eb2e8f9f7	5474	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	5475	{
<>	144:ef7eb2e8f9f7	5476	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5477	{
<>	144:ef7eb2e8f9f7	5478	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	5479	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5480
<>	144:ef7eb2e8f9f7	5481	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	144:ef7eb2e8f9f7	5482	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5483	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5484
<>	144:ef7eb2e8f9f7	5485	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5486	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5487
<>	144:ef7eb2e8f9f7	5488	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5489	}
<>	144:ef7eb2e8f9f7	5490	return HAL_OK;
<>	144:ef7eb2e8f9f7	5491	}
<>	144:ef7eb2e8f9f7	5492	/**
<>	144:ef7eb2e8f9f7	5493	* @}
<>	144:ef7eb2e8f9f7	5494	*/
<>	144:ef7eb2e8f9f7	5495
<>	144:ef7eb2e8f9f7	5496	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5497
<>	144:ef7eb2e8f9f7	5498	/**
<>	144:ef7eb2e8f9f7	5499	* @}
<>	144:ef7eb2e8f9f7	5500	*/
<>	144:ef7eb2e8f9f7	5501
<>	144:ef7eb2e8f9f7	5502	/**
<>	144:ef7eb2e8f9f7	5503	* @}
<>	144:ef7eb2e8f9f7	5504	*/
<>	144:ef7eb2e8f9f7	5505
<>	144:ef7eb2e8f9f7	5506	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
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targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_i2c.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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