Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_can.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_can.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Controller Area Network (CAN) peripheral:
<> 144:ef7eb2e8f9f7 9 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 10 * + IO operation functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable the CAN controller interface clock using
<> 144:ef7eb2e8f9f7 20 __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
<> 144:ef7eb2e8f9f7 21 -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) CAN pins configuration
<> 144:ef7eb2e8f9f7 24 (++) Enable the clock for the CAN GPIOs using the following function:
<> 144:ef7eb2e8f9f7 25 __GPIOx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 26 (++) Connect and configure the involved CAN pins to AF9 using the
<> 144:ef7eb2e8f9f7 27 following function HAL_GPIO_Init()
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Initialize and configure the CAN using CAN_Init() function.
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (#) Receive a CAN frame using HAL_CAN_Receive() function.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 36 =================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 (+) Start the CAN peripheral transmission and wait the end of this operation
<> 144:ef7eb2e8f9f7 39 using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 40 according to his end application
<> 144:ef7eb2e8f9f7 41 (+) Start the CAN peripheral reception and wait the end of this operation
<> 144:ef7eb2e8f9f7 42 using HAL_CAN_Receive(), at this stage user can specify the value of timeout
<> 144:ef7eb2e8f9f7 43 according to his end application
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 46 ===================================
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
<> 144:ef7eb2e8f9f7 49 (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
<> 144:ef7eb2e8f9f7 50 (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
<> 144:ef7eb2e8f9f7 51 (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 52 add his own code by customization of function pointer HAL_CAN_TxCpltCallback
<> 144:ef7eb2e8f9f7 53 (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 54 add his own code by customization of function pointer HAL_CAN_ErrorCallback
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** CAN HAL driver macros list ***
<> 144:ef7eb2e8f9f7 57 =============================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 Below the list of most used macros in CAN HAL driver.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 62 (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
<> 144:ef7eb2e8f9f7 63 (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
<> 144:ef7eb2e8f9f7 64 (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
<> 144:ef7eb2e8f9f7 65 (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 [..]
<> 144:ef7eb2e8f9f7 68 (@) You can refer to the CAN HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 @endverbatim
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 * @attention
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 78 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 83 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 85 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 86 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 ******************************************************************************
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup CAN CAN
<> 144:ef7eb2e8f9f7 110 * @brief CAN driver modules
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #ifdef HAL_CAN_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /** @addtogroup CAN_Private_Constants
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121 #define CAN_TIMEOUT_VALUE 10U
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 126 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 128 /** @addtogroup CAN_Private_Functions
<> 144:ef7eb2e8f9f7 129 * @{
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 132 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /** @defgroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 143 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 @verbatim
<> 144:ef7eb2e8f9f7 146 ==============================================================================
<> 144:ef7eb2e8f9f7 147 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 148 ==============================================================================
<> 144:ef7eb2e8f9f7 149 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 150 (+) Initialize and configure the CAN.
<> 144:ef7eb2e8f9f7 151 (+) De-initialize the CAN.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 @endverbatim
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @brief Initializes the CAN peripheral according to the specified
<> 144:ef7eb2e8f9f7 159 * parameters in the CAN_InitStruct.
<> 144:ef7eb2e8f9f7 160 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 161 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 162 * @retval HAL status
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 uint32_t InitStatus = 3U;
<> 144:ef7eb2e8f9f7 167 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 170 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Check the parameters */
<> 144:ef7eb2e8f9f7 176 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
<> 144:ef7eb2e8f9f7 179 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
<> 144:ef7eb2e8f9f7 183 assert_param(IS_CAN_MODE(hcan->Init.Mode));
<> 144:ef7eb2e8f9f7 184 assert_param(IS_CAN_SJW(hcan->Init.SJW));
<> 144:ef7eb2e8f9f7 185 assert_param(IS_CAN_BS1(hcan->Init.BS1));
<> 144:ef7eb2e8f9f7 186 assert_param(IS_CAN_BS2(hcan->Init.BS2));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 if(hcan->State == HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 193 hcan->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 194 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 195 HAL_CAN_MspInit(hcan);
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Initialize the CAN state*/
<> 144:ef7eb2e8f9f7 199 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Exit from sleep mode */
<> 144:ef7eb2e8f9f7 202 hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Request initialisation */
<> 144:ef7eb2e8f9f7 205 hcan->Instance->MCR |= CAN_MCR_INRQ ;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Get tick */
<> 144:ef7eb2e8f9f7 208 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 211 while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 216 /* Process unlocked */
<> 144:ef7eb2e8f9f7 217 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 218 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /* Check acknowledge */
<> 144:ef7eb2e8f9f7 223 if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227 else
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Set the time triggered communication mode */
<> 144:ef7eb2e8f9f7 230 if (hcan->Init.TTCM == ENABLE)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 hcan->Instance->MCR |= CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234 else
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Set the automatic bus-off management */
<> 144:ef7eb2e8f9f7 240 if (hcan->Init.ABOM == ENABLE)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 hcan->Instance->MCR |= CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244 else
<> 144:ef7eb2e8f9f7 245 {
<> 144:ef7eb2e8f9f7 246 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Set the automatic wake-up mode */
<> 144:ef7eb2e8f9f7 250 if (hcan->Init.AWUM == ENABLE)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 hcan->Instance->MCR |= CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254 else
<> 144:ef7eb2e8f9f7 255 {
<> 144:ef7eb2e8f9f7 256 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
<> 144:ef7eb2e8f9f7 257 }
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Set the no automatic retransmission */
<> 144:ef7eb2e8f9f7 260 if (hcan->Init.NART == ENABLE)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 hcan->Instance->MCR |= CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264 else
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Set the receive FIFO locked mode */
<> 144:ef7eb2e8f9f7 270 if (hcan->Init.RFLM == ENABLE)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 hcan->Instance->MCR |= CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 else
<> 144:ef7eb2e8f9f7 275 {
<> 144:ef7eb2e8f9f7 276 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Set the transmit FIFO priority */
<> 144:ef7eb2e8f9f7 280 if (hcan->Init.TXFP == ENABLE)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 hcan->Instance->MCR |= CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 else
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Set the bit timing register */
<> 144:ef7eb2e8f9f7 290 hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
<> 144:ef7eb2e8f9f7 291 ((uint32_t)hcan->Init.SJW) | \
<> 144:ef7eb2e8f9f7 292 ((uint32_t)hcan->Init.BS1) | \
<> 144:ef7eb2e8f9f7 293 ((uint32_t)hcan->Init.BS2) | \
<> 144:ef7eb2e8f9f7 294 ((uint32_t)hcan->Init.Prescaler - 1U);
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Request leave initialisation */
<> 144:ef7eb2e8f9f7 297 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Get tick */
<> 144:ef7eb2e8f9f7 300 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 303 while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 308 /* Process unlocked */
<> 144:ef7eb2e8f9f7 309 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 310 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Check acknowledged */
<> 144:ef7eb2e8f9f7 315 if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 InitStatus = CAN_INITSTATUS_FAILED;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319 else
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 InitStatus = CAN_INITSTATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 if(InitStatus == CAN_INITSTATUS_SUCCESS)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 328 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 331 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Return function status */
<> 144:ef7eb2e8f9f7 334 return HAL_OK;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 else
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Initialize the CAN state */
<> 144:ef7eb2e8f9f7 339 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* Return function status */
<> 144:ef7eb2e8f9f7 342 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief Configures the CAN reception filter according to the specified
<> 144:ef7eb2e8f9f7 348 * parameters in the CAN_FilterInitStruct.
<> 144:ef7eb2e8f9f7 349 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 351 * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
<> 144:ef7eb2e8f9f7 352 * contains the filter configuration information.
<> 144:ef7eb2e8f9f7 353 * @retval None
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
<> 144:ef7eb2e8f9f7 356 {
<> 144:ef7eb2e8f9f7 357 uint32_t filternbrbitpos = 0U;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Check the parameters */
<> 144:ef7eb2e8f9f7 360 assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
<> 144:ef7eb2e8f9f7 361 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
<> 144:ef7eb2e8f9f7 362 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
<> 144:ef7eb2e8f9f7 363 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
<> 144:ef7eb2e8f9f7 364 assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
<> 144:ef7eb2e8f9f7 365 assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 filternbrbitpos = ((uint32_t)1U) << sFilterConfig->FilterNumber;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 370 CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Select the start slave bank */
<> 144:ef7eb2e8f9f7 373 CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
<> 144:ef7eb2e8f9f7 374 CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Filter Deactivation */
<> 144:ef7eb2e8f9f7 377 CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Filter Scale */
<> 144:ef7eb2e8f9f7 380 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* 16-bit scale for the filter */
<> 144:ef7eb2e8f9f7 383 CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* First 16-bit identifier and First 16-bit mask */
<> 144:ef7eb2e8f9f7 386 /* Or First 16-bit identifier and Second 16-bit identifier */
<> 144:ef7eb2e8f9f7 387 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 388 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
<> 144:ef7eb2e8f9f7 389 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Second 16-bit identifier and Second 16-bit mask */
<> 144:ef7eb2e8f9f7 392 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
<> 144:ef7eb2e8f9f7 393 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 394 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 395 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 /* 32-bit scale for the filter */
<> 144:ef7eb2e8f9f7 401 CAN1->FS1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 402 /* 32-bit identifier or First 32-bit identifier */
<> 144:ef7eb2e8f9f7 403 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
<> 144:ef7eb2e8f9f7 404 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 405 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
<> 144:ef7eb2e8f9f7 406 /* 32-bit mask or Second 32-bit identifier */
<> 144:ef7eb2e8f9f7 407 CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
<> 144:ef7eb2e8f9f7 408 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
<> 144:ef7eb2e8f9f7 409 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Filter Mode */
<> 144:ef7eb2e8f9f7 413 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 /*Id/Mask mode for the filter*/
<> 144:ef7eb2e8f9f7 416 CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /*Identifier list mode for the filter*/
<> 144:ef7eb2e8f9f7 421 CAN1->FM1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Filter FIFO assignment */
<> 144:ef7eb2e8f9f7 425 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 /* FIFO 0 assignation for the filter */
<> 144:ef7eb2e8f9f7 428 CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* FIFO 1 assignation for the filter */
<> 144:ef7eb2e8f9f7 434 CAN1->FFA1R |= (uint32_t)filternbrbitpos;
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* Filter activation */
<> 144:ef7eb2e8f9f7 438 if (sFilterConfig->FilterActivation == ENABLE)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 CAN1->FA1R |= filternbrbitpos;
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Leave the initialisation mode for the filter */
<> 144:ef7eb2e8f9f7 444 CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Return function status */
<> 144:ef7eb2e8f9f7 447 return HAL_OK;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @brief Deinitializes the CANx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 452 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 453 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 454 * @retval HAL status
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 /* Check CAN handle */
<> 144:ef7eb2e8f9f7 459 if(hcan == NULL)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Check the parameters */
<> 144:ef7eb2e8f9f7 465 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Change CAN state */
<> 144:ef7eb2e8f9f7 468 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 471 HAL_CAN_MspDeInit(hcan);
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Change CAN state */
<> 144:ef7eb2e8f9f7 474 hcan->State = HAL_CAN_STATE_RESET;
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Release Lock */
<> 144:ef7eb2e8f9f7 477 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Return function status */
<> 144:ef7eb2e8f9f7 480 return HAL_OK;
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /**
<> 144:ef7eb2e8f9f7 484 * @brief Initializes the CAN MSP.
<> 144:ef7eb2e8f9f7 485 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 486 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 487 * @retval None
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 492 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 493 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 494 the HAL_CAN_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief DeInitializes the CAN MSP.
<> 144:ef7eb2e8f9f7 500 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 501 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 507 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 508 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 509 the HAL_CAN_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @}
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /** @defgroup CAN_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 518 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 519 *
<> 144:ef7eb2e8f9f7 520 @verbatim
<> 144:ef7eb2e8f9f7 521 ==============================================================================
<> 144:ef7eb2e8f9f7 522 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 523 ==============================================================================
<> 144:ef7eb2e8f9f7 524 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 525 (+) Transmit a CAN frame message.
<> 144:ef7eb2e8f9f7 526 (+) Receive a CAN frame message.
<> 144:ef7eb2e8f9f7 527 (+) Enter CAN peripheral in sleep mode.
<> 144:ef7eb2e8f9f7 528 (+) Wake up the CAN peripheral from sleep mode.
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 @endverbatim
<> 144:ef7eb2e8f9f7 531 * @{
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 536 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 537 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 538 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 539 * @retval HAL status
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 uint32_t transmitmailbox = 5U;
<> 144:ef7eb2e8f9f7 544 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Check the parameters */
<> 144:ef7eb2e8f9f7 547 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 548 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 549 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 552 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 553 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* Process locked */
<> 144:ef7eb2e8f9f7 556 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Change CAN state */
<> 144:ef7eb2e8f9f7 561 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 else
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Change CAN state */
<> 144:ef7eb2e8f9f7 566 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 570 if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 transmitmailbox = 0U;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 transmitmailbox = 1U;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 else
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 transmitmailbox = 2U;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Set up the Id */
<> 144:ef7eb2e8f9f7 584 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 585 if (hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 588 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 589 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591 else
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 594 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 595 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 596 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 600 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 601 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 602 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Set up the data field */
<> 144:ef7eb2e8f9f7 605 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 606 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 607 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 608 ((uint32_t)hcan->pTxMsg->Data[0U]));
<> 144:ef7eb2e8f9f7 609 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 610 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 611 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 612 ((uint32_t)hcan->pTxMsg->Data[4U]));
<> 144:ef7eb2e8f9f7 613 /* Request transmission */
<> 144:ef7eb2e8f9f7 614 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* Get tick */
<> 144:ef7eb2e8f9f7 617 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 620 while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 623 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 628 /* Process unlocked */
<> 144:ef7eb2e8f9f7 629 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 630 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Change CAN state */
<> 144:ef7eb2e8f9f7 637 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 else
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 /* Change CAN state */
<> 144:ef7eb2e8f9f7 642 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Process unlocked */
<> 144:ef7eb2e8f9f7 646 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Return function status */
<> 144:ef7eb2e8f9f7 649 return HAL_OK;
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 else
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 /* Change CAN state */
<> 144:ef7eb2e8f9f7 654 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Return function status */
<> 144:ef7eb2e8f9f7 657 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /**
<> 144:ef7eb2e8f9f7 662 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 663 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 664 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 665 * @retval HAL status
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 uint32_t transmitmailbox = 5U;
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Check the parameters */
<> 144:ef7eb2e8f9f7 672 assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
<> 144:ef7eb2e8f9f7 673 assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
<> 144:ef7eb2e8f9f7 674 assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
<> 144:ef7eb2e8f9f7 677 ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
<> 144:ef7eb2e8f9f7 678 ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 /* Process Locked */
<> 144:ef7eb2e8f9f7 681 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Select one empty transmit mailbox */
<> 144:ef7eb2e8f9f7 684 if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 transmitmailbox = 0U;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 transmitmailbox = 1U;
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 else
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 transmitmailbox = 2U;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Set up the Id */
<> 144:ef7eb2e8f9f7 698 hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 699 if(hcan->pTxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
<> 144:ef7eb2e8f9f7 702 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
<> 144:ef7eb2e8f9f7 703 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 else
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
<> 144:ef7eb2e8f9f7 708 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
<> 144:ef7eb2e8f9f7 709 hcan->pTxMsg->IDE | \
<> 144:ef7eb2e8f9f7 710 hcan->pTxMsg->RTR);
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Set up the DLC */
<> 144:ef7eb2e8f9f7 714 hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
<> 144:ef7eb2e8f9f7 715 hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
<> 144:ef7eb2e8f9f7 716 hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Set up the data field */
<> 144:ef7eb2e8f9f7 719 hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
<> 144:ef7eb2e8f9f7 720 ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
<> 144:ef7eb2e8f9f7 721 ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
<> 144:ef7eb2e8f9f7 722 ((uint32_t)hcan->pTxMsg->Data[0U]));
<> 144:ef7eb2e8f9f7 723 hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
<> 144:ef7eb2e8f9f7 724 ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
<> 144:ef7eb2e8f9f7 725 ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
<> 144:ef7eb2e8f9f7 726 ((uint32_t)hcan->pTxMsg->Data[4U]));
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 /* Change CAN state */
<> 144:ef7eb2e8f9f7 731 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 else
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 /* Change CAN state */
<> 144:ef7eb2e8f9f7 736 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 740 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 743 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 746 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 749 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 752 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 755 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 758 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 /* Enable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 761 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /* Request transmission */
<> 144:ef7eb2e8f9f7 764 hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766 else
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 /* Change CAN state */
<> 144:ef7eb2e8f9f7 769 hcan->State = HAL_CAN_STATE_ERROR;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Return function status */
<> 144:ef7eb2e8f9f7 772 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 return HAL_OK;
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /**
<> 144:ef7eb2e8f9f7 779 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 780 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 781 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 782 * @param FIFONumber: FIFO Number value
<> 144:ef7eb2e8f9f7 783 * @param Timeout: Specify Timeout value
<> 144:ef7eb2e8f9f7 784 * @retval HAL status
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Check the parameters */
<> 144:ef7eb2e8f9f7 791 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /* Process locked */
<> 144:ef7eb2e8f9f7 794 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 /* Change CAN state */
<> 144:ef7eb2e8f9f7 799 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801 else
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 /* Change CAN state */
<> 144:ef7eb2e8f9f7 804 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Get tick */
<> 144:ef7eb2e8f9f7 808 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Check pending message */
<> 144:ef7eb2e8f9f7 811 while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 814 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 819 /* Process unlocked */
<> 144:ef7eb2e8f9f7 820 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 821 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Get the Id */
<> 144:ef7eb2e8f9f7 827 hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 828 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 else
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 838 /* Get the DLC */
<> 144:ef7eb2e8f9f7 839 hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 840 /* Get the FMI */
<> 144:ef7eb2e8f9f7 841 hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
<> 144:ef7eb2e8f9f7 842 /* Get the data field */
<> 144:ef7eb2e8f9f7 843 hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 844 hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
<> 144:ef7eb2e8f9f7 845 hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
<> 144:ef7eb2e8f9f7 846 hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
<> 144:ef7eb2e8f9f7 847 hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 848 hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
<> 144:ef7eb2e8f9f7 849 hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
<> 144:ef7eb2e8f9f7 850 hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 853 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 854 {
<> 144:ef7eb2e8f9f7 855 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 856 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 859 {
<> 144:ef7eb2e8f9f7 860 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 861 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 /* Change CAN state */
<> 144:ef7eb2e8f9f7 867 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Process unlocked */
<> 144:ef7eb2e8f9f7 870 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872 else
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 /* Change CAN state */
<> 144:ef7eb2e8f9f7 875 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Process unlocked */
<> 144:ef7eb2e8f9f7 878 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 879 }
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Return function status */
<> 144:ef7eb2e8f9f7 882 return HAL_OK;
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /**
<> 144:ef7eb2e8f9f7 886 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 887 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 888 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 889 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 890 * @retval HAL status
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /* Check the parameters */
<> 144:ef7eb2e8f9f7 897 assert_param(IS_CAN_FIFO(FIFONumber));
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 tmp = hcan->State;
<> 144:ef7eb2e8f9f7 900 if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 /* Process locked */
<> 144:ef7eb2e8f9f7 903 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 906 {
<> 144:ef7eb2e8f9f7 907 /* Change CAN state */
<> 144:ef7eb2e8f9f7 908 hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910 else
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 /* Change CAN state */
<> 144:ef7eb2e8f9f7 913 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Set CAN error code to none */
<> 144:ef7eb2e8f9f7 917 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Enable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 920 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Enable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 923 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Enable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 926 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 /* Enable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 929 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /* Enable Error Interrupt */
<> 144:ef7eb2e8f9f7 932 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 /* Process unlocked */
<> 144:ef7eb2e8f9f7 935 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 if(FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Enable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 940 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 else
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Enable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 945 __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949 else
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Return function status */
<> 144:ef7eb2e8f9f7 955 return HAL_OK;
<> 144:ef7eb2e8f9f7 956 }
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /**
<> 144:ef7eb2e8f9f7 959 * @brief Enters the Sleep (low power) mode.
<> 144:ef7eb2e8f9f7 960 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 961 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 962 * @retval HAL status.
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Process locked */
<> 144:ef7eb2e8f9f7 969 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Change CAN state */
<> 144:ef7eb2e8f9f7 972 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Request Sleep mode */
<> 144:ef7eb2e8f9f7 975 hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 978 if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 /* Process unlocked */
<> 144:ef7eb2e8f9f7 981 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /* Return function status */
<> 144:ef7eb2e8f9f7 984 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /* Get tick */
<> 144:ef7eb2e8f9f7 988 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /* Wait the acknowledge */
<> 144:ef7eb2e8f9f7 991 while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 hcan->State = HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 996 /* Process unlocked */
<> 144:ef7eb2e8f9f7 997 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 998 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1003 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1006 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Return function status */
<> 144:ef7eb2e8f9f7 1009 return HAL_OK;
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
<> 144:ef7eb2e8f9f7 1014 * is in the normal mode.
<> 144:ef7eb2e8f9f7 1015 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1016 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1017 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1018 */
<> 144:ef7eb2e8f9f7 1019 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Process locked */
<> 144:ef7eb2e8f9f7 1024 __HAL_LOCK(hcan);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1027 hcan->State = HAL_CAN_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Wake up request */
<> 144:ef7eb2e8f9f7 1030 hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /* Get tick */
<> 144:ef7eb2e8f9f7 1033 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /* Sleep mode status */
<> 144:ef7eb2e8f9f7 1036 while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 hcan->State= HAL_CAN_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1041 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1042 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1043 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1049 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Return function status */
<> 144:ef7eb2e8f9f7 1052 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1056 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1059 __HAL_UNLOCK(hcan);
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Return function status */
<> 144:ef7eb2e8f9f7 1062 return HAL_OK;
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 /**
<> 144:ef7eb2e8f9f7 1066 * @brief Handles CAN interrupt request
<> 144:ef7eb2e8f9f7 1067 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1068 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1069 * @retval None
<> 144:ef7eb2e8f9f7 1070 */
<> 144:ef7eb2e8f9f7 1071 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Check End of transmission flag */
<> 144:ef7eb2e8f9f7 1076 if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
<> 144:ef7eb2e8f9f7 1079 tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
<> 144:ef7eb2e8f9f7 1080 tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
<> 144:ef7eb2e8f9f7 1081 if(tmp1 || tmp2 || tmp3)
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 /* Call transmit function */
<> 144:ef7eb2e8f9f7 1084 CAN_Transmit_IT(hcan);
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1089 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1090 /* Check End of reception flag for FIFO0 */
<> 144:ef7eb2e8f9f7 1091 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 /* Call receive function */
<> 144:ef7eb2e8f9f7 1094 CAN_Receive_IT(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1095 }
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1098 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1099 /* Check End of reception flag for FIFO1 */
<> 144:ef7eb2e8f9f7 1100 if((tmp1 != 0U) && tmp2)
<> 144:ef7eb2e8f9f7 1101 {
<> 144:ef7eb2e8f9f7 1102 /* Call receive function */
<> 144:ef7eb2e8f9f7 1103 CAN_Receive_IT(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
<> 144:ef7eb2e8f9f7 1107 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1108 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1109 /* Check Error Warning Flag */
<> 144:ef7eb2e8f9f7 1110 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1111 {
<> 144:ef7eb2e8f9f7 1112 /* Set CAN error code to EWG error */
<> 144:ef7eb2e8f9f7 1113 hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
<> 144:ef7eb2e8f9f7 1114 }
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
<> 144:ef7eb2e8f9f7 1117 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1118 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1119 /* Check Error Passive Flag */
<> 144:ef7eb2e8f9f7 1120 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 /* Set CAN error code to EPV error */
<> 144:ef7eb2e8f9f7 1123 hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
<> 144:ef7eb2e8f9f7 1127 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1128 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1129 /* Check Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1130 if(tmp1 && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1131 {
<> 144:ef7eb2e8f9f7 1132 /* Set CAN error code to BOF error */
<> 144:ef7eb2e8f9f7 1133 hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1137 tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1138 tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1139 /* Check Last error code Flag */
<> 144:ef7eb2e8f9f7 1140 if((!tmp1) && tmp2 && tmp3)
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
<> 144:ef7eb2e8f9f7 1143 switch(tmp1)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 case(CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1146 /* Set CAN error code to STF error */
<> 144:ef7eb2e8f9f7 1147 hcan->ErrorCode |= HAL_CAN_ERROR_STF;
<> 144:ef7eb2e8f9f7 1148 break;
<> 144:ef7eb2e8f9f7 1149 case(CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1150 /* Set CAN error code to FOR error */
<> 144:ef7eb2e8f9f7 1151 hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
<> 144:ef7eb2e8f9f7 1152 break;
<> 144:ef7eb2e8f9f7 1153 case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1154 /* Set CAN error code to ACK error */
<> 144:ef7eb2e8f9f7 1155 hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
<> 144:ef7eb2e8f9f7 1156 break;
<> 144:ef7eb2e8f9f7 1157 case(CAN_ESR_LEC_2):
<> 144:ef7eb2e8f9f7 1158 /* Set CAN error code to BR error */
<> 144:ef7eb2e8f9f7 1159 hcan->ErrorCode |= HAL_CAN_ERROR_BR;
<> 144:ef7eb2e8f9f7 1160 break;
<> 144:ef7eb2e8f9f7 1161 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
<> 144:ef7eb2e8f9f7 1162 /* Set CAN error code to BD error */
<> 144:ef7eb2e8f9f7 1163 hcan->ErrorCode |= HAL_CAN_ERROR_BD;
<> 144:ef7eb2e8f9f7 1164 break;
<> 144:ef7eb2e8f9f7 1165 case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
<> 144:ef7eb2e8f9f7 1166 /* Set CAN error code to CRC error */
<> 144:ef7eb2e8f9f7 1167 hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
<> 144:ef7eb2e8f9f7 1168 break;
<> 144:ef7eb2e8f9f7 1169 default:
<> 144:ef7eb2e8f9f7 1170 break;
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Clear Last error code Flag */
<> 144:ef7eb2e8f9f7 1174 hcan->Instance->ESR &= ~(CAN_ESR_LEC);
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1178 if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Clear ERRI Flag */
<> 144:ef7eb2e8f9f7 1181 hcan->Instance->MSR = CAN_MSR_ERRI;
<> 144:ef7eb2e8f9f7 1182 /* Set the CAN state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1183 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1184 /* Call Error callback function */
<> 144:ef7eb2e8f9f7 1185 HAL_CAN_ErrorCallback(hcan);
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1191 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1192 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1193 * @retval None
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1198 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1199 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1200 the HAL_CAN_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1201 */
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @brief Transmission complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 1206 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1207 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1208 * @retval None
<> 144:ef7eb2e8f9f7 1209 */
<> 144:ef7eb2e8f9f7 1210 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1211 {
<> 144:ef7eb2e8f9f7 1212 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1213 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1214 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1215 the HAL_CAN_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1216 */
<> 144:ef7eb2e8f9f7 1217 }
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @brief Error CAN callback.
<> 144:ef7eb2e8f9f7 1221 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1222 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1223 * @retval None
<> 144:ef7eb2e8f9f7 1224 */
<> 144:ef7eb2e8f9f7 1225 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1228 UNUSED(hcan);
<> 144:ef7eb2e8f9f7 1229 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1230 the HAL_CAN_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1231 */
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /**
<> 144:ef7eb2e8f9f7 1235 * @}
<> 144:ef7eb2e8f9f7 1236 */
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1239 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 1240 *
<> 144:ef7eb2e8f9f7 1241 @verbatim
<> 144:ef7eb2e8f9f7 1242 ==============================================================================
<> 144:ef7eb2e8f9f7 1243 ##### Peripheral State and Error functions #####
<> 144:ef7eb2e8f9f7 1244 ==============================================================================
<> 144:ef7eb2e8f9f7 1245 [..]
<> 144:ef7eb2e8f9f7 1246 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1247 (+) Check the CAN state.
<> 144:ef7eb2e8f9f7 1248 (+) Check CAN Errors detected during interrupt process
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 @endverbatim
<> 144:ef7eb2e8f9f7 1251 * @{
<> 144:ef7eb2e8f9f7 1252 */
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /**
<> 144:ef7eb2e8f9f7 1255 * @brief return the CAN state
<> 144:ef7eb2e8f9f7 1256 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1257 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1258 * @retval HAL state
<> 144:ef7eb2e8f9f7 1259 */
<> 144:ef7eb2e8f9f7 1260 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 /* Return CAN state */
<> 144:ef7eb2e8f9f7 1263 return hcan->State;
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @brief Return the CAN error code
<> 144:ef7eb2e8f9f7 1268 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1269 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1270 * @retval CAN Error Code
<> 144:ef7eb2e8f9f7 1271 */
<> 144:ef7eb2e8f9f7 1272 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
<> 144:ef7eb2e8f9f7 1273 {
<> 144:ef7eb2e8f9f7 1274 return hcan->ErrorCode;
<> 144:ef7eb2e8f9f7 1275 }
<> 144:ef7eb2e8f9f7 1276
<> 144:ef7eb2e8f9f7 1277 /**
<> 144:ef7eb2e8f9f7 1278 * @}
<> 144:ef7eb2e8f9f7 1279 */
<> 144:ef7eb2e8f9f7 1280 /**
<> 144:ef7eb2e8f9f7 1281 * @brief Initiates and transmits a CAN frame message.
<> 144:ef7eb2e8f9f7 1282 * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1283 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1284 * @retval HAL status
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
<> 144:ef7eb2e8f9f7 1287 {
<> 144:ef7eb2e8f9f7 1288 /* Disable Transmit mailbox empty Interrupt */
<> 144:ef7eb2e8f9f7 1289 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 if(hcan->State == HAL_CAN_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1292 {
<> 144:ef7eb2e8f9f7 1293 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1294 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1297 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1300 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1303 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1306 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1307 }
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1312 hcan->State = HAL_CAN_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314 else
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1317 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1318 }
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /* Transmission complete callback */
<> 144:ef7eb2e8f9f7 1321 HAL_CAN_TxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 return HAL_OK;
<> 144:ef7eb2e8f9f7 1324 }
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @brief Receives a correct CAN frame.
<> 144:ef7eb2e8f9f7 1328 * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1329 * the configuration information for the specified CAN.
<> 144:ef7eb2e8f9f7 1330 * @param FIFONumber: Specify the FIFO number
<> 144:ef7eb2e8f9f7 1331 * @retval HAL status
<> 144:ef7eb2e8f9f7 1332 * @retval None
<> 144:ef7eb2e8f9f7 1333 */
<> 144:ef7eb2e8f9f7 1334 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
<> 144:ef7eb2e8f9f7 1335 {
<> 144:ef7eb2e8f9f7 1336 /* Get the Id */
<> 144:ef7eb2e8f9f7 1337 hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1338 if (hcan->pRxMsg->IDE == CAN_ID_STD)
<> 144:ef7eb2e8f9f7 1339 {
<> 144:ef7eb2e8f9f7 1340 hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
<> 144:ef7eb2e8f9f7 1341 }
<> 144:ef7eb2e8f9f7 1342 else
<> 144:ef7eb2e8f9f7 1343 {
<> 144:ef7eb2e8f9f7 1344 hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
<> 144:ef7eb2e8f9f7 1348 /* Get the DLC */
<> 144:ef7eb2e8f9f7 1349 hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
<> 144:ef7eb2e8f9f7 1350 /* Get the FMI */
<> 144:ef7eb2e8f9f7 1351 hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
<> 144:ef7eb2e8f9f7 1352 /* Get the data field */
<> 144:ef7eb2e8f9f7 1353 hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
<> 144:ef7eb2e8f9f7 1354 hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
<> 144:ef7eb2e8f9f7 1355 hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
<> 144:ef7eb2e8f9f7 1356 hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
<> 144:ef7eb2e8f9f7 1357 hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
<> 144:ef7eb2e8f9f7 1358 hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
<> 144:ef7eb2e8f9f7 1359 hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
<> 144:ef7eb2e8f9f7 1360 hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
<> 144:ef7eb2e8f9f7 1361 /* Release the FIFO */
<> 144:ef7eb2e8f9f7 1362 /* Release FIFO0 */
<> 144:ef7eb2e8f9f7 1363 if (FIFONumber == CAN_FIFO0)
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Disable FIFO 0 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1368 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
<> 144:ef7eb2e8f9f7 1369 }
<> 144:ef7eb2e8f9f7 1370 /* Release FIFO1 */
<> 144:ef7eb2e8f9f7 1371 else /* FIFONumber == CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 1372 {
<> 144:ef7eb2e8f9f7 1373 __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
<> 144:ef7eb2e8f9f7 1374
<> 144:ef7eb2e8f9f7 1375 /* Disable FIFO 1 message pending Interrupt */
<> 144:ef7eb2e8f9f7 1376 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 if(hcan->State == HAL_CAN_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1380 {
<> 144:ef7eb2e8f9f7 1381 /* Disable Error warning Interrupt */
<> 144:ef7eb2e8f9f7 1382 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Disable Error passive Interrupt */
<> 144:ef7eb2e8f9f7 1385 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Disable Bus-off Interrupt */
<> 144:ef7eb2e8f9f7 1388 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Disable Last error code Interrupt */
<> 144:ef7eb2e8f9f7 1391 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 /* Disable Error Interrupt */
<> 144:ef7eb2e8f9f7 1394 __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
<> 144:ef7eb2e8f9f7 1395 }
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 /* Disable CAN state */
<> 144:ef7eb2e8f9f7 1400 hcan->State = HAL_CAN_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1401 }
<> 144:ef7eb2e8f9f7 1402 else
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 /* Change CAN state */
<> 144:ef7eb2e8f9f7 1405 hcan->State = HAL_CAN_STATE_READY;
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Receive complete callback */
<> 144:ef7eb2e8f9f7 1409 HAL_CAN_RxCpltCallback(hcan);
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Return function status */
<> 144:ef7eb2e8f9f7 1412 return HAL_OK;
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /**
<> 144:ef7eb2e8f9f7 1416 * @}
<> 144:ef7eb2e8f9f7 1417 */
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 #endif /* HAL_CAN_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1420 /**
<> 144:ef7eb2e8f9f7 1421 * @}
<> 144:ef7eb2e8f9f7 1422 */
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 /**
<> 144:ef7eb2e8f9f7 1425 * @}
<> 144:ef7eb2e8f9f7 1426 */
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/