Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/ioman_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_IOMAN_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_IOMAN_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file ioman_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup ioman IO MUX Manager
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 typedef enum {
<> 144:ef7eb2e8f9f7 50 /** Pin Mapping 'A' */
<> 144:ef7eb2e8f9f7 51 MXC_E_IOMAN_MAPPING_A = 0,
<> 144:ef7eb2e8f9f7 52 /** Pin Mapping 'B' */
<> 144:ef7eb2e8f9f7 53 MXC_E_IOMAN_MAPPING_B,
<> 144:ef7eb2e8f9f7 54 /** Pin Mapping 'C' */
<> 144:ef7eb2e8f9f7 55 MXC_E_IOMAN_MAPPING_C,
<> 144:ef7eb2e8f9f7 56 /** Pin Mapping 'D' */
<> 144:ef7eb2e8f9f7 57 MXC_E_IOMAN_MAPPING_D,
<> 144:ef7eb2e8f9f7 58 /** Pin Mapping 'E' */
<> 144:ef7eb2e8f9f7 59 MXC_E_IOMAN_MAPPING_E,
<> 144:ef7eb2e8f9f7 60 /** Pin Mapping 'F' */
<> 144:ef7eb2e8f9f7 61 MXC_E_IOMAN_MAPPING_F,
<> 144:ef7eb2e8f9f7 62 /** Pin Mapping 'G' */
<> 144:ef7eb2e8f9f7 63 MXC_E_IOMAN_MAPPING_G,
<> 144:ef7eb2e8f9f7 64 /** Pin Mapping 'H' */
<> 144:ef7eb2e8f9f7 65 MXC_E_IOMAN_MAPPING_H,
<> 144:ef7eb2e8f9f7 66 } ioman_mapping_t;
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* Offset Register Description
<> 144:ef7eb2e8f9f7 69 ====== ========================================== */
<> 144:ef7eb2e8f9f7 70 typedef struct {
<> 144:ef7eb2e8f9f7 71 __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t spi0_req; /* 0x0020 SPI0 I/O Mode Request */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t spi0_ack; /* 0x0024 SPI0 I/O Mode Acknowledge */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t spi1_req; /* 0x0028 SPI1 I/O Mode Request */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t spi1_ack; /* 0x002C SPI1 I/O Mode Acknowledge */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t spi2_req; /* 0x0030 SPI2 I/O Mode Request */
<> 144:ef7eb2e8f9f7 84 __IO uint32_t spi2_ack; /* 0x0034 SPI2 I/O Mode Acknowledge */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t uart0_req; /* 0x0038 UART0 I/O Mode Request */
<> 144:ef7eb2e8f9f7 86 __IO uint32_t uart0_ack; /* 0x003C UART0 I/O Mode Acknowledge */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t uart1_req; /* 0x0040 UART1 I/O Mode Request */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t uart1_ack; /* 0x0044 UART1 I/O Mode Acknowledge */
<> 144:ef7eb2e8f9f7 89 __IO uint32_t i2cm0_req; /* 0x0048 I2C Master 0 I/O Request */
<> 144:ef7eb2e8f9f7 90 __IO uint32_t i2cm0_ack; /* 0x004C I2C Master 0 I/O Acknowledge */
<> 144:ef7eb2e8f9f7 91 __IO uint32_t i2cs0_req; /* 0x0050 I2C Slave 0 I/O Request */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t i2s0_ack; /* 0x0054 I2C Slave 0 I/O Acknowledge */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t lcd_com_req; /* 0x0058 LCD COM Driver I/O Request */
<> 144:ef7eb2e8f9f7 94 __IO uint32_t lcd_com_ack; /* 0x005C LCD COM Driver I/O Acknowledge */
<> 144:ef7eb2e8f9f7 95 __IO uint32_t lcd_seg_req0; /* 0x0060 LCD SEG Driver I/O Request Register 0 */
<> 144:ef7eb2e8f9f7 96 __IO uint32_t lcd_seg_req1; /* 0x0064 LCD SEG Driver I/O Request Register 1 */
<> 144:ef7eb2e8f9f7 97 __IO uint32_t lcd_seg_ack0; /* 0x0068 LCD SEG Driver I/O Acknowledge Register 0 */
<> 144:ef7eb2e8f9f7 98 __IO uint32_t lcd_seg_ack1; /* 0x006C LCD SEG Driver I/O Acknowledge Register 1 */
<> 144:ef7eb2e8f9f7 99 __IO uint32_t crnt_req; /* 0x0070 Current Drive I/O Request Register */
<> 144:ef7eb2e8f9f7 100 __IO uint32_t io_crnt_ack; /* 0x0074 Current Drive I/O Acknowledge Register */
<> 144:ef7eb2e8f9f7 101 __IO uint32_t crnt_mode; /* 0x0078 Current Drive I/O Mode Control */
<> 144:ef7eb2e8f9f7 102 __IO uint32_t ali_connect0; /* 0x007C Analog I/O Connection Control Register 0 */
<> 144:ef7eb2e8f9f7 103 __IO uint32_t ali_connect1; /* 0x0080 Analog I/O Connection Control Register 1 */
<> 144:ef7eb2e8f9f7 104 __IO uint32_t i2cm1_req; /* 0x0084 I2C Master 1 I/O Request */
<> 144:ef7eb2e8f9f7 105 __IO uint32_t i2cm1_ack; /* 0x0088 I2C Master 1 I/O Acknowledge */
<> 144:ef7eb2e8f9f7 106 __IO uint32_t padx_control; /* 0x008C PADX Control */
<> 144:ef7eb2e8f9f7 107 } mxc_ioman_regs_t;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /*
<> 144:ef7eb2e8f9f7 111 Register offsets for module IOMAN.
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 114 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 115 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 116 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 117 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 118 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 119 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 120 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 121 #define MXC_R_IOMAN_OFFS_SPI0_REQ ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 122 #define MXC_R_IOMAN_OFFS_SPI0_ACK ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 123 #define MXC_R_IOMAN_OFFS_SPI1_REQ ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 124 #define MXC_R_IOMAN_OFFS_SPI1_ACK ((uint32_t)0x0000002CUL)
<> 144:ef7eb2e8f9f7 125 #define MXC_R_IOMAN_OFFS_SPI2_REQ ((uint32_t)0x00000030UL)
<> 144:ef7eb2e8f9f7 126 #define MXC_R_IOMAN_OFFS_SPI2_ACK ((uint32_t)0x00000034UL)
<> 144:ef7eb2e8f9f7 127 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000038UL)
<> 144:ef7eb2e8f9f7 128 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x0000003CUL)
<> 144:ef7eb2e8f9f7 129 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 130 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 131 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 132 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x0000004CUL)
<> 144:ef7eb2e8f9f7 133 #define MXC_R_IOMAN_OFFS_I2CS0_REQ ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 134 #define MXC_R_IOMAN_OFFS_I2SC0_ACK ((uint32_t)0x00000054UL)
<> 144:ef7eb2e8f9f7 135 #define MXC_R_IOMAN_OFFS_LCD_COM_REQ ((uint32_t)0x00000058UL)
<> 144:ef7eb2e8f9f7 136 #define MXC_R_IOMAN_OFFS_LCD_COM_ACK ((uint32_t)0x0000005CUL)
<> 144:ef7eb2e8f9f7 137 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0 ((uint32_t)0x00000060UL)
<> 144:ef7eb2e8f9f7 138 #define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1 ((uint32_t)0x00000064UL)
<> 144:ef7eb2e8f9f7 139 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0 ((uint32_t)0x00000068UL)
<> 144:ef7eb2e8f9f7 140 #define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1 ((uint32_t)0x0000006CUL)
<> 144:ef7eb2e8f9f7 141 #define MXC_R_IOMAN_OFFS_IO_CRNT_REQ ((uint32_t)0x00000070UL)
<> 144:ef7eb2e8f9f7 142 #define MXC_R_IOMAN_OFFS_IO_CRNT_ACK ((uint32_t)0x00000074UL)
<> 144:ef7eb2e8f9f7 143 #define MXC_R_IOMAN_OFFS_IO_CRNT_MODE ((uint32_t)0x00000078UL)
<> 144:ef7eb2e8f9f7 144 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x0000007CUL)
<> 144:ef7eb2e8f9f7 145 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000080UL)
<> 144:ef7eb2e8f9f7 146 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000084UL)
<> 144:ef7eb2e8f9f7 147 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x00000088UL)
<> 144:ef7eb2e8f9f7 148 #define MXC_R_IOMAN_OFFS_PADX_CONTROL ((uint32_t)0x0000008CUL)
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /*
<> 144:ef7eb2e8f9f7 152 Field positions and masks for module IOMAN.
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 #define MXC_F_IOMAN_WUD_REQ0_PORT0_POS 0
<> 144:ef7eb2e8f9f7 155 #define MXC_F_IOMAN_WUD_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
<> 144:ef7eb2e8f9f7 156 #define MXC_F_IOMAN_WUD_REQ0_PORT1_POS 8
<> 144:ef7eb2e8f9f7 157 #define MXC_F_IOMAN_WUD_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_IOMAN_WUD_REQ0_PORT2_POS 16
<> 144:ef7eb2e8f9f7 159 #define MXC_F_IOMAN_WUD_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_IOMAN_WUD_REQ0_PORT3_POS 24
<> 144:ef7eb2e8f9f7 161 #define MXC_F_IOMAN_WUD_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #define MXC_F_IOMAN_WUD_REQ1_PORT4_POS 0
<> 144:ef7eb2e8f9f7 164 #define MXC_F_IOMAN_WUD_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_IOMAN_WUD_REQ1_PORT5_POS 8
<> 144:ef7eb2e8f9f7 166 #define MXC_F_IOMAN_WUD_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_IOMAN_WUD_REQ1_PORT6_POS 16
<> 144:ef7eb2e8f9f7 168 #define MXC_F_IOMAN_WUD_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_IOMAN_WUD_REQ1_PORT7_POS 24
<> 144:ef7eb2e8f9f7 170 #define MXC_F_IOMAN_WUD_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 #define MXC_F_IOMAN_WUD_ACK0_PORT0_POS 0
<> 144:ef7eb2e8f9f7 173 #define MXC_F_IOMAN_WUD_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
<> 144:ef7eb2e8f9f7 174 #define MXC_F_IOMAN_WUD_ACK0_PORT1_POS 8
<> 144:ef7eb2e8f9f7 175 #define MXC_F_IOMAN_WUD_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_F_IOMAN_WUD_ACK0_PORT2_POS 16
<> 144:ef7eb2e8f9f7 177 #define MXC_F_IOMAN_WUD_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_F_IOMAN_WUD_ACK0_PORT3_POS 24
<> 144:ef7eb2e8f9f7 179 #define MXC_F_IOMAN_WUD_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #define MXC_F_IOMAN_WUD_ACK1_PORT4_POS 0
<> 144:ef7eb2e8f9f7 182 #define MXC_F_IOMAN_WUD_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
<> 144:ef7eb2e8f9f7 183 #define MXC_F_IOMAN_WUD_ACK1_PORT5_POS 8
<> 144:ef7eb2e8f9f7 184 #define MXC_F_IOMAN_WUD_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
<> 144:ef7eb2e8f9f7 185 #define MXC_F_IOMAN_WUD_ACK1_PORT6_POS 16
<> 144:ef7eb2e8f9f7 186 #define MXC_F_IOMAN_WUD_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
<> 144:ef7eb2e8f9f7 187 #define MXC_F_IOMAN_WUD_ACK1_PORT7_POS 24
<> 144:ef7eb2e8f9f7 188 #define MXC_F_IOMAN_WUD_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 #define MXC_F_IOMAN_ALI_REQ0_PORT0_POS 0
<> 144:ef7eb2e8f9f7 191 #define MXC_F_IOMAN_ALI_REQ0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
<> 144:ef7eb2e8f9f7 192 #define MXC_F_IOMAN_ALI_REQ0_PORT1_POS 8
<> 144:ef7eb2e8f9f7 193 #define MXC_F_IOMAN_ALI_REQ0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
<> 144:ef7eb2e8f9f7 194 #define MXC_F_IOMAN_ALI_REQ0_PORT2_POS 16
<> 144:ef7eb2e8f9f7 195 #define MXC_F_IOMAN_ALI_REQ0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
<> 144:ef7eb2e8f9f7 196 #define MXC_F_IOMAN_ALI_REQ0_PORT3_POS 24
<> 144:ef7eb2e8f9f7 197 #define MXC_F_IOMAN_ALI_REQ0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #define MXC_F_IOMAN_ALI_REQ1_PORT4_POS 0
<> 144:ef7eb2e8f9f7 200 #define MXC_F_IOMAN_ALI_REQ1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
<> 144:ef7eb2e8f9f7 201 #define MXC_F_IOMAN_ALI_REQ1_PORT5_POS 8
<> 144:ef7eb2e8f9f7 202 #define MXC_F_IOMAN_ALI_REQ1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
<> 144:ef7eb2e8f9f7 203 #define MXC_F_IOMAN_ALI_REQ1_PORT6_POS 16
<> 144:ef7eb2e8f9f7 204 #define MXC_F_IOMAN_ALI_REQ1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_F_IOMAN_ALI_REQ1_PORT7_POS 24
<> 144:ef7eb2e8f9f7 206 #define MXC_F_IOMAN_ALI_REQ1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define MXC_F_IOMAN_ALI_ACK0_PORT0_POS 0
<> 144:ef7eb2e8f9f7 209 #define MXC_F_IOMAN_ALI_ACK0_PORT0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
<> 144:ef7eb2e8f9f7 210 #define MXC_F_IOMAN_ALI_ACK0_PORT1_POS 8
<> 144:ef7eb2e8f9f7 211 #define MXC_F_IOMAN_ALI_ACK0_PORT1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_F_IOMAN_ALI_ACK0_PORT2_POS 16
<> 144:ef7eb2e8f9f7 213 #define MXC_F_IOMAN_ALI_ACK0_PORT2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
<> 144:ef7eb2e8f9f7 214 #define MXC_F_IOMAN_ALI_ACK0_PORT3_POS 24
<> 144:ef7eb2e8f9f7 215 #define MXC_F_IOMAN_ALI_ACK0_PORT3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define MXC_F_IOMAN_ALI_ACK1_PORT4_POS 0
<> 144:ef7eb2e8f9f7 218 #define MXC_F_IOMAN_ALI_ACK1_PORT4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
<> 144:ef7eb2e8f9f7 219 #define MXC_F_IOMAN_ALI_ACK1_PORT5_POS 8
<> 144:ef7eb2e8f9f7 220 #define MXC_F_IOMAN_ALI_ACK1_PORT5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
<> 144:ef7eb2e8f9f7 221 #define MXC_F_IOMAN_ALI_ACK1_PORT6_POS 16
<> 144:ef7eb2e8f9f7 222 #define MXC_F_IOMAN_ALI_ACK1_PORT6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
<> 144:ef7eb2e8f9f7 223 #define MXC_F_IOMAN_ALI_ACK1_PORT7_POS 24
<> 144:ef7eb2e8f9f7 224 #define MXC_F_IOMAN_ALI_ACK1_PORT7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #define MXC_F_IOMAN_SPI_MAPPING_POS 0
<> 144:ef7eb2e8f9f7 227 #define MXC_F_IOMAN_SPI_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
<> 144:ef7eb2e8f9f7 228 #define MXC_F_IOMAN_SPI_CORE_IO_POS 4
<> 144:ef7eb2e8f9f7 229 #define MXC_F_IOMAN_SPI_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
<> 144:ef7eb2e8f9f7 230 #define MXC_F_IOMAN_SPI_SS0_IO_POS 8
<> 144:ef7eb2e8f9f7 231 #define MXC_F_IOMAN_SPI_SS0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
<> 144:ef7eb2e8f9f7 232 #define MXC_F_IOMAN_SPI_SS1_IO_POS 9
<> 144:ef7eb2e8f9f7 233 #define MXC_F_IOMAN_SPI_SS1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
<> 144:ef7eb2e8f9f7 234 #define MXC_F_IOMAN_SPI_SS2_IO_POS 10
<> 144:ef7eb2e8f9f7 235 #define MXC_F_IOMAN_SPI_SS2_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
<> 144:ef7eb2e8f9f7 236 #define MXC_F_IOMAN_SPI_SS3_IO_POS 11
<> 144:ef7eb2e8f9f7 237 #define MXC_F_IOMAN_SPI_SS3_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
<> 144:ef7eb2e8f9f7 238 #define MXC_F_IOMAN_SPI_SS4_IO_POS 12
<> 144:ef7eb2e8f9f7 239 #define MXC_F_IOMAN_SPI_SS4_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
<> 144:ef7eb2e8f9f7 240 #define MXC_F_IOMAN_SPI_SR0_IO_POS 16
<> 144:ef7eb2e8f9f7 241 #define MXC_F_IOMAN_SPI_SR0_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
<> 144:ef7eb2e8f9f7 242 #define MXC_F_IOMAN_SPI_SR1_IO_POS 17
<> 144:ef7eb2e8f9f7 243 #define MXC_F_IOMAN_SPI_SR1_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
<> 144:ef7eb2e8f9f7 244 #define MXC_F_IOMAN_SPI_QUAD_IO_POS 20
<> 144:ef7eb2e8f9f7 245 #define MXC_F_IOMAN_SPI_QUAD_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
<> 144:ef7eb2e8f9f7 246 #define MXC_F_IOMAN_SPI_FAST_MODE_POS 24
<> 144:ef7eb2e8f9f7 247 #define MXC_F_IOMAN_SPI_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 #define MXC_F_IOMAN_UART_MAPPING_POS 0
<> 144:ef7eb2e8f9f7 250 #define MXC_F_IOMAN_UART_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
<> 144:ef7eb2e8f9f7 251 #define MXC_F_IOMAN_UART_CORE_IO_POS 4
<> 144:ef7eb2e8f9f7 252 #define MXC_F_IOMAN_UART_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
<> 144:ef7eb2e8f9f7 253 #define MXC_F_IOMAN_UART_CTS_IO_POS 5
<> 144:ef7eb2e8f9f7 254 #define MXC_F_IOMAN_UART_CTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
<> 144:ef7eb2e8f9f7 255 #define MXC_F_IOMAN_UART_RTS_IO_POS 6
<> 144:ef7eb2e8f9f7 256 #define MXC_F_IOMAN_UART_RTS_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #define MXC_F_IOMAN_I2CM_MAPPING_POS 0
<> 144:ef7eb2e8f9f7 259 #define MXC_F_IOMAN_I2CM_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
<> 144:ef7eb2e8f9f7 260 #define MXC_F_IOMAN_I2CM_CORE_IO_POS 4
<> 144:ef7eb2e8f9f7 261 #define MXC_F_IOMAN_I2CM_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 #define MXC_F_IOMAN_I2CS_MAPPING_POS 0
<> 144:ef7eb2e8f9f7 264 #define MXC_F_IOMAN_I2CS_MAPPING ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
<> 144:ef7eb2e8f9f7 265 #define MXC_F_IOMAN_I2CS_CORE_IO_POS 4
<> 144:ef7eb2e8f9f7 266 #define MXC_F_IOMAN_I2CS_CORE_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS 0
<> 144:ef7eb2e8f9f7 269 #define MXC_F_IOMAN_LCD_COM_REQ_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS 0
<> 144:ef7eb2e8f9f7 272 #define MXC_F_IOMAN_LCD_COM_ACK_COM_IO ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS 0
<> 144:ef7eb2e8f9f7 275 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
<> 144:ef7eb2e8f9f7 276 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS 1
<> 144:ef7eb2e8f9f7 277 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
<> 144:ef7eb2e8f9f7 278 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS 2
<> 144:ef7eb2e8f9f7 279 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
<> 144:ef7eb2e8f9f7 280 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS 3
<> 144:ef7eb2e8f9f7 281 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
<> 144:ef7eb2e8f9f7 282 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS 4
<> 144:ef7eb2e8f9f7 283 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
<> 144:ef7eb2e8f9f7 284 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS 5
<> 144:ef7eb2e8f9f7 285 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
<> 144:ef7eb2e8f9f7 286 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS 6
<> 144:ef7eb2e8f9f7 287 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
<> 144:ef7eb2e8f9f7 288 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS 7
<> 144:ef7eb2e8f9f7 289 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
<> 144:ef7eb2e8f9f7 290 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS 8
<> 144:ef7eb2e8f9f7 291 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
<> 144:ef7eb2e8f9f7 292 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS 9
<> 144:ef7eb2e8f9f7 293 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
<> 144:ef7eb2e8f9f7 294 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS 10
<> 144:ef7eb2e8f9f7 295 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
<> 144:ef7eb2e8f9f7 296 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS 11
<> 144:ef7eb2e8f9f7 297 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
<> 144:ef7eb2e8f9f7 298 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS 12
<> 144:ef7eb2e8f9f7 299 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
<> 144:ef7eb2e8f9f7 300 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS 13
<> 144:ef7eb2e8f9f7 301 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
<> 144:ef7eb2e8f9f7 302 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS 14
<> 144:ef7eb2e8f9f7 303 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
<> 144:ef7eb2e8f9f7 304 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS 15
<> 144:ef7eb2e8f9f7 305 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
<> 144:ef7eb2e8f9f7 306 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS 16
<> 144:ef7eb2e8f9f7 307 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
<> 144:ef7eb2e8f9f7 308 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS 17
<> 144:ef7eb2e8f9f7 309 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
<> 144:ef7eb2e8f9f7 310 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS 18
<> 144:ef7eb2e8f9f7 311 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
<> 144:ef7eb2e8f9f7 312 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS 19
<> 144:ef7eb2e8f9f7 313 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
<> 144:ef7eb2e8f9f7 314 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS 20
<> 144:ef7eb2e8f9f7 315 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
<> 144:ef7eb2e8f9f7 316 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS 21
<> 144:ef7eb2e8f9f7 317 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
<> 144:ef7eb2e8f9f7 318 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS 22
<> 144:ef7eb2e8f9f7 319 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
<> 144:ef7eb2e8f9f7 320 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS 23
<> 144:ef7eb2e8f9f7 321 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
<> 144:ef7eb2e8f9f7 322 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS 24
<> 144:ef7eb2e8f9f7 323 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
<> 144:ef7eb2e8f9f7 324 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS 25
<> 144:ef7eb2e8f9f7 325 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
<> 144:ef7eb2e8f9f7 326 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS 26
<> 144:ef7eb2e8f9f7 327 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
<> 144:ef7eb2e8f9f7 328 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS 27
<> 144:ef7eb2e8f9f7 329 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
<> 144:ef7eb2e8f9f7 330 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS 28
<> 144:ef7eb2e8f9f7 331 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
<> 144:ef7eb2e8f9f7 332 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS 29
<> 144:ef7eb2e8f9f7 333 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
<> 144:ef7eb2e8f9f7 334 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS 30
<> 144:ef7eb2e8f9f7 335 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
<> 144:ef7eb2e8f9f7 336 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS 31
<> 144:ef7eb2e8f9f7 337 #define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS 0
<> 144:ef7eb2e8f9f7 340 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
<> 144:ef7eb2e8f9f7 341 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS 1
<> 144:ef7eb2e8f9f7 342 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
<> 144:ef7eb2e8f9f7 343 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS 2
<> 144:ef7eb2e8f9f7 344 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
<> 144:ef7eb2e8f9f7 345 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS 3
<> 144:ef7eb2e8f9f7 346 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
<> 144:ef7eb2e8f9f7 347 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS 4
<> 144:ef7eb2e8f9f7 348 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
<> 144:ef7eb2e8f9f7 349 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS 5
<> 144:ef7eb2e8f9f7 350 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
<> 144:ef7eb2e8f9f7 351 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS 6
<> 144:ef7eb2e8f9f7 352 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
<> 144:ef7eb2e8f9f7 353 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS 7
<> 144:ef7eb2e8f9f7 354 #define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS 0
<> 144:ef7eb2e8f9f7 357 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
<> 144:ef7eb2e8f9f7 358 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS 1
<> 144:ef7eb2e8f9f7 359 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
<> 144:ef7eb2e8f9f7 360 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS 2
<> 144:ef7eb2e8f9f7 361 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
<> 144:ef7eb2e8f9f7 362 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS 3
<> 144:ef7eb2e8f9f7 363 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
<> 144:ef7eb2e8f9f7 364 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS 4
<> 144:ef7eb2e8f9f7 365 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
<> 144:ef7eb2e8f9f7 366 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS 5
<> 144:ef7eb2e8f9f7 367 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
<> 144:ef7eb2e8f9f7 368 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS 6
<> 144:ef7eb2e8f9f7 369 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
<> 144:ef7eb2e8f9f7 370 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS 7
<> 144:ef7eb2e8f9f7 371 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
<> 144:ef7eb2e8f9f7 372 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS 8
<> 144:ef7eb2e8f9f7 373 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
<> 144:ef7eb2e8f9f7 374 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS 9
<> 144:ef7eb2e8f9f7 375 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
<> 144:ef7eb2e8f9f7 376 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS 10
<> 144:ef7eb2e8f9f7 377 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
<> 144:ef7eb2e8f9f7 378 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS 11
<> 144:ef7eb2e8f9f7 379 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
<> 144:ef7eb2e8f9f7 380 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS 12
<> 144:ef7eb2e8f9f7 381 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
<> 144:ef7eb2e8f9f7 382 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS 13
<> 144:ef7eb2e8f9f7 383 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
<> 144:ef7eb2e8f9f7 384 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS 14
<> 144:ef7eb2e8f9f7 385 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
<> 144:ef7eb2e8f9f7 386 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS 15
<> 144:ef7eb2e8f9f7 387 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
<> 144:ef7eb2e8f9f7 388 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS 16
<> 144:ef7eb2e8f9f7 389 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
<> 144:ef7eb2e8f9f7 390 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS 17
<> 144:ef7eb2e8f9f7 391 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
<> 144:ef7eb2e8f9f7 392 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS 18
<> 144:ef7eb2e8f9f7 393 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
<> 144:ef7eb2e8f9f7 394 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS 19
<> 144:ef7eb2e8f9f7 395 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
<> 144:ef7eb2e8f9f7 396 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS 20
<> 144:ef7eb2e8f9f7 397 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
<> 144:ef7eb2e8f9f7 398 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS 21
<> 144:ef7eb2e8f9f7 399 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
<> 144:ef7eb2e8f9f7 400 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS 22
<> 144:ef7eb2e8f9f7 401 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
<> 144:ef7eb2e8f9f7 402 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS 23
<> 144:ef7eb2e8f9f7 403 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
<> 144:ef7eb2e8f9f7 404 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS 24
<> 144:ef7eb2e8f9f7 405 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
<> 144:ef7eb2e8f9f7 406 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS 25
<> 144:ef7eb2e8f9f7 407 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
<> 144:ef7eb2e8f9f7 408 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS 26
<> 144:ef7eb2e8f9f7 409 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
<> 144:ef7eb2e8f9f7 410 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS 27
<> 144:ef7eb2e8f9f7 411 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
<> 144:ef7eb2e8f9f7 412 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS 28
<> 144:ef7eb2e8f9f7 413 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
<> 144:ef7eb2e8f9f7 414 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS 29
<> 144:ef7eb2e8f9f7 415 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
<> 144:ef7eb2e8f9f7 416 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS 30
<> 144:ef7eb2e8f9f7 417 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
<> 144:ef7eb2e8f9f7 418 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS 31
<> 144:ef7eb2e8f9f7 419 #define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS 0
<> 144:ef7eb2e8f9f7 422 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
<> 144:ef7eb2e8f9f7 423 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS 1
<> 144:ef7eb2e8f9f7 424 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
<> 144:ef7eb2e8f9f7 425 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS 2
<> 144:ef7eb2e8f9f7 426 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
<> 144:ef7eb2e8f9f7 427 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS 3
<> 144:ef7eb2e8f9f7 428 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
<> 144:ef7eb2e8f9f7 429 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS 4
<> 144:ef7eb2e8f9f7 430 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
<> 144:ef7eb2e8f9f7 431 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS 5
<> 144:ef7eb2e8f9f7 432 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
<> 144:ef7eb2e8f9f7 433 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS 6
<> 144:ef7eb2e8f9f7 434 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
<> 144:ef7eb2e8f9f7 435 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS 7
<> 144:ef7eb2e8f9f7 436 #define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS 0
<> 144:ef7eb2e8f9f7 439 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
<> 144:ef7eb2e8f9f7 440 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS 1
<> 144:ef7eb2e8f9f7 441 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
<> 144:ef7eb2e8f9f7 442 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS 2
<> 144:ef7eb2e8f9f7 443 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
<> 144:ef7eb2e8f9f7 444 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS 3
<> 144:ef7eb2e8f9f7 445 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
<> 144:ef7eb2e8f9f7 446 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS 4
<> 144:ef7eb2e8f9f7 447 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
<> 144:ef7eb2e8f9f7 448 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS 5
<> 144:ef7eb2e8f9f7 449 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
<> 144:ef7eb2e8f9f7 450 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS 6
<> 144:ef7eb2e8f9f7 451 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
<> 144:ef7eb2e8f9f7 452 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS 7
<> 144:ef7eb2e8f9f7 453 #define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS 0
<> 144:ef7eb2e8f9f7 456 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
<> 144:ef7eb2e8f9f7 457 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS 1
<> 144:ef7eb2e8f9f7 458 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
<> 144:ef7eb2e8f9f7 459 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS 2
<> 144:ef7eb2e8f9f7 460 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
<> 144:ef7eb2e8f9f7 461 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS 3
<> 144:ef7eb2e8f9f7 462 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
<> 144:ef7eb2e8f9f7 463 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS 4
<> 144:ef7eb2e8f9f7 464 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
<> 144:ef7eb2e8f9f7 465 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS 5
<> 144:ef7eb2e8f9f7 466 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
<> 144:ef7eb2e8f9f7 467 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS 6
<> 144:ef7eb2e8f9f7 468 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
<> 144:ef7eb2e8f9f7 469 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS 7
<> 144:ef7eb2e8f9f7 470 #define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7 ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS 0
<> 144:ef7eb2e8f9f7 473 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
<> 144:ef7eb2e8f9f7 474 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS 4
<> 144:ef7eb2e8f9f7 475 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
<> 144:ef7eb2e8f9f7 476 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS 8
<> 144:ef7eb2e8f9f7 477 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
<> 144:ef7eb2e8f9f7 478 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS 12
<> 144:ef7eb2e8f9f7 479 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
<> 144:ef7eb2e8f9f7 480 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS 16
<> 144:ef7eb2e8f9f7 481 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
<> 144:ef7eb2e8f9f7 482 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS 20
<> 144:ef7eb2e8f9f7 483 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
<> 144:ef7eb2e8f9f7 484 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS 24
<> 144:ef7eb2e8f9f7 485 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
<> 144:ef7eb2e8f9f7 486 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS 28
<> 144:ef7eb2e8f9f7 487 #define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7 ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS 0
<> 144:ef7eb2e8f9f7 490 #define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
<> 144:ef7eb2e8f9f7 491 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS 4
<> 144:ef7eb2e8f9f7 492 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
<> 144:ef7eb2e8f9f7 493 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
<> 144:ef7eb2e8f9f7 494 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
<> 144:ef7eb2e8f9f7 495 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS 8
<> 144:ef7eb2e8f9f7 496 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
<> 144:ef7eb2e8f9f7 497 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
<> 144:ef7eb2e8f9f7 498 #define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 #endif
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 #endif /* _MXC_IOMAN_REGS_H_ */