Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_SPI_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_SPI_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file spi_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup spi SPI
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Offset Register Description
<> 144:ef7eb2e8f9f7 50 ====== ============================================ */
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
<> 144:ef7eb2e8f9f7 59 __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
<> 144:ef7eb2e8f9f7 60 } mxc_spi_regs_t;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct {
<> 144:ef7eb2e8f9f7 66 union {
<> 144:ef7eb2e8f9f7 67 __O uint8_t txfifo_8;
<> 144:ef7eb2e8f9f7 68 __O uint16_t txfifo_16;
<> 144:ef7eb2e8f9f7 69 __O uint32_t txfifo_32;
<> 144:ef7eb2e8f9f7 70 };
<> 144:ef7eb2e8f9f7 71 } mxc_spi_txfifo_regs_t;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /**
<> 144:ef7eb2e8f9f7 74 * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 typedef struct {
<> 144:ef7eb2e8f9f7 77 union {
<> 144:ef7eb2e8f9f7 78 __I uint8_t rxfifo_8;
<> 144:ef7eb2e8f9f7 79 __I uint16_t rxfifo_16;
<> 144:ef7eb2e8f9f7 80 __I uint32_t rxfifo_32;
<> 144:ef7eb2e8f9f7 81 };
<> 144:ef7eb2e8f9f7 82 } mxc_spi_rxfifo_regs_t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /*
<> 144:ef7eb2e8f9f7 85 Register offsets for module SPI.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 #define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 88 #define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 89 #define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 90 #define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 91 #define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 93 #define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*
<> 144:ef7eb2e8f9f7 99 Field positions and masks for module SPI.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
<> 144:ef7eb2e8f9f7 102 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
<> 144:ef7eb2e8f9f7 103 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
<> 144:ef7eb2e8f9f7 104 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
<> 144:ef7eb2e8f9f7 105 #define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
<> 144:ef7eb2e8f9f7 106 #define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
<> 144:ef7eb2e8f9f7 107 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
<> 144:ef7eb2e8f9f7 108 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
<> 144:ef7eb2e8f9f7 110 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
<> 144:ef7eb2e8f9f7 112 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
<> 144:ef7eb2e8f9f7 114 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
<> 144:ef7eb2e8f9f7 116 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
<> 144:ef7eb2e8f9f7 117 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
<> 144:ef7eb2e8f9f7 118 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
<> 144:ef7eb2e8f9f7 119 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
<> 144:ef7eb2e8f9f7 120 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 123 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
<> 144:ef7eb2e8f9f7 124 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
<> 144:ef7eb2e8f9f7 125 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 144:ef7eb2e8f9f7 128 #define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 144:ef7eb2e8f9f7 129 #define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 144:ef7eb2e8f9f7 130 #define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
<> 144:ef7eb2e8f9f7 133 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
<> 144:ef7eb2e8f9f7 134 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
<> 144:ef7eb2e8f9f7 135 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
<> 144:ef7eb2e8f9f7 138 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
<> 144:ef7eb2e8f9f7 140 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
<> 144:ef7eb2e8f9f7 142 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
<> 144:ef7eb2e8f9f7 144 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
<> 144:ef7eb2e8f9f7 146 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
<> 144:ef7eb2e8f9f7 147 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
<> 144:ef7eb2e8f9f7 148 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
<> 144:ef7eb2e8f9f7 150 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
<> 144:ef7eb2e8f9f7 151 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
<> 144:ef7eb2e8f9f7 152 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
<> 144:ef7eb2e8f9f7 153 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
<> 144:ef7eb2e8f9f7 154 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
<> 144:ef7eb2e8f9f7 156 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
<> 144:ef7eb2e8f9f7 159 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
<> 144:ef7eb2e8f9f7 161 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
<> 144:ef7eb2e8f9f7 162 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
<> 144:ef7eb2e8f9f7 163 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
<> 144:ef7eb2e8f9f7 165 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
<> 144:ef7eb2e8f9f7 168 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
<> 144:ef7eb2e8f9f7 170 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
<> 144:ef7eb2e8f9f7 171 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
<> 144:ef7eb2e8f9f7 172 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
<> 144:ef7eb2e8f9f7 173 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
<> 144:ef7eb2e8f9f7 174 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 #define MXC_F_SPI_INTFL_TX_STALLED_POS 0
<> 144:ef7eb2e8f9f7 177 #define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_F_SPI_INTFL_RX_STALLED_POS 1
<> 144:ef7eb2e8f9f7 179 #define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
<> 144:ef7eb2e8f9f7 180 #define MXC_F_SPI_INTFL_TX_READY_POS 2
<> 144:ef7eb2e8f9f7 181 #define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
<> 144:ef7eb2e8f9f7 182 #define MXC_F_SPI_INTFL_RX_DONE_POS 3
<> 144:ef7eb2e8f9f7 183 #define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
<> 144:ef7eb2e8f9f7 184 #define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
<> 144:ef7eb2e8f9f7 185 #define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
<> 144:ef7eb2e8f9f7 187 #define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define MXC_F_SPI_INTEN_TX_STALLED_POS 0
<> 144:ef7eb2e8f9f7 190 #define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
<> 144:ef7eb2e8f9f7 191 #define MXC_F_SPI_INTEN_RX_STALLED_POS 1
<> 144:ef7eb2e8f9f7 192 #define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
<> 144:ef7eb2e8f9f7 193 #define MXC_F_SPI_INTEN_TX_READY_POS 2
<> 144:ef7eb2e8f9f7 194 #define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
<> 144:ef7eb2e8f9f7 195 #define MXC_F_SPI_INTEN_RX_DONE_POS 3
<> 144:ef7eb2e8f9f7 196 #define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
<> 144:ef7eb2e8f9f7 197 #define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
<> 144:ef7eb2e8f9f7 198 #define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
<> 144:ef7eb2e8f9f7 199 #define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
<> 144:ef7eb2e8f9f7 200 #define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #define MXC_F_SPI_FIFO_DIR_POS 0
<> 144:ef7eb2e8f9f7 203 #define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
<> 144:ef7eb2e8f9f7 204 #define MXC_F_SPI_FIFO_UNIT_POS 2
<> 144:ef7eb2e8f9f7 205 #define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
<> 144:ef7eb2e8f9f7 206 #define MXC_F_SPI_FIFO_SIZE_POS 4
<> 144:ef7eb2e8f9f7 207 #define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
<> 144:ef7eb2e8f9f7 208 #define MXC_F_SPI_FIFO_WIDTH_POS 9
<> 144:ef7eb2e8f9f7 209 #define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
<> 144:ef7eb2e8f9f7 210 #define MXC_F_SPI_FIFO_ALT_POS 11
<> 144:ef7eb2e8f9f7 211 #define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
<> 144:ef7eb2e8f9f7 212 #define MXC_F_SPI_FIFO_FLOW_POS 12
<> 144:ef7eb2e8f9f7 213 #define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
<> 144:ef7eb2e8f9f7 214 #define MXC_F_SPI_FIFO_DASS_POS 13
<> 144:ef7eb2e8f9f7 215 #define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 #endif
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #endif /* _MXC_SPI_REGS_H */