Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_PWRSEQ_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_PWRSEQ_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file pwrseq_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup pwrseq PWRSEQ
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Offset Register Description
<> 144:ef7eb2e8f9f7 50 ====== ================================================= */
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
<> 144:ef7eb2e8f9f7 59 __I uint32_t rsv001C; /* 0x001C */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
<> 144:ef7eb2e8f9f7 62 } mxc_pwrseq_regs_t;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /*
<> 144:ef7eb2e8f9f7 66 Register offsets for module PWRSEQ.
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 69 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 70 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 71 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 72 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 73 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 74 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 75 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 76 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /*
<> 144:ef7eb2e8f9f7 80 Field positions and masks for module PWRSEQ.
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
<> 144:ef7eb2e8f9f7 83 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
<> 144:ef7eb2e8f9f7 84 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
<> 144:ef7eb2e8f9f7 85 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
<> 144:ef7eb2e8f9f7 86 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
<> 144:ef7eb2e8f9f7 87 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
<> 144:ef7eb2e8f9f7 88 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS 3
<> 144:ef7eb2e8f9f7 89 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
<> 144:ef7eb2e8f9f7 90 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS 4
<> 144:ef7eb2e8f9f7 91 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
<> 144:ef7eb2e8f9f7 92 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS 5
<> 144:ef7eb2e8f9f7 93 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
<> 144:ef7eb2e8f9f7 94 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS 6
<> 144:ef7eb2e8f9f7 95 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
<> 144:ef7eb2e8f9f7 96 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
<> 144:ef7eb2e8f9f7 97 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
<> 144:ef7eb2e8f9f7 98 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
<> 144:ef7eb2e8f9f7 99 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
<> 144:ef7eb2e8f9f7 100 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
<> 144:ef7eb2e8f9f7 101 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
<> 144:ef7eb2e8f9f7 102 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
<> 144:ef7eb2e8f9f7 103 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
<> 144:ef7eb2e8f9f7 104 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
<> 144:ef7eb2e8f9f7 105 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
<> 144:ef7eb2e8f9f7 106 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
<> 144:ef7eb2e8f9f7 107 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
<> 144:ef7eb2e8f9f7 108 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS 13
<> 144:ef7eb2e8f9f7 109 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
<> 144:ef7eb2e8f9f7 110 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS 14
<> 144:ef7eb2e8f9f7 111 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
<> 144:ef7eb2e8f9f7 112 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS 15
<> 144:ef7eb2e8f9f7 113 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
<> 144:ef7eb2e8f9f7 114 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS 16
<> 144:ef7eb2e8f9f7 115 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
<> 144:ef7eb2e8f9f7 116 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
<> 144:ef7eb2e8f9f7 117 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
<> 144:ef7eb2e8f9f7 118 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS 18
<> 144:ef7eb2e8f9f7 119 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS 19
<> 144:ef7eb2e8f9f7 121 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS 0
<> 144:ef7eb2e8f9f7 124 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
<> 144:ef7eb2e8f9f7 125 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS 8
<> 144:ef7eb2e8f9f7 126 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS 9
<> 144:ef7eb2e8f9f7 128 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS 10
<> 144:ef7eb2e8f9f7 130 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
<> 144:ef7eb2e8f9f7 131 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS 11
<> 144:ef7eb2e8f9f7 132 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS 12
<> 144:ef7eb2e8f9f7 134 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS 13
<> 144:ef7eb2e8f9f7 136 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS 14
<> 144:ef7eb2e8f9f7 138 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS 0
<> 144:ef7eb2e8f9f7 141 #define MXC_F_PWRSEQ_REG2_PWR_RST3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
<> 144:ef7eb2e8f9f7 142 #define MXC_F_PWRSEQ_REG2_PWR_W3_POS 5
<> 144:ef7eb2e8f9f7 143 #define MXC_F_PWRSEQ_REG2_PWR_W3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
<> 144:ef7eb2e8f9f7 144 #define MXC_F_PWRSEQ_REG2_PWR_W1_POS 10
<> 144:ef7eb2e8f9f7 145 #define MXC_F_PWRSEQ_REG2_PWR_W1 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
<> 144:ef7eb2e8f9f7 146 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS 15
<> 144:ef7eb2e8f9f7 147 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
<> 144:ef7eb2e8f9f7 148 #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS 20
<> 144:ef7eb2e8f9f7 149 #define MXC_F_PWRSEQ_REG2_PWR_WRTC ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
<> 144:ef7eb2e8f9f7 150 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS 25
<> 144:ef7eb2e8f9f7 151 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
<> 144:ef7eb2e8f9f7 154 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
<> 144:ef7eb2e8f9f7 155 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS 3
<> 144:ef7eb2e8f9f7 156 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
<> 144:ef7eb2e8f9f7 157 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS 5
<> 144:ef7eb2e8f9f7 158 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
<> 144:ef7eb2e8f9f7 159 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS 8
<> 144:ef7eb2e8f9f7 160 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
<> 144:ef7eb2e8f9f7 161 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS 10
<> 144:ef7eb2e8f9f7 162 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
<> 144:ef7eb2e8f9f7 163 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 13
<> 144:ef7eb2e8f9f7 164 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
<> 144:ef7eb2e8f9f7 165 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 15
<> 144:ef7eb2e8f9f7 166 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
<> 144:ef7eb2e8f9f7 167 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS 16
<> 144:ef7eb2e8f9f7 168 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS 17
<> 144:ef7eb2e8f9f7 170 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
<> 144:ef7eb2e8f9f7 173 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
<> 144:ef7eb2e8f9f7 174 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
<> 144:ef7eb2e8f9f7 175 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
<> 144:ef7eb2e8f9f7 176 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS 2
<> 144:ef7eb2e8f9f7 177 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
<> 144:ef7eb2e8f9f7 178 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
<> 144:ef7eb2e8f9f7 179 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
<> 144:ef7eb2e8f9f7 180 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS 4
<> 144:ef7eb2e8f9f7 181 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
<> 144:ef7eb2e8f9f7 182 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS 5
<> 144:ef7eb2e8f9f7 183 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
<> 144:ef7eb2e8f9f7 184 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS 6
<> 144:ef7eb2e8f9f7 185 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
<> 144:ef7eb2e8f9f7 188 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
<> 144:ef7eb2e8f9f7 189 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS 6
<> 144:ef7eb2e8f9f7 190 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8 ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
<> 144:ef7eb2e8f9f7 191 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS 10
<> 144:ef7eb2e8f9f7 192 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3 ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
<> 144:ef7eb2e8f9f7 193 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS 15
<> 144:ef7eb2e8f9f7 194 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
<> 144:ef7eb2e8f9f7 197 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
<> 144:ef7eb2e8f9f7 198 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
<> 144:ef7eb2e8f9f7 199 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
<> 144:ef7eb2e8f9f7 200 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
<> 144:ef7eb2e8f9f7 201 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
<> 144:ef7eb2e8f9f7 204 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
<> 144:ef7eb2e8f9f7 206 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
<> 144:ef7eb2e8f9f7 207 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS 2
<> 144:ef7eb2e8f9f7 208 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
<> 144:ef7eb2e8f9f7 209 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
<> 144:ef7eb2e8f9f7 210 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
<> 144:ef7eb2e8f9f7 211 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS 4
<> 144:ef7eb2e8f9f7 212 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 213 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS 5
<> 144:ef7eb2e8f9f7 214 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 215 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS 6
<> 144:ef7eb2e8f9f7 216 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
<> 144:ef7eb2e8f9f7 217 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS 7
<> 144:ef7eb2e8f9f7 218 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
<> 144:ef7eb2e8f9f7 219 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS 8
<> 144:ef7eb2e8f9f7 220 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
<> 144:ef7eb2e8f9f7 221 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS 9
<> 144:ef7eb2e8f9f7 222 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
<> 144:ef7eb2e8f9f7 223 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS 10
<> 144:ef7eb2e8f9f7 224 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
<> 144:ef7eb2e8f9f7 225 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS 11
<> 144:ef7eb2e8f9f7 226 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
<> 144:ef7eb2e8f9f7 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS 12
<> 144:ef7eb2e8f9f7 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
<> 144:ef7eb2e8f9f7 229 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 13
<> 144:ef7eb2e8f9f7 230 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
<> 144:ef7eb2e8f9f7 231 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 14
<> 144:ef7eb2e8f9f7 232 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
<> 144:ef7eb2e8f9f7 233 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 15
<> 144:ef7eb2e8f9f7 234 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
<> 144:ef7eb2e8f9f7 235 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 16
<> 144:ef7eb2e8f9f7 236 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
<> 144:ef7eb2e8f9f7 237 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS 17
<> 144:ef7eb2e8f9f7 238 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
<> 144:ef7eb2e8f9f7 239 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
<> 144:ef7eb2e8f9f7 240 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 241 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
<> 144:ef7eb2e8f9f7 242 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 243 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS 20
<> 144:ef7eb2e8f9f7 244 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
<> 144:ef7eb2e8f9f7 245 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS 21
<> 144:ef7eb2e8f9f7 246 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
<> 144:ef7eb2e8f9f7 249 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
<> 144:ef7eb2e8f9f7 250 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS 2
<> 144:ef7eb2e8f9f7 251 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
<> 144:ef7eb2e8f9f7 252 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS 3
<> 144:ef7eb2e8f9f7 253 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
<> 144:ef7eb2e8f9f7 254 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS 4
<> 144:ef7eb2e8f9f7 255 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 256 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS 5
<> 144:ef7eb2e8f9f7 257 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 258 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS 6
<> 144:ef7eb2e8f9f7 259 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
<> 144:ef7eb2e8f9f7 260 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS 7
<> 144:ef7eb2e8f9f7 261 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
<> 144:ef7eb2e8f9f7 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS 8
<> 144:ef7eb2e8f9f7 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
<> 144:ef7eb2e8f9f7 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS 9
<> 144:ef7eb2e8f9f7 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
<> 144:ef7eb2e8f9f7 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS 10
<> 144:ef7eb2e8f9f7 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
<> 144:ef7eb2e8f9f7 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS 11
<> 144:ef7eb2e8f9f7 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
<> 144:ef7eb2e8f9f7 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS 12
<> 144:ef7eb2e8f9f7 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
<> 144:ef7eb2e8f9f7 272 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 13
<> 144:ef7eb2e8f9f7 273 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
<> 144:ef7eb2e8f9f7 274 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 14
<> 144:ef7eb2e8f9f7 275 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
<> 144:ef7eb2e8f9f7 276 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 15
<> 144:ef7eb2e8f9f7 277 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
<> 144:ef7eb2e8f9f7 278 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 16
<> 144:ef7eb2e8f9f7 279 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
<> 144:ef7eb2e8f9f7 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS 17
<> 144:ef7eb2e8f9f7 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
<> 144:ef7eb2e8f9f7 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 18
<> 144:ef7eb2e8f9f7 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 284 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 19
<> 144:ef7eb2e8f9f7 285 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 144:ef7eb2e8f9f7 286 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS 20
<> 144:ef7eb2e8f9f7 287 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
<> 144:ef7eb2e8f9f7 288 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS 21
<> 144:ef7eb2e8f9f7 289 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 #endif
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @}
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 #endif /* _MXC_PWRSEQ_REGS_H */