Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_I2CM_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_I2CM_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file i2cm_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup i2cm I2CM
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Offset Register Description
<> 144:ef7eb2e8f9f7 50 ====== ================================================ */
<> 144:ef7eb2e8f9f7 51 typedef struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */
<> 144:ef7eb2e8f9f7 54 __I uint32_t rsv0008; /* 0x0008 */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t intfl; /* 0x0018 Interrupt Flags */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 60 __I uint32_t rsv0020[2]; /* 0x0020 */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */
<> 144:ef7eb2e8f9f7 62 } mxc_i2cm_regs_t;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Offset Register Description
<> 144:ef7eb2e8f9f7 65 ====== ================================================ */
<> 144:ef7eb2e8f9f7 66 typedef struct {
<> 144:ef7eb2e8f9f7 67 __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */
<> 144:ef7eb2e8f9f7 69 } mxc_i2cm_fifo_regs_t;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /*
<> 144:ef7eb2e8f9f7 72 Register offsets for module I2CM.
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74 #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 75 #define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 76 #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 77 #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 78 #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 79 #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 80 #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 81 #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
<> 144:ef7eb2e8f9f7 82 #define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 85 #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*
<> 144:ef7eb2e8f9f7 88 Field positions and masks for module I2CM.
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90 #define MXC_S_I2CM_TRANS_TAG_START 0x000
<> 144:ef7eb2e8f9f7 91 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
<> 144:ef7eb2e8f9f7 92 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
<> 144:ef7eb2e8f9f7 93 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
<> 144:ef7eb2e8f9f7 94 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
<> 144:ef7eb2e8f9f7 95 #define MXC_S_I2CM_TRANS_TAG_STOP 0x700
<> 144:ef7eb2e8f9f7 96 #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
<> 144:ef7eb2e8f9f7 97 #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0
<> 144:ef7eb2e8f9f7 100 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
<> 144:ef7eb2e8f9f7 101 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8
<> 144:ef7eb2e8f9f7 102 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
<> 144:ef7eb2e8f9f7 103 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20
<> 144:ef7eb2e8f9f7 104 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
<> 144:ef7eb2e8f9f7 107 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 108 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
<> 144:ef7eb2e8f9f7 109 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
<> 144:ef7eb2e8f9f7 112 #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
<> 144:ef7eb2e8f9f7 114 #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
<> 144:ef7eb2e8f9f7 115 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
<> 144:ef7eb2e8f9f7 116 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #define MXC_F_I2CM_TRANS_TX_START_POS 0
<> 144:ef7eb2e8f9f7 119 #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
<> 144:ef7eb2e8f9f7 121 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
<> 144:ef7eb2e8f9f7 122 #define MXC_F_I2CM_TRANS_TX_DONE_POS 2
<> 144:ef7eb2e8f9f7 123 #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
<> 144:ef7eb2e8f9f7 124 #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
<> 144:ef7eb2e8f9f7 125 #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
<> 144:ef7eb2e8f9f7 126 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
<> 144:ef7eb2e8f9f7 127 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
<> 144:ef7eb2e8f9f7 128 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
<> 144:ef7eb2e8f9f7 129 #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 #define MXC_F_I2CM_INTFL_TX_DONE_POS 0
<> 144:ef7eb2e8f9f7 132 #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
<> 144:ef7eb2e8f9f7 133 #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
<> 144:ef7eb2e8f9f7 134 #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
<> 144:ef7eb2e8f9f7 136 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
<> 144:ef7eb2e8f9f7 137 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
<> 144:ef7eb2e8f9f7 138 #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 139 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
<> 144:ef7eb2e8f9f7 140 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 141 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
<> 144:ef7eb2e8f9f7 142 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
<> 144:ef7eb2e8f9f7 143 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 144 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
<> 144:ef7eb2e8f9f7 145 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
<> 144:ef7eb2e8f9f7 146 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
<> 144:ef7eb2e8f9f7 147 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
<> 144:ef7eb2e8f9f7 148 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
<> 144:ef7eb2e8f9f7 149 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
<> 144:ef7eb2e8f9f7 150 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 #define MXC_F_I2CM_INTEN_TX_DONE_POS 0
<> 144:ef7eb2e8f9f7 153 #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
<> 144:ef7eb2e8f9f7 154 #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
<> 144:ef7eb2e8f9f7 155 #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
<> 144:ef7eb2e8f9f7 156 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
<> 144:ef7eb2e8f9f7 157 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
<> 144:ef7eb2e8f9f7 158 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
<> 144:ef7eb2e8f9f7 159 #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 160 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
<> 144:ef7eb2e8f9f7 161 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 162 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
<> 144:ef7eb2e8f9f7 163 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
<> 144:ef7eb2e8f9f7 164 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6
<> 144:ef7eb2e8f9f7 165 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
<> 144:ef7eb2e8f9f7 166 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
<> 144:ef7eb2e8f9f7 167 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
<> 144:ef7eb2e8f9f7 168 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
<> 144:ef7eb2e8f9f7 169 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
<> 144:ef7eb2e8f9f7 170 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
<> 144:ef7eb2e8f9f7 171 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
<> 144:ef7eb2e8f9f7 174 #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
<> 144:ef7eb2e8f9f7 176 #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
<> 144:ef7eb2e8f9f7 178 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
<> 144:ef7eb2e8f9f7 180 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
<> 144:ef7eb2e8f9f7 182 #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186 #endif
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #endif