Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/wdt_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file wdt_map.h
<> 144:ef7eb2e8f9f7 4 * @brief WDT HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3283 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-02-26 18:52:22 +0530 (Thu, 26 Feb 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup wdt
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * Watchdog Timer HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 */
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 31 #pragma anon_unions
<> 144:ef7eb2e8f9f7 32 #endif
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef WDT_MAP_H_
<> 144:ef7eb2e8f9f7 35 #define WDT_MAP_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #include "architecture.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifdef REVB
<> 144:ef7eb2e8f9f7 40 /** Watch Dog Timer Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 41 typedef struct {
<> 144:ef7eb2e8f9f7 42 __IO uint32_t LOAD; /**< Watchdog load value */
<> 144:ef7eb2e8f9f7 43 __I uint32_t VALUE; /**< Watchdog current value */
<> 144:ef7eb2e8f9f7 44 union {
<> 144:ef7eb2e8f9f7 45 struct {
<> 144:ef7eb2e8f9f7 46 __IO uint32_t INT_EN :1; /**< interrupt event : 0 = disable counter and interrupt , 1 = enable counter and interrupt */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t RESET_EN :1; /**< Watchdog reset output : 0 = disable 1 = enable */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t PAD :30; /**< Reserved, read undefined, must read as zeros. */
<> 144:ef7eb2e8f9f7 49 } BITS;
<> 144:ef7eb2e8f9f7 50 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 51 } CONTROL;
<> 144:ef7eb2e8f9f7 52 __IO uint32_t INT_CLEAR; /**< Watchdog interrupt clear */
<> 144:ef7eb2e8f9f7 53 __I uint32_t RAW_INT_STAT; /**< Raw interrupt status from the counter */
<> 144:ef7eb2e8f9f7 54 __I uint32_t MASKED_INT_STAT; /**< Enabled interrupt status from the counter */
<> 144:ef7eb2e8f9f7 55 union {
<> 144:ef7eb2e8f9f7 56 struct {
<> 144:ef7eb2e8f9f7 57 __IO uint32_t WRITE_EN :1; /**< write access to all other registers : 0 = enabled(default) , 1 = disabled */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t REG_WRITE_EN :31; /**< Enable write access to all other registers by writing 0x1ACCE551. Disable it by writing any other value.*/
<> 144:ef7eb2e8f9f7 59 } BITS;
<> 144:ef7eb2e8f9f7 60 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 61 } LOCK;
<> 144:ef7eb2e8f9f7 62 __I uint32_t TEST_CTRL; /**< Integration Test Mode : 0 = disable , 1 = Enable */
<> 144:ef7eb2e8f9f7 63 union {
<> 144:ef7eb2e8f9f7 64 struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t VAL_INT :1; /**< Value output on WDOGINT when in Integration Test Mode */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t VAL_RES :1; /**< Value output on WDOGRES when in Integration Test Mode */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t PAD:30; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 68 } BITS;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 70 } TEST_OUT;
<> 144:ef7eb2e8f9f7 71 union {
<> 144:ef7eb2e8f9f7 72 struct {
<> 144:ef7eb2e8f9f7 73 __IO uint32_t PART_0 :8; /**< These bits read back as 0x05 */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 75 } BITS;
<> 144:ef7eb2e8f9f7 76 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 77 } PID_REG0;
<> 144:ef7eb2e8f9f7 78 union {
<> 144:ef7eb2e8f9f7 79 struct {
<> 144:ef7eb2e8f9f7 80 __IO uint32_t PART_1 :4; /**< These bits read back as 0x08 */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t DESIGNER_0 :4; /**< These bits read back as 0x01 */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 83 } BITS;
<> 144:ef7eb2e8f9f7 84 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 85 } PID_REG1;
<> 144:ef7eb2e8f9f7 86 union {
<> 144:ef7eb2e8f9f7 87 struct {
<> 144:ef7eb2e8f9f7 88 __IO uint32_t DESIGNER_1 :4; /**< These bits read back as 0x4 */
<> 144:ef7eb2e8f9f7 89 __IO uint32_t REVISION :4; /**< These bits read back as 0x0*/
<> 144:ef7eb2e8f9f7 90 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 91 } BITS;
<> 144:ef7eb2e8f9f7 92 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 93 } PID_REG2;
<> 144:ef7eb2e8f9f7 94 union {
<> 144:ef7eb2e8f9f7 95 struct {
<> 144:ef7eb2e8f9f7 96 __IO uint32_t CONFIG :8; /**< These bits read back as 0x00 */
<> 144:ef7eb2e8f9f7 97 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 98 } BITS;
<> 144:ef7eb2e8f9f7 99 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 100 } PID_REG3;
<> 144:ef7eb2e8f9f7 101 union {
<> 144:ef7eb2e8f9f7 102 struct {
<> 144:ef7eb2e8f9f7 103 __IO uint32_t ID0 :8; /**< These bits read back as 0x0D */
<> 144:ef7eb2e8f9f7 104 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 105 } BITS;
<> 144:ef7eb2e8f9f7 106 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 107 } PCELL_ID0;
<> 144:ef7eb2e8f9f7 108 union {
<> 144:ef7eb2e8f9f7 109 struct {
<> 144:ef7eb2e8f9f7 110 __IO uint32_t ID :8; /**< These bits read back as 0xF0*/
<> 144:ef7eb2e8f9f7 111 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 112 } BITS;
<> 144:ef7eb2e8f9f7 113 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 114 } PCELL_ID1;
<> 144:ef7eb2e8f9f7 115 union {
<> 144:ef7eb2e8f9f7 116 struct {
<> 144:ef7eb2e8f9f7 117 __IO uint32_t ID :8; /**< These bits read back as 0x05*/
<> 144:ef7eb2e8f9f7 118 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 119 } BITS;
<> 144:ef7eb2e8f9f7 120 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 121 } PCELL_ID2;
<> 144:ef7eb2e8f9f7 122 union {
<> 144:ef7eb2e8f9f7 123 struct {
<> 144:ef7eb2e8f9f7 124 __IO uint32_t ID :8; /**< These bits read back as 0xB1*/
<> 144:ef7eb2e8f9f7 125 __IO uint32_t PAD :24; /**< Reserved, read undefined, must read as zeros.*/
<> 144:ef7eb2e8f9f7 126 } BITS;
<> 144:ef7eb2e8f9f7 127 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 128 } PCELL_ID3;
<> 144:ef7eb2e8f9f7 129 } WdtReg_t, *WdtReg_pt;
<> 144:ef7eb2e8f9f7 130 #endif /* REVB */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #ifdef REVD
<> 144:ef7eb2e8f9f7 133 typedef struct {
<> 144:ef7eb2e8f9f7 134 __IO uint32_t LOAD; /**< 0x4000A000 Contains the value from which the counter is decremented. When this register is written to the count is immediately restarted from the new value. The minimum valid value is 1. */
<> 144:ef7eb2e8f9f7 135 __I uint32_t CURRENT_VALUE; /**< 0x4000A004 Gives the current value of the decrementing counter */
<> 144:ef7eb2e8f9f7 136 union {
<> 144:ef7eb2e8f9f7 137 struct {
<> 144:ef7eb2e8f9f7 138 __IO uint32_t WDT_EN :1; /**< Watchdog enable, 0 – Watchdog disabled, 1 – Watchdog enabled */
<> 144:ef7eb2e8f9f7 139 } BITS;
<> 144:ef7eb2e8f9f7 140 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 141 } CONTROL; /* 0x4000A008 */
<> 144:ef7eb2e8f9f7 142 __O uint32_t KICK; /**< 0x4000A00C A write of any value to this register reloads the value register from the load register */
<> 144:ef7eb2e8f9f7 143 __O uint32_t LOCK; /**< 0x4000A010 Use of this register causes write-access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 enables write access to all other registers. Writing any other value disables write access. A read from this register only returns the bottom bit…, 0 – Write access is enabled, 1 – Write access is disabled */
<> 144:ef7eb2e8f9f7 144 union {
<> 144:ef7eb2e8f9f7 145 struct {
<> 144:ef7eb2e8f9f7 146 __I uint32_t WRITE_BUSY_ANY :1; /**< Busy writing any register */
<> 144:ef7eb2e8f9f7 147 __I uint32_t WRITE_BUSY_LOAD :1; /**< Busy writing the load register */
<> 144:ef7eb2e8f9f7 148 __I uint32_t WRITE_BUSY_CONTROL :1; /**< Busy writing the control enable register */
<> 144:ef7eb2e8f9f7 149 __IO uint32_t WRITE_ERROR :1; /**< Error bit. Set when write occurs before previous write completes (busy) */
<> 144:ef7eb2e8f9f7 150 } BITS;
<> 144:ef7eb2e8f9f7 151 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 152 } STATUS; /* 0x4000A014 */
<> 144:ef7eb2e8f9f7 153 } WdtReg_t, *WdtReg_pt;
<> 144:ef7eb2e8f9f7 154 #endif /* REVD */
<> 144:ef7eb2e8f9f7 155 #endif /* WDT_MAP_H_ */