Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file uart_16c550.h
<> 144:ef7eb2e8f9f7 4 * @brief Definitions and API for the 16c550 driver.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2607 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-12-06 18:02:43 +0530 (Fri, 06 Dec 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup uart_16c550
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * The driver for the 16c550 UART is a character driver (see char_driver.h).
<> 144:ef7eb2e8f9f7 25 * The driver can be accessed via the uart_16c550_driver variable.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * This file defines the options structure to be passed to the driver when
<> 144:ef7eb2e8f9f7 28 * opening a device. The structure depends on the generic uart_options_t
<> 144:ef7eb2e8f9f7 29 * options structure for any UART implementation (see uart.h).
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * Any application that uses this driver must define an interrupt handler
<> 144:ef7eb2e8f9f7 32 * for the 16C550 interrupt and call the fUart16C550Handler() function from
<> 144:ef7eb2e8f9f7 33 * that ISR.
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #ifndef UART_16C550_H_
<> 144:ef7eb2e8f9f7 37 #define UART_16C550_H_
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #include "architecture.h"
<> 144:ef7eb2e8f9f7 40 #include "uart.h"
<> 144:ef7eb2e8f9f7 41 #include "uart_16c550_map.h"
<> 144:ef7eb2e8f9f7 42 #include "memory_map.h"
<> 144:ef7eb2e8f9f7 43 #include "crossbar.h"
<> 144:ef7eb2e8f9f7 44 #include "types.h"
<> 144:ef7eb2e8f9f7 45 #include "clock.h"
<> 144:ef7eb2e8f9f7 46 #include "pad.h"
<> 144:ef7eb2e8f9f7 47 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** A set of options to be passed when opening a 16C550 UART device. */
<> 144:ef7eb2e8f9f7 50 typedef struct uart_16c550_options {
<> 144:ef7eb2e8f9f7 51 uart_options_t uartOptions; /**< The generic UART options. */
<> 144:ef7eb2e8f9f7 52 Uart16C550Reg_pt membase; /**< The memory base for the device's registers. */
<> 144:ef7eb2e8f9f7 53 uint8_t irq; /**< The IRQ number of the IRQ associated to the device. */
<> 144:ef7eb2e8f9f7 54 } uart_16c550_options_t, *uart_16c550_options_pt;
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 #define UART_NUM 2
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 #define CTS_ASSERT 1
<> 144:ef7eb2e8f9f7 59 #define CTS_UNASSERT 0
<> 144:ef7eb2e8f9f7 60 #define RTS_ASSERT 1
<> 144:ef7eb2e8f9f7 61 #define RTS_UNASSERT 0
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 #define UART_ERROR_INSUFFICIENT_SPACE ((uint8_t)0xF0)
<> 144:ef7eb2e8f9f7 64 #define UART_ERROR_TOO_BIG ((uint8_t)0xF1)
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /** The depth of the hardware FIFOs. */
<> 144:ef7eb2e8f9f7 67 #define UART_HW_FIFO_DEPTH 16
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /** The length of the receive buffer in software. */
<> 144:ef7eb2e8f9f7 70 #define UART_RX_BUFFER_LENGTH (1<<8)
<> 144:ef7eb2e8f9f7 71 #define UART_TX_BUFFER_LENGTH (1<<8)
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #define STATUS_INVALID_PARAMETER 0x1
<> 144:ef7eb2e8f9f7 74 #define STATUS_SUCCESS 0x1
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define UART_LCR_DATALEN_BIT_POS 0
<> 144:ef7eb2e8f9f7 77 #define UART_LCR_STPBIT_BIT_POS 2
<> 144:ef7eb2e8f9f7 78 #define UART_LCR_PARITY_BIT_POS 3
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define UART_FCS_RX_FIFO_RST_BIT_POS 1
<> 144:ef7eb2e8f9f7 81 #define UART_FCS_TX_FIFO_RST_BIT_POS 2
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define UART_RX_IRQ 0x0
<> 144:ef7eb2e8f9f7 84 #define UART_TX_IRQ 0x1
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #define UART_RX_BUFFER_LEN_MAX 16
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #define UART_LSR_TX_EMPTY_MASK 0x40
<> 144:ef7eb2e8f9f7 89 #define UART_LSR_RX_DATA_READY_MASK 0x01
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #define UART_IER_TX_EMPTY_MASK 0x02
<> 144:ef7eb2e8f9f7 92 #define UART_IER_RX_DATA_READY_MASK 0x01
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #define UART_DEFAULT_BAUD 9600
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** Interrupt handler for 16C550 UART devices; to be called from an actual ISR.
<> 144:ef7eb2e8f9f7 97 * @param membase The memory base for the device that corresponds to the IRQ.
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 void fUart16C550Handler(Uart16C550Reg_pt membase);
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** An externally accessible instance of the UART driver implementation. */
<> 144:ef7eb2e8f9f7 102 //extern char_driver_t uart_16c550_driver;
<> 144:ef7eb2e8f9f7 103 typedef void (*fUartCallBack)(void);
<> 144:ef7eb2e8f9f7 104 //void serial_init(serial_t *obj, PinName tx, PinName rx);
<> 144:ef7eb2e8f9f7 105 //extern void fSerialInit(Uart16C550Reg_pt UartRegBase, flow_control_t FlowControl);
<> 144:ef7eb2e8f9f7 106 extern void fSerialFree(void);
<> 144:ef7eb2e8f9f7 107 extern void fSerialBaud(Uart16C550Reg_pt UartRegBase, uint32_t BaudRate);
<> 144:ef7eb2e8f9f7 108 extern void fSerialFormat(Uart16C550Reg_pt UartRegBase, uint8_t DataLen, uint8_t Parity, uint8_t StopBit);
<> 144:ef7eb2e8f9f7 109 extern void fSerialIrqSet(Uart16C550Reg_pt UartRegBase, fUartCallBack PtrUartCallBack, uint8_t IrqType, boolean Enable);
<> 144:ef7eb2e8f9f7 110 extern uint8_t fSerialGetc(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 111 extern void fSerialPutc(Uart16C550Reg_pt UartRegBase, uint8_t c);
<> 144:ef7eb2e8f9f7 112 extern boolean fSerialReadable(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 113 extern boolean fSerialWritable(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 114 extern void fSerialClear(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 115 extern void fSerialBreakSet(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 116 extern void fSerialBreakClear(Uart16C550Reg_pt UartRegBase);
<> 144:ef7eb2e8f9f7 117 extern void fSerialPinoutTx(uint8_t PinNo);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 extern void Uart1_Irq(void);
<> 144:ef7eb2e8f9f7 120 extern void Uart2_Irq(void);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #endif /* UART_16C550_H_ */