Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file Serial.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a 16C550 UART driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 0.1 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup uart_16c550
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24 #if DEVICE_SERIAL
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 29 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 30 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 33 #include <string.h>
<> 144:ef7eb2e8f9f7 34 #include "uart_16c550.h"
<> 144:ef7eb2e8f9f7 35 #include "cmsis_nvic.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 static IRQn_Type Irq;
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 uint32_t stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 40 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 static uint32_t serial_irq_ids[UART_NUM] = {0};
<> 144:ef7eb2e8f9f7 43 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 44 static inline void uart_irq(uint8_t status, uint32_t index);
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** Opens UART device.
<> 144:ef7eb2e8f9f7 48 * @details
<> 144:ef7eb2e8f9f7 49 * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1.
<> 144:ef7eb2e8f9f7 50 * The UART interrupt is enabled.
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 * @note The UART transmit interrupt is not enabled, because sending is controlled
<> 144:ef7eb2e8f9f7 53 * by the task.
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * @param UartNum A UART device instance.
<> 144:ef7eb2e8f9f7 56 * @param options The options parameter containing the baud rate.
<> 144:ef7eb2e8f9f7 57 * @return True if opening was successful.
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 uint16_t clockDivisor;
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 CrossbReg_t *CbRegOffSet;
<> 144:ef7eb2e8f9f7 65 PadReg_t *PadRegOffset;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 //find which peripheral is associated with the rx and tx pins
<> 144:ef7eb2e8f9f7 68 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 69 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 70 //check if the peripherals for each pin are the same or not
<> 144:ef7eb2e8f9f7 71 //returns the enum associated with the peripheral
<> 144:ef7eb2e8f9f7 72 //in the case of this target, the enum is the base address of the peripheral
<> 144:ef7eb2e8f9f7 73 obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 74 MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 77 pinmap_pinout(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
<> 144:ef7eb2e8f9f7 82 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 83 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85 /*TODO: determine if pullups are needed/recommended */
<> 144:ef7eb2e8f9f7 86 /* if (tx != NC) {
<> 144:ef7eb2e8f9f7 87 pin_mode(tx, PullUp);
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89 if (rx != NC) {
<> 144:ef7eb2e8f9f7 90 pin_mode(rx, PullUp);
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 /* Configure IOs to UART using cross bar, pad and GPIO settings */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 if(obj->UARTREG == UART2REG) {
<> 144:ef7eb2e8f9f7 96 /* UART 2 */
<> 144:ef7eb2e8f9f7 97 CLOCK_ENABLE(CLOCK_UART2);
<> 144:ef7eb2e8f9f7 98 Irq = Uart2_IRQn;
<> 144:ef7eb2e8f9f7 99 } else if(obj->UARTREG == UART1REG) {
<> 144:ef7eb2e8f9f7 100 /* UART 1 */
<> 144:ef7eb2e8f9f7 101 CLOCK_ENABLE(CLOCK_UART1);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 Irq = Uart1_IRQn;
<> 144:ef7eb2e8f9f7 104 } else {
<> 144:ef7eb2e8f9f7 105 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 109 CLOCK_ENABLE(CLOCK_CROSSB);
<> 144:ef7eb2e8f9f7 110 CLOCK_ENABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Configure tx pin as UART */
<> 144:ef7eb2e8f9f7 115 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 116 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Configure rx pin as UART */
<> 144:ef7eb2e8f9f7 119 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 120 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /** - Set pad parameters, output drive strength, pull piece control, output drive type */
<> 144:ef7eb2e8f9f7 123 PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 124 PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 127 PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
<> 144:ef7eb2e8f9f7 130 GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 CLOCK_DISABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 133 CLOCK_DISABLE(CLOCK_CROSSB);
<> 144:ef7eb2e8f9f7 134 CLOCK_DISABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
<> 144:ef7eb2e8f9f7 137 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
<> 144:ef7eb2e8f9f7 138 clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
<> 144:ef7eb2e8f9f7 139 obj->UARTREG->LCR.WORD = 0x80;
<> 144:ef7eb2e8f9f7 140 obj->UARTREG->DLL = clockDivisor & 0xFF;
<> 144:ef7eb2e8f9f7 141 obj->UARTREG->DLM = clockDivisor >> 8;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register,
<> 144:ef7eb2e8f9f7 144 * effectively disabling the divisor latch. */
<> 144:ef7eb2e8f9f7 145 obj->UARTREG->LCR.WORD = 0x03;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode
<> 144:ef7eb2e8f9f7 148 to 1. */
<> 144:ef7eb2e8f9f7 149 obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 |
<> 144:ef7eb2e8f9f7 150 FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE);
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the
<> 144:ef7eb2e8f9f7 153 * flow control state. */
<> 144:ef7eb2e8f9f7 154 obj->UARTREG->SCR = obj->UARTREG->MSR.WORD;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 if((int)obj->UARTREG == STDIO_UART) {
<> 144:ef7eb2e8f9f7 157 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 158 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 NVIC_ClearPendingIRQ(Irq);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 return;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** Closes a UART device.
<> 144:ef7eb2e8f9f7 167 * @details
<> 144:ef7eb2e8f9f7 168 * Disables the UART interrupt.
<> 144:ef7eb2e8f9f7 169 *
<> 144:ef7eb2e8f9f7 170 * @param device The UART device to close.
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 void serial_free(serial_t *obj)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 NVIC_DisableIRQ(obj->IRQType);
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 void serial_baud(serial_t *obj, int baudrate)
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
<> 144:ef7eb2e8f9f7 180 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
<> 144:ef7eb2e8f9f7 181 uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 obj->UARTREG->LCR.BITS.DLAB = True;
<> 144:ef7eb2e8f9f7 184 obj->UARTREG->DLL = clockDivisor & 0xFF;
<> 144:ef7eb2e8f9f7 185 obj->UARTREG->DLM = clockDivisor >> 8;
<> 144:ef7eb2e8f9f7 186 obj->UARTREG->LCR.BITS.DLAB = False;
<> 144:ef7eb2e8f9f7 187 }
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /*
<> 144:ef7eb2e8f9f7 190 Parity XX0 – Parity disabled; 001 – Odd Parity; 011 – Even Parity; 101 – Stick Parity, checked as 1; 111 – Stick Parity, checked as 0.
<> 144:ef7eb2e8f9f7 191 StopBit 0 – 1 stop bit; 1 – 2 stop bits.
<> 144:ef7eb2e8f9f7 192 DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) {
<> 144:ef7eb2e8f9f7 197 if(parity == (SerialParity)0) {
<> 144:ef7eb2e8f9f7 198 parity = (SerialParity)0;
<> 144:ef7eb2e8f9f7 199 } else {
<> 144:ef7eb2e8f9f7 200 parity = (SerialParity)(parity + parity - 1) ;
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
<> 144:ef7eb2e8f9f7 204 (parity << UART_LCR_PARITY_BIT_POS) |
<> 144:ef7eb2e8f9f7 205 ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
<> 144:ef7eb2e8f9f7 206 } else {
<> 144:ef7eb2e8f9f7 207 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 208 }
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 irq_handler = handler;
<> 144:ef7eb2e8f9f7 214 serial_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /******************************************************
<> 144:ef7eb2e8f9f7 218 ************* Internal IRQ functions ******************
<> 144:ef7eb2e8f9f7 219 *******************************************************/
<> 144:ef7eb2e8f9f7 220 void Uart1_Irq()
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
<> 144:ef7eb2e8f9f7 223 uint8_t irq_mask = 0;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 226 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 230 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
<> 144:ef7eb2e8f9f7 234 uart_irq(active_irq & irq_mask, 0);
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 void Uart2_Irq()
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
<> 144:ef7eb2e8f9f7 240 uint8_t irq_mask = 0;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 243 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
<> 144:ef7eb2e8f9f7 247 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
<> 144:ef7eb2e8f9f7 251 uart_irq(active_irq & irq_mask, 1);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 static inline void uart_irq(uint8_t status, uint32_t index)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 if (serial_irq_ids[index] != 0) {
<> 144:ef7eb2e8f9f7 258 if (status & UART_LSR_TX_EMPTY_MASK) {
<> 144:ef7eb2e8f9f7 259 irq_handler(serial_irq_ids[index], TxIrq);
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261 if (status & UART_LSR_RX_DATA_READY_MASK) {
<> 144:ef7eb2e8f9f7 262 irq_handler(serial_irq_ids[index], RxIrq);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266 /******************************************************/
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 IRQn_Type irq_n = (IRQn_Type)0;
<> 144:ef7eb2e8f9f7 271 uint32_t Vector = 0;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Check UART number & assign irq handler */
<> 144:ef7eb2e8f9f7 274 if(obj->UARTREG == UART1REG) {
<> 144:ef7eb2e8f9f7 275 /* UART 2 */
<> 144:ef7eb2e8f9f7 276 Vector = (uint32_t)&Uart1_Irq;
<> 144:ef7eb2e8f9f7 277 irq_n = Uart1_IRQn;
<> 144:ef7eb2e8f9f7 278 } else if(obj->UARTREG == UART2REG) {
<> 144:ef7eb2e8f9f7 279 /* UART 1 */
<> 144:ef7eb2e8f9f7 280 Vector = (uint32_t)&Uart2_Irq;
<> 144:ef7eb2e8f9f7 281 irq_n = Uart2_IRQn;
<> 144:ef7eb2e8f9f7 282 } else {
<> 144:ef7eb2e8f9f7 283 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Check IRQ type & enable/disable accordingly */
<> 144:ef7eb2e8f9f7 287 if(enable) {
<> 144:ef7eb2e8f9f7 288 /* Enable */
<> 144:ef7eb2e8f9f7 289 if(irq == RxIrq) {
<> 144:ef7eb2e8f9f7 290 /* Rx IRQ */
<> 144:ef7eb2e8f9f7 291 obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
<> 144:ef7eb2e8f9f7 292 obj->UARTREG->IER.BITS.RX_DATA_INT = True;
<> 144:ef7eb2e8f9f7 293 } else if(irq == TxIrq) {
<> 144:ef7eb2e8f9f7 294 /* Tx IRQ */
<> 144:ef7eb2e8f9f7 295 obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
<> 144:ef7eb2e8f9f7 296 } else {
<> 144:ef7eb2e8f9f7 297 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 NVIC_SetVector(irq_n, Vector);
<> 144:ef7eb2e8f9f7 300 NVIC_EnableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 301 } else {
<> 144:ef7eb2e8f9f7 302 /* Disable */
<> 144:ef7eb2e8f9f7 303 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 304 if(irq == RxIrq) {
<> 144:ef7eb2e8f9f7 305 /* Rx IRQ */
<> 144:ef7eb2e8f9f7 306 obj->UARTREG->IER.BITS.RX_DATA_INT = False;
<> 144:ef7eb2e8f9f7 307 } else if(irq == TxIrq) {
<> 144:ef7eb2e8f9f7 308 /* Tx IRQ */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
<> 144:ef7eb2e8f9f7 311 } else {
<> 144:ef7eb2e8f9f7 312 MBED_ASSERT(False);
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 uint8_t c;
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
<> 144:ef7eb2e8f9f7 322 c = obj->UARTREG->RBR & 0xFF; /* Get received character */
<> 144:ef7eb2e8f9f7 323 return c;
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
<> 144:ef7eb2e8f9f7 330 obj->UARTREG->THR = c; /* Transmit byte */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 return obj->UARTREG->LSR.BITS.READY;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 void serial_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Reset TX & RX FIFO */
<> 144:ef7eb2e8f9f7 347 obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
<> 144:ef7eb2e8f9f7 348 (True << UART_FCS_RX_FIFO_RST_BIT_POS));
<> 144:ef7eb2e8f9f7 349 }
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 obj->UARTREG->LCR.BITS.BREAK = True;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 357 {
<> 144:ef7eb2e8f9f7 358 obj->UARTREG->LCR.BITS.BREAK = False;
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 /* COnfigure PinNo to drive strength of 1, Push pull and pull none */
<> 144:ef7eb2e8f9f7 364 fPadIOCtrl(tx, 1, 0, 1);
<> 144:ef7eb2e8f9f7 365 }
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** Configure the serial for the flow control. It sets flow control in the hardware
<> 144:ef7eb2e8f9f7 368 * if a serial peripheral supports it, otherwise software emulation is used.
<> 144:ef7eb2e8f9f7 369 *
<> 144:ef7eb2e8f9f7 370 * @param obj The serial object
<> 144:ef7eb2e8f9f7 371 * @param type The type of the flow control. Look at the available FlowControl types.
<> 144:ef7eb2e8f9f7 372 * @param rxflow The TX pin name
<> 144:ef7eb2e8f9f7 373 * @param txflow The RX pin name
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* TODO: This is an empty implementation for now.*/
<> 144:ef7eb2e8f9f7 378 }
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 #endif /* DEVICE_SERIAL */