Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rtc_map.h
<> 144:ef7eb2e8f9f7 4 * @brief Real Time Clock HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev: 3008 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup rtc
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * Teal Time Clock HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 29 * <p>
<> 144:ef7eb2e8f9f7 30 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 31 * IPC7206 APB RTC Design Specification v1.0 </a>
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #ifndef RTC_MAP_H_
<> 144:ef7eb2e8f9f7 36 #define RTC_MAP_H_
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "architecture.h"
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /** Real Time Clock Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 41 typedef struct {
<> 144:ef7eb2e8f9f7 42 #ifdef REVB
<> 144:ef7eb2e8f9f7 43 /*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t SECOND;/**<SECOND Counter */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t MINUTE;/**<DAY Counter */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t HOUR;/**< HOUR Counter */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t DAY;/**< DAY Counter */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t MONTH;/**< MONTH Counter */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t YEAR;/**< YEAR Counter */
<> 144:ef7eb2e8f9f7 50 union {
<> 144:ef7eb2e8f9f7 51 struct {
<> 144:ef7eb2e8f9f7 52 __IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
<> 144:ef7eb2e8f9f7 60 } BITS;
<> 144:ef7eb2e8f9f7 61 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 62 } CONTROL;
<> 144:ef7eb2e8f9f7 63 __IO uint32_t DIVISOR;/**<Clock Divisor value */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
<> 144:ef7eb2e8f9f7 67 __IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
<> 144:ef7eb2e8f9f7 68 __IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
<> 144:ef7eb2e8f9f7 70 union {
<> 144:ef7eb2e8f9f7 71 struct {
<> 144:ef7eb2e8f9f7 72 __IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
<> 144:ef7eb2e8f9f7 79 } BITS;
<> 144:ef7eb2e8f9f7 80 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 81 } INT_EN_CONTROL;
<> 144:ef7eb2e8f9f7 82 union {
<> 144:ef7eb2e8f9f7 83 struct {
<> 144:ef7eb2e8f9f7 84 __I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 85 __I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 86 __I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 87 __I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 88 __I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 89 __I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
<> 144:ef7eb2e8f9f7 90 __I uint32_t PAD :2; /**<Read as 00 */
<> 144:ef7eb2e8f9f7 91 } BITS;
<> 144:ef7eb2e8f9f7 92 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 93 } INT_STATUS;
<> 144:ef7eb2e8f9f7 94 union {
<> 144:ef7eb2e8f9f7 95 struct {
<> 144:ef7eb2e8f9f7 96 __O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
<> 144:ef7eb2e8f9f7 97 __O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
<> 144:ef7eb2e8f9f7 98 __O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
<> 144:ef7eb2e8f9f7 99 __O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
<> 144:ef7eb2e8f9f7 100 __O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
<> 144:ef7eb2e8f9f7 101 __O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
<> 144:ef7eb2e8f9f7 102 __O uint32_t PAD :2 ;/**< Writes have no effect. */
<> 144:ef7eb2e8f9f7 103 } BITS;
<> 144:ef7eb2e8f9f7 104 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 105 } INT_CLEAR;
<> 144:ef7eb2e8f9f7 106 #endif /* REVB */
<> 144:ef7eb2e8f9f7 107 #ifdef REVD
<> 144:ef7eb2e8f9f7 108 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
<> 144:ef7eb2e8f9f7 109 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
<> 144:ef7eb2e8f9f7 110 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
<> 144:ef7eb2e8f9f7 111 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
<> 144:ef7eb2e8f9f7 112 union {
<> 144:ef7eb2e8f9f7 113 struct {
<> 144:ef7eb2e8f9f7 114 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
<> 144:ef7eb2e8f9f7 115 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
<> 144:ef7eb2e8f9f7 116 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 144:ef7eb2e8f9f7 117 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
<> 144:ef7eb2e8f9f7 118 } BITS;
<> 144:ef7eb2e8f9f7 119 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 120 } CONTROL; /* 0x4000F010 */
<> 144:ef7eb2e8f9f7 121 union {
<> 144:ef7eb2e8f9f7 122 struct {
<> 144:ef7eb2e8f9f7 123 /**<Any write to the status register will clear the error bit. */
<> 144:ef7eb2e8f9f7 124 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 144:ef7eb2e8f9f7 125 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
<> 144:ef7eb2e8f9f7 126 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
<> 144:ef7eb2e8f9f7 127 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
<> 144:ef7eb2e8f9f7 128 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
<> 144:ef7eb2e8f9f7 129 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
<> 144:ef7eb2e8f9f7 130 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
<> 144:ef7eb2e8f9f7 131 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
<> 144:ef7eb2e8f9f7 132 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
<> 144:ef7eb2e8f9f7 133 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
<> 144:ef7eb2e8f9f7 134 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
<> 144:ef7eb2e8f9f7 135 } BITS;
<> 144:ef7eb2e8f9f7 136 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 137 } STATUS; /* 0x4000F014 */
<> 144:ef7eb2e8f9f7 138 union {
<> 144:ef7eb2e8f9f7 139 struct {
<> 144:ef7eb2e8f9f7 140 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
<> 144:ef7eb2e8f9f7 141 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
<> 144:ef7eb2e8f9f7 142 } BITS;
<> 144:ef7eb2e8f9f7 143 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 144 } INT_CLEAR; /* 0x4000F018 */
<> 144:ef7eb2e8f9f7 145 #endif /* REVD */
<> 144:ef7eb2e8f9f7 146 } RtcReg_t, *RtcReg_pt;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #endif /* RTC_MAP_H_ */