Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rfAna_map.h
<> 144:ef7eb2e8f9f7 4 * @brief rfAna hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2953 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-09-15 18:13:01 +0530 (Mon, 15 Sep 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup rfAna
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * Rf and Analog control and trimming hw module register map
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 */
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #ifndef RFANA_MAP_H_
<> 144:ef7eb2e8f9f7 30 #define RFANA_MAP_H_
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 33 * *
<> 144:ef7eb2e8f9f7 34 * Header files *
<> 144:ef7eb2e8f9f7 35 * *
<> 144:ef7eb2e8f9f7 36 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "architecture.h"
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 41 * *
<> 144:ef7eb2e8f9f7 42 * Type definitions *
<> 144:ef7eb2e8f9f7 43 * *
<> 144:ef7eb2e8f9f7 44 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** rfAna register map (control part) */
<> 144:ef7eb2e8f9f7 47 typedef struct {
<> 144:ef7eb2e8f9f7 48 union {
<> 144:ef7eb2e8f9f7 49 struct {
<> 144:ef7eb2e8f9f7 50 __IO uint32_t FRACT_WORD:24;
<> 144:ef7eb2e8f9f7 51 __IO uint32_t INT_WORD:8;
<> 144:ef7eb2e8f9f7 52 } BITS;
<> 144:ef7eb2e8f9f7 53 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 54 } TX_LO_CONTROL;
<> 144:ef7eb2e8f9f7 55 union {
<> 144:ef7eb2e8f9f7 56 struct {
<> 144:ef7eb2e8f9f7 57 __IO uint32_t FRACT_WORD:24;
<> 144:ef7eb2e8f9f7 58 __IO uint32_t INT_WORD:8;
<> 144:ef7eb2e8f9f7 59 } BITS;
<> 144:ef7eb2e8f9f7 60 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 61 } RX_LO_CONTROL;
<> 144:ef7eb2e8f9f7 62 union {
<> 144:ef7eb2e8f9f7 63 struct {
<> 144:ef7eb2e8f9f7 64 __IO uint32_t PLL_RESET_TIME:10;
<> 144:ef7eb2e8f9f7 65 __I uint32_t RESERVED:6;
<> 144:ef7eb2e8f9f7 66 __IO uint32_t PLL_LOCK_TIME:10;
<> 144:ef7eb2e8f9f7 67 } BITS;
<> 144:ef7eb2e8f9f7 68 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 69 } PLL_TIMING;
<> 144:ef7eb2e8f9f7 70 union {
<> 144:ef7eb2e8f9f7 71 struct {
<> 144:ef7eb2e8f9f7 72 __IO uint32_t LNA_GAIN_MODE:1;
<> 144:ef7eb2e8f9f7 73 __IO uint32_t ADC_DITHER_MODE:1;
<> 144:ef7eb2e8f9f7 74 } BITS;
<> 144:ef7eb2e8f9f7 75 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 76 } RX_CONTROL;
<> 144:ef7eb2e8f9f7 77 __IO uint32_t TX_POWER;
<> 144:ef7eb2e8f9f7 78 __I uint32_t RECEIVER_GAIN;
<> 144:ef7eb2e8f9f7 79 } RfAnaReg_t, *RfAnaReg_pt;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** rfAna register map (trimming part) */
<> 144:ef7eb2e8f9f7 82 typedef struct {
<> 144:ef7eb2e8f9f7 83 __IO uint32_t PMU_TRIM;
<> 144:ef7eb2e8f9f7 84 __IO uint32_t RESERVED;
<> 144:ef7eb2e8f9f7 85 __IO uint32_t RX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 86 union {
<> 144:ef7eb2e8f9f7 87 struct {
<> 144:ef7eb2e8f9f7 88 __I uint32_t BIAS_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 89 __I uint32_t MODULATION_TRIM:4;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t TX_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 91 __IO uint32_t RX_VCO_TRIM:4;
<> 144:ef7eb2e8f9f7 92 __I uint32_t DIV_TRIM:3;
<> 144:ef7eb2e8f9f7 93 __I uint32_t REG_TRIM:2;
<> 144:ef7eb2e8f9f7 94 __I uint32_t LFR_TRIM:3;
<> 144:ef7eb2e8f9f7 95 __I uint32_t PAD0:4;
<> 144:ef7eb2e8f9f7 96 __I uint32_t CHARGE_PUMP_RANGE:4;
<> 144:ef7eb2e8f9f7 97 } BITS;
<> 144:ef7eb2e8f9f7 98 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 99 } PLL_TRIM;
<> 144:ef7eb2e8f9f7 100 __IO uint32_t PLL_VCO_TAP_LOCATION;
<> 144:ef7eb2e8f9f7 101 __IO uint32_t TX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 102 #ifdef REVC
<> 144:ef7eb2e8f9f7 103 __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
<> 144:ef7eb2e8f9f7 104 __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
<> 144:ef7eb2e8f9f7 105 __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
<> 144:ef7eb2e8f9f7 106 __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
<> 144:ef7eb2e8f9f7 107 __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
<> 144:ef7eb2e8f9f7 108 #endif
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef REVD
<> 144:ef7eb2e8f9f7 111 __IO uint32_t RX_VCO_TRIM_LUT2; /** 0x40019098 */
<> 144:ef7eb2e8f9f7 112 __IO uint32_t RX_VCO_TRIM_LUT1; /** 0x4001909C */
<> 144:ef7eb2e8f9f7 113 __IO uint32_t TX_VCO_TRIM_LUT2; /** 0x400190A0 */
<> 144:ef7eb2e8f9f7 114 __IO uint32_t TX_VCO_TRIM_LUT1; /** 0x400190A4 */
<> 144:ef7eb2e8f9f7 115 __IO uint32_t ADC_OFFSET_BUF; /** 0x400190A8 */
<> 144:ef7eb2e8f9f7 116 #endif /* REVD */
<> 144:ef7eb2e8f9f7 117 } RfAnaTrimReg_t, *RfAnaTrimReg_pt;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #endif /* RFANA_MAP_H_ */