Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/objects.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file Objects.h
<> 144:ef7eb2e8f9f7 4 * @brief Implements an assertion.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 0.1 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-06 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup debug
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23 #ifndef OBJECTS_H_
<> 144:ef7eb2e8f9f7 24 #define OBJECTS_H_
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 28 extern "C" {
<> 144:ef7eb2e8f9f7 29 #endif
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #include "gpio_map.h"
<> 144:ef7eb2e8f9f7 32 #include "uart_16c550_map.h"
<> 144:ef7eb2e8f9f7 33 #include "PinNames.h"
<> 144:ef7eb2e8f9f7 34 #include "PortNames.h"
<> 144:ef7eb2e8f9f7 35 #include "PeripheralNames.h"
<> 144:ef7eb2e8f9f7 36 #include "target_config.h"
<> 144:ef7eb2e8f9f7 37 #include "spi.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 typedef enum {
<> 144:ef7eb2e8f9f7 40 FlowControlNone_1,
<> 144:ef7eb2e8f9f7 41 FlowControlRTS_1,
<> 144:ef7eb2e8f9f7 42 FlowControlCTS_1,
<> 144:ef7eb2e8f9f7 43 FlowControlRTSCTS_1
<> 144:ef7eb2e8f9f7 44 } FlowControl_1;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 struct serial_s {
<> 144:ef7eb2e8f9f7 47 Uart16C550Reg_pt UARTREG;
<> 144:ef7eb2e8f9f7 48 FlowControl_1 FlowCtrl;
<> 144:ef7eb2e8f9f7 49 IRQn_Type IRQType;
<> 144:ef7eb2e8f9f7 50 int index;
<> 144:ef7eb2e8f9f7 51 };
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 typedef struct _gpio_t {
<> 144:ef7eb2e8f9f7 54 GpioReg_pt GPIOMEMBASE;
<> 144:ef7eb2e8f9f7 55 PinName gpioPin;
<> 144:ef7eb2e8f9f7 56 uint32_t gpioMask;
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 } gpio_t;
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* TODO: This is currently a dummy structure; implementation will be done along
<> 144:ef7eb2e8f9f7 62 * with the sleep API implementation
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct sleep_s {
<> 144:ef7eb2e8f9f7 65 uint32_t timeToSleep; /* 0: Use sleep type variable; Noz-zero: Selects sleep type based on duration using table 1. sleep below */
<> 144:ef7eb2e8f9f7 66 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
<> 144:ef7eb2e8f9f7 67 } sleep_t;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Table 1. Sleep
<> 144:ef7eb2e8f9f7 70 ___________________________________________________________________________________
<> 144:ef7eb2e8f9f7 71 | Sleep duration | Sleep Type |
<> 144:ef7eb2e8f9f7 72 |-------------------------------------------------------------------|---------------|
<> 144:ef7eb2e8f9f7 73 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
<> 144:ef7eb2e8f9f7 74 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
<> 144:ef7eb2e8f9f7 75 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
<> 144:ef7eb2e8f9f7 76 |___________________________________________________________________|_______________|
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 struct gpio_irq_s {
<> 144:ef7eb2e8f9f7 81 uint32_t pin;
<> 144:ef7eb2e8f9f7 82 uint32_t pinMask;
<> 144:ef7eb2e8f9f7 83 GpioReg_pt GPIOMEMBASE;
<> 144:ef7eb2e8f9f7 84 };
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 typedef struct {
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* options to configure the ADC */
<> 144:ef7eb2e8f9f7 89 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
<> 144:ef7eb2e8f9f7 90 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
<> 144:ef7eb2e8f9f7 91 uint8_t measurementType; /**< 1= Absolute 0= Differential */
<> 144:ef7eb2e8f9f7 92 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
<> 144:ef7eb2e8f9f7 93 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
<> 144:ef7eb2e8f9f7 94 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
<> 144:ef7eb2e8f9f7 95 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
<> 144:ef7eb2e8f9f7 96 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
<> 144:ef7eb2e8f9f7 97 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
<> 144:ef7eb2e8f9f7 98 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 } analog_config_s;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 struct analogin_s {
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 analog_config_s *adcConf;
<> 144:ef7eb2e8f9f7 105 AdcReg_pt adcReg;
<> 144:ef7eb2e8f9f7 106 PinName pin;
<> 144:ef7eb2e8f9f7 107 uint8_t pinFlag;
<> 144:ef7eb2e8f9f7 108 };
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 struct pwmout_s {
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 PwmReg_pt pwmReg;
<> 144:ef7eb2e8f9f7 113 };
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 struct port_s {
<> 144:ef7eb2e8f9f7 116 GpioReg_pt GPIOMEMBASE;
<> 144:ef7eb2e8f9f7 117 PortName port;
<> 144:ef7eb2e8f9f7 118 uint32_t mask;
<> 144:ef7eb2e8f9f7 119 };
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 typedef enum {
<> 144:ef7eb2e8f9f7 122 littleEndian = 0,
<> 144:ef7eb2e8f9f7 123 bigEndian
<> 144:ef7eb2e8f9f7 124 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** Type for the clock polarity. */
<> 144:ef7eb2e8f9f7 127 typedef enum {
<> 144:ef7eb2e8f9f7 128 activeLow = 0,
<> 144:ef7eb2e8f9f7 129 activeHigh
<> 144:ef7eb2e8f9f7 130 } spi_clockPolarity_t, *spi_clockPolarity_pt;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** Type for the clock phase. */
<> 144:ef7eb2e8f9f7 133 typedef enum {
<> 144:ef7eb2e8f9f7 134 risingEdge = 0,
<> 144:ef7eb2e8f9f7 135 fallingEdge
<> 144:ef7eb2e8f9f7 136 } spi_clockPhase_t, *spi_clockPhase_pt;
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 struct spi_s {
<> 144:ef7eb2e8f9f7 139 SpiIpc7207Reg_pt membase; /* Register address */
<> 144:ef7eb2e8f9f7 140 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
<> 144:ef7eb2e8f9f7 141 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
<> 144:ef7eb2e8f9f7 142 * - bit 7 = Receive FIFO Full
<> 144:ef7eb2e8f9f7 143 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
<> 144:ef7eb2e8f9f7 144 * - bit 5 = Receive FIFO Not Empty
<> 144:ef7eb2e8f9f7 145 * - bit 4 = Transmit FIFO Not Full
<> 144:ef7eb2e8f9f7 146 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
<> 144:ef7eb2e8f9f7 147 * - bit 2 = Transmit FIFO Empty
<> 144:ef7eb2e8f9f7 148 * - bit 1 = Transfer Error
<> 144:ef7eb2e8f9f7 149 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
<> 144:ef7eb2e8f9f7 150 * (unused option in current implementation / irq 6 and 7 used) */
<> 144:ef7eb2e8f9f7 151 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
<> 144:ef7eb2e8f9f7 152 * - 0 (x4) = Slave select enable
<> 144:ef7eb2e8f9f7 153 * - 1 (x4) = Slave select disable */
<> 144:ef7eb2e8f9f7 154 uint8_t slaveSelectBurst; /* Slave Select burst mode:
<> 144:ef7eb2e8f9f7 155 * - NO_BURST_MODE = Burst mode disable
<> 144:ef7eb2e8f9f7 156 * - BURST_MODE = Burst mode enable */
<> 144:ef7eb2e8f9f7 157 uint8_t slaveSelectPolarity;/* Slave Select polarity (x4) for up to 4 slaves:
<> 144:ef7eb2e8f9f7 158 * - 0 (x4) = Slave select is active low
<> 144:ef7eb2e8f9f7 159 * - 1 (x4) = Slave select is active high */
<> 144:ef7eb2e8f9f7 160 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
<> 144:ef7eb2e8f9f7 161 * - Value between 1 and 15
<> 144:ef7eb2e8f9f7 162 * (unused option in current implementation / not txWatermark irq used) */
<> 144:ef7eb2e8f9f7 163 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
<> 144:ef7eb2e8f9f7 164 * - Value between 1 and 15
<> 144:ef7eb2e8f9f7 165 * * (unused option in current implementation / rxWatermark fixed to 1) */
<> 144:ef7eb2e8f9f7 166 spi_ipc7207_endian_t endian; /* Bits endianness:
<> 144:ef7eb2e8f9f7 167 * - LITTLE_ENDIAN = LSB first
<> 144:ef7eb2e8f9f7 168 * - BIG_ENDIAN = MSB first */
<> 144:ef7eb2e8f9f7 169 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
<> 144:ef7eb2e8f9f7 170 * - 0 = opposite to SDO sampling edge
<> 144:ef7eb2e8f9f7 171 * - 1 = same as SDO sampling edge */
<> 144:ef7eb2e8f9f7 172 uint32_t baudrate; /* The expected baud rate. */
<> 144:ef7eb2e8f9f7 173 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
<> 144:ef7eb2e8f9f7 174 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
<> 144:ef7eb2e8f9f7 175 uint8_t wordSize; /* The size word size in number of bits. */
<> 144:ef7eb2e8f9f7 176 uint8_t Mode;
<> 144:ef7eb2e8f9f7 177 uint32_t event;
<> 144:ef7eb2e8f9f7 178 };
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 struct i2c_s {
<> 144:ef7eb2e8f9f7 181 uint32_t baudrate; /**< The expected baud rate. */
<> 144:ef7eb2e8f9f7 182 uint32_t I2cStatusFromInt;
<> 144:ef7eb2e8f9f7 183 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
<> 144:ef7eb2e8f9f7 184 uint8_t irqEnable; /**< IRQs to be enabled */
<> 144:ef7eb2e8f9f7 185 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
<> 144:ef7eb2e8f9f7 186 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
<> 144:ef7eb2e8f9f7 187 //queue_pt rxQueue; /**< The receive queue for the device instance. */
<> 144:ef7eb2e8f9f7 188 };
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 191 }
<> 144:ef7eb2e8f9f7 192 #endif
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #endif //OBJECTS_H_