Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file us_ticker_api.h
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a Timer driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-15 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup timer
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #include <stddef.h>
<> 144:ef7eb2e8f9f7 25 #include "timer.h"
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 #define US_TIMER TIMER0
<> 144:ef7eb2e8f9f7 28 #define US_TICKER TIMER1
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 static void us_timer_init(void);
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 static uint32_t us_ticker_int_counter = 0;
<> 144:ef7eb2e8f9f7 35 static volatile uint32_t msb_counter = 0;
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 void us_ticker_init(void)
<> 144:ef7eb2e8f9f7 38 {
<> 144:ef7eb2e8f9f7 39 if (!us_ticker_inited) {
<> 144:ef7eb2e8f9f7 40 us_timer_init();
<> 144:ef7eb2e8f9f7 41 }
<> 144:ef7eb2e8f9f7 42 }
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /*******************************************************************************
<> 144:ef7eb2e8f9f7 45 * Timer for us timing reference
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * Uptime counter for scheduling reference. It uses TIMER0.
<> 144:ef7eb2e8f9f7 48 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 144:ef7eb2e8f9f7 49 * which is why a software timer is required to get 32-bit word length.
<> 144:ef7eb2e8f9f7 50 ******************************************************************************/
<> 144:ef7eb2e8f9f7 51 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 144:ef7eb2e8f9f7 52 /* TODO - Add msb_counter rollover protection at 16 bits count? */
<> 144:ef7eb2e8f9f7 53 /* TODO - How is overflow handled? */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Timer 0 for free running time */
<> 144:ef7eb2e8f9f7 56 extern void us_timer_isr(void)
<> 144:ef7eb2e8f9f7 57 {
<> 144:ef7eb2e8f9f7 58 TIM0REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 59 msb_counter++;
<> 144:ef7eb2e8f9f7 60 }
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */
<> 144:ef7eb2e8f9f7 63 static void us_timer_init(void)
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 /* Enable the timer0 periphery clock */
<> 144:ef7eb2e8f9f7 66 CLOCK_ENABLE(CLOCK_TIMER0);
<> 144:ef7eb2e8f9f7 67 /* Enable the timer0 periphery clock */
<> 144:ef7eb2e8f9f7 68 CLOCK_ENABLE(CLOCK_TIMER1);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Timer init */
<> 144:ef7eb2e8f9f7 71 /* load timer value */
<> 144:ef7eb2e8f9f7 72 TIM0REG->LOAD = 0xFFFF;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* set timer prescale 32 (1 us), mode & enable */
<> 144:ef7eb2e8f9f7 75 TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 144:ef7eb2e8f9f7 76 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
<> 144:ef7eb2e8f9f7 77 (TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Ticker init */
<> 144:ef7eb2e8f9f7 80 /* load timer value */
<> 144:ef7eb2e8f9f7 81 TIM1REG->LOAD = 0xFFFF;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* set timer prescale 32 (1 us), mode & enable */
<> 144:ef7eb2e8f9f7 84 TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 144:ef7eb2e8f9f7 85 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Register & enable interrupt associated with the timer */
<> 144:ef7eb2e8f9f7 88 NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
<> 144:ef7eb2e8f9f7 89 NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Clear pending irqs */
<> 144:ef7eb2e8f9f7 92 NVIC_ClearPendingIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 93 NVIC_ClearPendingIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* Setup NVIC for timer */
<> 144:ef7eb2e8f9f7 96 NVIC_EnableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 97 NVIC_EnableIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */
<> 144:ef7eb2e8f9f7 103 uint32_t us_ticker_read()
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 uint32_t retval, tim0cval;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 if (!us_ticker_inited) {
<> 144:ef7eb2e8f9f7 108 us_timer_init();
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Get the current tick from the hw and sw timers */
<> 144:ef7eb2e8f9f7 112 tim0cval = TIM0REG->VALUE; /* read current time */
<> 144:ef7eb2e8f9f7 113 retval = (0xFFFF - tim0cval); /* subtract down count */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 NVIC_DisableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 116 if (TIM0REG->CONTROL.BITS.INT) {
<> 144:ef7eb2e8f9f7 117 TIM0REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 118 msb_counter++;
<> 144:ef7eb2e8f9f7 119 tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
<> 144:ef7eb2e8f9f7 120 retval = (0xFFFF - tim0cval);
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122 retval |= msb_counter << 16; /* add software bits */
<> 144:ef7eb2e8f9f7 123 NVIC_EnableIRQ(Tim0_IRQn);
<> 144:ef7eb2e8f9f7 124 return retval;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /*******************************************************************************
<> 144:ef7eb2e8f9f7 128 * Event Timer
<> 144:ef7eb2e8f9f7 129 *
<> 144:ef7eb2e8f9f7 130 * Schedules interrupts at given (32bit)us interval of time. It uses TIMER1.
<> 144:ef7eb2e8f9f7 131 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 144:ef7eb2e8f9f7 132 * which is why a software timer is required to get 32-bit word length.
<> 144:ef7eb2e8f9f7 133 *******************************************************************************/
<> 144:ef7eb2e8f9f7 134 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* TImer 1 disbale interrupt */
<> 144:ef7eb2e8f9f7 137 void us_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 /* Disable the TIMER1 interrupt */
<> 144:ef7eb2e8f9f7 140 TIM1REG->CONTROL.BITS.ENABLE = 0x0;
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* TImer 1 clear interrupt */
<> 144:ef7eb2e8f9f7 144 void us_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Clear the Ticker (TIMER1) interrupt */
<> 144:ef7eb2e8f9f7 147 TIM1REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Setting TImer 1 (ticker) */
<> 144:ef7eb2e8f9f7 151 inline static void ticker_set(uint32_t count)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 /* Disable TIMER1, load the new value, and re-enable */
<> 144:ef7eb2e8f9f7 154 TIM1REG->CONTROL.BITS.ENABLE = 0;
<> 144:ef7eb2e8f9f7 155 TIM1REG->LOAD = count;
<> 144:ef7eb2e8f9f7 156 TIM1REG->CONTROL.BITS.ENABLE = 1;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* TImer 1 - ticker ISR */
<> 144:ef7eb2e8f9f7 160 extern void us_ticker_isr(void)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 /* Clear IRQ flag */
<> 144:ef7eb2e8f9f7 163 TIM1REG->CLEAR = 0;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* If this is a longer timer it will take multiple full hw counter cycles */
<> 144:ef7eb2e8f9f7 166 if (us_ticker_int_counter > 0) {
<> 144:ef7eb2e8f9f7 167 ticker_set(0xFFFF);
<> 144:ef7eb2e8f9f7 168 us_ticker_int_counter--;
<> 144:ef7eb2e8f9f7 169 } else {
<> 144:ef7eb2e8f9f7 170 TIM1REG->CONTROL.BITS.ENABLE = False;
<> 144:ef7eb2e8f9f7 171 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Set timer 1 ticker interrupt */
<> 144:ef7eb2e8f9f7 176 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 int32_t delta = (uint32_t)timestamp - us_ticker_read();
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 if (delta <= 0) {
<> 144:ef7eb2e8f9f7 181 /* This event was in the past */
<> 144:ef7eb2e8f9f7 182 //us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 183 // This event was in the past.
<> 144:ef7eb2e8f9f7 184 // Set the interrupt as pending, but don't process it here.
<> 144:ef7eb2e8f9f7 185 // This prevents a recurive loop under heavy load
<> 144:ef7eb2e8f9f7 186 // which can lead to a stack overflow.
<> 144:ef7eb2e8f9f7 187 NVIC_SetPendingIRQ(Tim1_IRQn);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 return;
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Calculate how much delta falls outside the 16-bit counter range. */
<> 144:ef7eb2e8f9f7 193 /* You will have to perform a full timer overflow for each bit above */
<> 144:ef7eb2e8f9f7 194 /* that range. */
<> 144:ef7eb2e8f9f7 195 us_ticker_int_counter = (uint32_t)(delta >> 16);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 ticker_set(delta);
<> 144:ef7eb2e8f9f7 198 }