Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_spi.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file spi.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a IPC 7207 SPI master driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * @version $Rev: $
<> 144:ef7eb2e8f9f7 8 * @date $Date: 2016-02-05 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup spi
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 */
<> 144:ef7eb2e8f9f7 26 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #include "spi.h"
<> 144:ef7eb2e8f9f7 29 #include "clock.h"
<> 144:ef7eb2e8f9f7 30 #include "objects.h"
<> 144:ef7eb2e8f9f7 31 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 32 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 33 #include "spi_ipc7207_map.h"
<> 144:ef7eb2e8f9f7 34 #include "crossbar.h"
<> 144:ef7eb2e8f9f7 35 #include "pad.h"
<> 144:ef7eb2e8f9f7 36 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /** Initializes a spi device.
<> 144:ef7eb2e8f9f7 39 * @details
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 * @param obj A spi device instance.
<> 144:ef7eb2e8f9f7 42 * @param mosi pin to used as SPI MOSI
<> 144:ef7eb2e8f9f7 43 * @param miso pin to used as SPI MISO
<> 144:ef7eb2e8f9f7 44 * @param sclk pin to used as SPI SCLK
<> 144:ef7eb2e8f9f7 45 * @return None
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47 void fSpiInit(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 144:ef7eb2e8f9f7 48 {
<> 144:ef7eb2e8f9f7 49 uint32_t clockDivisor;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* determine the SPI to use */
<> 144:ef7eb2e8f9f7 52 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 53 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 54 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 55 SPIName spi_ssel = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 SPIName spi_data_1 = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 58 SPIName spi_data_2 = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 obj->membase = (SpiIpc7207Reg_pt)pinmap_merge(spi_data_1, spi_data_2);
<> 144:ef7eb2e8f9f7 61 MBED_ASSERT((int)obj->membase != NC);
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Check device to be activated */
<> 144:ef7eb2e8f9f7 64 if(obj->membase == SPI1REG) {
<> 144:ef7eb2e8f9f7 65 /* SPI 1 selected */
<> 144:ef7eb2e8f9f7 66 CLOCK_ENABLE(CLOCK_SPI); /* Enable clock */
<> 144:ef7eb2e8f9f7 67 } else {
<> 144:ef7eb2e8f9f7 68 /* SPI 2 selected */
<> 144:ef7eb2e8f9f7 69 CLOCK_ENABLE(CLOCK_SPI2); /* Enable clock */
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /* Cross bar setting: Map GPIOs to SPI */
<> 144:ef7eb2e8f9f7 73 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 74 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 75 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 76 pinmap_pinout(miso, PinMap_SPI_SSEL);/* TODO Need to implement as per morpheus */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* TODO Do we need GPIO direction settings done here or at init phase? */
<> 144:ef7eb2e8f9f7 79 /* GPIO config */
<> 144:ef7eb2e8f9f7 80 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 81 GPIOREG->W_OUT |= ((0x1 << sclk) | (0x1 << mosi)); /* Set pins as output */
<> 144:ef7eb2e8f9f7 82 GPIOREG->W_IN |= (0x1 << miso); /* Set pin as input */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 pin_mode(sclk, PushPullNoPull);
<> 144:ef7eb2e8f9f7 85 pin_mode(mosi, PushPullPullUp);
<> 144:ef7eb2e8f9f7 86 pin_mode(miso, OpenDrainPullUp);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* PAD drive strength */
<> 144:ef7eb2e8f9f7 89 PadReg_t *padRegOffset = (PadReg_t*)(PADREG_BASE + (sclk * PAD_REG_ADRS_BYTE_SIZE));
<> 144:ef7eb2e8f9f7 90 CLOCK_ENABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 91 padRegOffset->PADIO0.BITS.POWER = 1; /* sclk: Drive strength */
<> 144:ef7eb2e8f9f7 92 padRegOffset->PADIO1.BITS.POWER = 1; /* mosi: Drive strength */
<> 144:ef7eb2e8f9f7 93 padRegOffset->PADIO2.BITS.POWER = 1; /* miso: Drive strength */
<> 144:ef7eb2e8f9f7 94 CLOCK_DISABLE(CLOCK_PAD);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* disable/reset the spi port */
<> 144:ef7eb2e8f9f7 97 obj->membase->CONTROL.BITS.ENABLE = False;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* set default baud rate to 1MHz */
<> 144:ef7eb2e8f9f7 100 clockDivisor = ((fClockGetPeriphClockfrequency() / 1000000) >> 1) - 1;
<> 144:ef7eb2e8f9f7 101 obj->membase->FDIV = clockDivisor;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* set tx/rx fifos watermarks */ /* TODO water mark level 1 byte ?*/
<> 144:ef7eb2e8f9f7 104 obj->membase->TX_WATERMARK = 1;
<> 144:ef7eb2e8f9f7 105 obj->membase->RX_WATERMARK = 1;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /* DIsable and clear IRQs */ /* TODO sync api, do not need irq ?*/
<> 144:ef7eb2e8f9f7 108 obj->membase->IRQ_ENABLE = False;
<> 144:ef7eb2e8f9f7 109 obj->membase->IRQ_CLEAR = 0xFF; /* Clear all */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* configure slave select */
<> 144:ef7eb2e8f9f7 112 obj->membase->SLAVE_SELECT.BITS.SS_ENABLE = False;
<> 144:ef7eb2e8f9f7 113 obj->membase->SLAVE_SELECT.BITS.SS_BURST = True;
<> 144:ef7eb2e8f9f7 114 obj->membase->SLAVE_SELECT_POLARITY = False;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* set control register parameters */
<> 144:ef7eb2e8f9f7 117 obj->membase->CONTROL.BITS.WORD_WIDTH = False; /* 8 bits */
<> 144:ef7eb2e8f9f7 118 obj->membase->CONTROL.BITS.MODE = 1; /* master */
<> 144:ef7eb2e8f9f7 119 obj->membase->CONTROL.BITS.CPOL = 0; /* CPOL = 0, Idle low */
<> 144:ef7eb2e8f9f7 120 obj->membase->CONTROL.BITS.CPHA = 0; /* CPHA = 0, First transmit occurs before first edge of SCLK*/
<> 144:ef7eb2e8f9f7 121 obj->membase->CONTROL.BITS.ENDIAN = 0; /* Little endian */
<> 144:ef7eb2e8f9f7 122 obj->membase->CONTROL.BITS.SAMPLING_EDGE = False; /* Sample incoming data on opposite edge of SCLK from when outgoing data is driven */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /* SPI1REG->SLAVE_SELECT.BITS.SS_ENABLE = 0; Slave select TODO do we need? */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* enable the spi port */
<> 144:ef7eb2e8f9f7 127 obj->membase->CONTROL.BITS.ENABLE = True;
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** Close a spi device.
<> 144:ef7eb2e8f9f7 131 * @details
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * @param obj The spi device to close.
<> 144:ef7eb2e8f9f7 134 * @return None
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 void fSpiClose(spi_t *obj)
<> 144:ef7eb2e8f9f7 137 {
<> 144:ef7eb2e8f9f7 138 /* disable the spi port */
<> 144:ef7eb2e8f9f7 139 obj->membase->CONTROL.BITS.ENABLE = False;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* disable interruption associated with spi */
<> 144:ef7eb2e8f9f7 142 NVIC_DisableIRQ(obj->irq);
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * Write data to an SPI device.
<> 144:ef7eb2e8f9f7 147 * The data is written from the buffer into the transmit register.
<> 144:ef7eb2e8f9f7 148 * This function blocks untill write and read happens.
<> 144:ef7eb2e8f9f7 149 *
<> 144:ef7eb2e8f9f7 150 * @param obj The device to write to.
<> 144:ef7eb2e8f9f7 151 * @param buf The buffer to write from (the contents of the buffer may not be modified).
<> 144:ef7eb2e8f9f7 152 * @return the value received during send
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 int fSpiWriteB(spi_t *obj, uint32_t const buf)
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 int byte;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 while((obj->membase->STATUS.BITS.TX_FULL == 1) && (obj->membase->STATUS.BITS.RX_FULL == 1)); /* Wait till Tx/Rx status is full */
<> 144:ef7eb2e8f9f7 159 obj->membase->TX_DATA = buf;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 while (obj->membase->STATUS.BITS.RX_EMPTY == 1); /* Wait till Receive status is empty */
<> 144:ef7eb2e8f9f7 162 byte = obj->membase->RX_DATA;
<> 144:ef7eb2e8f9f7 163 return byte;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 #endif /* DEVICE_SPI */