Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c_ipc7208_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file i2c_ipc7208_map.h
<> 144:ef7eb2e8f9f7 4 * @brief I2C IPC 7208 HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3324 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-03-27 17:00:28 +0530 (Fri, 27 Mar 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup i2c_ipc7208
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * I2C IPC 7208 HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 29 * <p>
<> 144:ef7eb2e8f9f7 30 * <a href="../pdf/IPC7208_I2C_APB_DS_v1P3.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 31 * IPC7208 APB I2C Master Design Specification v1.3 </a>
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 36 #pragma anon_unions
<> 144:ef7eb2e8f9f7 37 #endif
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef I2C_IPC7208_MAP_H_
<> 144:ef7eb2e8f9f7 40 #define I2C_IPC7208_MAP_H_
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #include "architecture.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** I2C HW Structure Overlay */
<> 144:ef7eb2e8f9f7 45 typedef struct {
<> 144:ef7eb2e8f9f7 46 union {
<> 144:ef7eb2e8f9f7 47 struct {
<> 144:ef7eb2e8f9f7 48 __IO uint32_t CMD_FIFO_EMPTY :1; /**< 1 = Command FIFO is empty , 0 = Command FIFO is empty */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t RD_FIFO_NOT_EMPTY :1; /**< 0 = Read data is not ready , 1 = Read data is ready */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t I2C_BUS_ERR :1; /**< 0 = No buss error occurred , 1 = buss error */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t RD_FIFO_UFL :1; /**< 0 = Read data FIFO is not underflowed , 1 = Read data FIFO is underflowed */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t CMD_FIFO_OFL :1;/**< 0 = Command FIFO is not overflowed 1 = Command FIFO is overflowed */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t CMD_FIFO_FULL :1; /**< 0 = Command FIFO not full , 1 = Command FIFO full */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t PAD :2; /**< Reserved . Always reads back 0. */
<> 144:ef7eb2e8f9f7 55 } BITS;
<> 144:ef7eb2e8f9f7 56 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 57 } STATUS;
<> 144:ef7eb2e8f9f7 58 __IO uint32_t RD_FIFO_REG;/**< Data from the I2C Slave to be read by the processor. */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t CMD_REG; /**< I2C Command Programming interface */
<> 144:ef7eb2e8f9f7 60 union {
<> 144:ef7eb2e8f9f7 61 struct {
<> 144:ef7eb2e8f9f7 62 __IO uint32_t CMD_FIFO_INT :1; /**< Command FIFO empty interrupt : 0 = disable , 1 = enable */
<> 144:ef7eb2e8f9f7 63 __IO uint32_t RD_FIFO_INT :1; /**< Read Data FIFO Not Empty Interrupt : 0 = disable , 1 = enable */
<> 144:ef7eb2e8f9f7 64 __IO uint32_t I2C_ERR_INT :1; /**< I2C Error Interrupt : 0 = disable , 1 = enable */
<> 144:ef7eb2e8f9f7 65 // __IO uint32_t PAD :4; /**< Reserved. Writes have no effect; Read as 0x00. */
<> 144:ef7eb2e8f9f7 66 } BITS;
<> 144:ef7eb2e8f9f7 67 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 68 } IER;
<> 144:ef7eb2e8f9f7 69 union {
<> 144:ef7eb2e8f9f7 70 struct {
<> 144:ef7eb2e8f9f7 71 __IO uint32_t CD_VAL :5; /**< I2C APB Clock Divider Value (low 5 bits). */
<> 144:ef7eb2e8f9f7 72 __IO uint32_t I2C_APB_CD_EN :1; /**< 0 = I2C clock divider disable 1 = I2C clock divider enable */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t I2C_CLK_SRC :1; /**< I2C clock source : 0 = external clock , 1 = APB clock */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t I2C_MODULE_EN :1; /**< 0 = I2C disable , 1 = I2C enable */
<> 144:ef7eb2e8f9f7 75 } BITS;
<> 144:ef7eb2e8f9f7 76 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 77 } CR;
<> 144:ef7eb2e8f9f7 78 __IO uint32_t PRE_SCALE_REG; /* I2C APB Clock Divider Value (upper 8 bits). */
<> 144:ef7eb2e8f9f7 79 } I2cIpc7208Reg_t, *I2cIpc7208Reg_pt;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #endif /* I2C_IPC7208_MAP_H_ */