Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/i2c.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file i2c.h
<> 144:ef7eb2e8f9f7 4 * @brief (API) Public header of i2c driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: $
<> 144:ef7eb2e8f9f7 8 * $Date: 2016-04-20 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup i2c
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 25 #include "i2c_api.h"
<> 144:ef7eb2e8f9f7 26 #include "clock.h"
<> 144:ef7eb2e8f9f7 27 #include "i2c_ipc7208_map.h"
<> 144:ef7eb2e8f9f7 28 #include "memory_map.h"
<> 144:ef7eb2e8f9f7 29 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef I2C_H_
<> 144:ef7eb2e8f9f7 32 #define I2C_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /* Miscellaneous I/O and control operations codes */
<> 144:ef7eb2e8f9f7 35 #define I2C_IPC7208_IOCTL_NOT_ACK 0x03
<> 144:ef7eb2e8f9f7 36 #define I2C_IPC7208_IOCTL_NULL_CMD 0x04
<> 144:ef7eb2e8f9f7 37 #define I2C_IPC7208_IOCTL_ACK 0x05
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /* Definitions for the clock speed. */
<> 144:ef7eb2e8f9f7 40 #define I2C_SPEED_100K_AT_8MHZ (uint8_t)0x12
<> 144:ef7eb2e8f9f7 41 #define I2C_SPEED_100K_AT_16MHZ (uint8_t)0x26
<> 144:ef7eb2e8f9f7 42 #define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03
<> 144:ef7eb2e8f9f7 43 #define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* I2C commands */
<> 144:ef7eb2e8f9f7 47 #define I2C_CMD_NULL 0x00
<> 144:ef7eb2e8f9f7 48 #define I2C_CMD_WDAT0 0x10
<> 144:ef7eb2e8f9f7 49 #define I2C_CMD_WDAT1 0x11
<> 144:ef7eb2e8f9f7 50 #define I2C_CMD_WDAT8 0x12
<> 144:ef7eb2e8f9f7 51 #define I2C_CMD_RDAT8 0x13
<> 144:ef7eb2e8f9f7 52 #define I2C_CMD_STOP 0x14
<> 144:ef7eb2e8f9f7 53 #define I2C_CMD_START 0x15
<> 144:ef7eb2e8f9f7 54 #define I2C_CMD_VRFY_ACK 0x16
<> 144:ef7eb2e8f9f7 55 #define I2C_CMD_VRFY_VACK 0x17
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Status register bits */
<> 144:ef7eb2e8f9f7 58 #define I2C_STATUS_CMD_FIFO_MPTY_BIT 0x01
<> 144:ef7eb2e8f9f7 59 #define I2C_STATUS_RD_DATA_RDY_BIT 0x02
<> 144:ef7eb2e8f9f7 60 #define I2C_STATUS_BUS_ERR_BIT 0x04
<> 144:ef7eb2e8f9f7 61 #define I2C_STATUS_RD_DATA_UFL_BIT 0x08
<> 144:ef7eb2e8f9f7 62 #define I2C_STATUS_CMD_FIFO_OFL_BIT 0x10
<> 144:ef7eb2e8f9f7 63 #define I2C_STATUS_CMD_FIFO_FULL_BIT 0x20
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* I2C return status */
<> 144:ef7eb2e8f9f7 66 #define I2C_STATUS_INVALID 0xFF
<> 144:ef7eb2e8f9f7 67 #define I2C_STATUS_SUCCESS 0x00
<> 144:ef7eb2e8f9f7 68 #define I2C_STATUS_FAIL 0x01
<> 144:ef7eb2e8f9f7 69 #define I2C_STATUS_BUS_ERROR 0x02
<> 144:ef7eb2e8f9f7 70 #define I2C_STATUS_RD_DATA_UFL 0x03
<> 144:ef7eb2e8f9f7 71 #define I2C_STATUS_CMD_FIFO_OFL 0x04
<> 144:ef7eb2e8f9f7 72 #define I2C_STATUS_INTERRUPT_ERROR 0x05
<> 144:ef7eb2e8f9f7 73 #define I2C_STATUS_CMD_FIFO_EMPTY 0x06
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* I2C clock divider position */
<> 144:ef7eb2e8f9f7 76 #define I2C_CLOCKDIVEDER_VAL_MASK 0x1F
<> 144:ef7eb2e8f9f7 77 #define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /* Error check */
<> 144:ef7eb2e8f9f7 80 #define I2C_UFL_CHECK (d->membase->STATUS.WORD & 0x80)
<> 144:ef7eb2e8f9f7 81 #define FIFO_OFL_CHECK (d->membase->STATUS.WORD & 0x10)
<> 144:ef7eb2e8f9f7 82 #define I2C_BUS_ERR_CHECK (d->membase->STATUS.WORD & 0x04)
<> 144:ef7eb2e8f9f7 83 #define RD_DATA_READY (d->membase->STATUS.WORD & 0x02)
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #define I2C_API_STATUS_SUCCESS 0
<> 144:ef7eb2e8f9f7 86 #define PAD_REG_ADRS_BYTE_SIZE 4
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** Init I2C device.
<> 144:ef7eb2e8f9f7 89 * @details
<> 144:ef7eb2e8f9f7 90 * Sets the necessary registers. The baud rate is set default to 100K
<> 144:ef7eb2e8f9f7 91 *
<> 144:ef7eb2e8f9f7 92 * @param obj A I2C device instance.
<> 144:ef7eb2e8f9f7 93 * @param sda GPIO number for SDA line
<> 144:ef7eb2e8f9f7 94 * @param scl GPIO number for SCL line
<> 144:ef7eb2e8f9f7 95 * @return None
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 extern void fI2cInit(i2c_t *obj,PinName sda,PinName scl);
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** Set baud rate or frequency
<> 144:ef7eb2e8f9f7 100 * @details
<> 144:ef7eb2e8f9f7 101 * Sets user baudrate
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * @param obj A I2C device instance.
<> 144:ef7eb2e8f9f7 104 * @param hz User desired baud rate/frequency
<> 144:ef7eb2e8f9f7 105 * @return None
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 extern void fI2cFrequency(i2c_t *obj, uint32_t hz);
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** Sends start bit
<> 144:ef7eb2e8f9f7 110 * @details
<> 144:ef7eb2e8f9f7 111 * Sends start bit on i2c pins
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * @param obj A I2C device instance.
<> 144:ef7eb2e8f9f7 114 * @return status
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 extern int32_t fI2cStart(i2c_t *obj);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /** Sends stop bit
<> 144:ef7eb2e8f9f7 119 * @details
<> 144:ef7eb2e8f9f7 120 * Sends stop bit on i2c pins
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * @param obj A I2C device instance.
<> 144:ef7eb2e8f9f7 123 * @return status
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 extern int32_t fI2cStop(i2c_t *obj);
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** Reads data from a I2C device in blocking fashion.
<> 144:ef7eb2e8f9f7 128 * @details
<> 144:ef7eb2e8f9f7 129 * The data is read from the receive queue into the buffer. The receive queue is
<> 144:ef7eb2e8f9f7 130 * filled by the interrupt handler. If not enough data is available,
<> 144:ef7eb2e8f9f7 131 *
<> 144:ef7eb2e8f9f7 132 * @param d The device to read from.
<> 144:ef7eb2e8f9f7 133 * @param buf The buffer to read into (only the contents of the buffer may be modified, not the buffer itself).
<> 144:ef7eb2e8f9f7 134 * @param len The maximum number of bytes to read, typically the buffer length.
<> 144:ef7eb2e8f9f7 135 * @return On Success: The actual number of bytes read. On Failure: Failure code.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 extern int32_t fI2cReadB(i2c_t *d, char *buf, int len);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** Write data to an I2C device.
<> 144:ef7eb2e8f9f7 140 * @details
<> 144:ef7eb2e8f9f7 141 * The commands(I2C instructions) and data arrive at the I2C Engine via the Command FIFO.
<> 144:ef7eb2e8f9f7 142 * The command to write the data & data to be written is sent to command FIFO by writing it into command register.
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 * @param d The device to write to.
<> 144:ef7eb2e8f9f7 145 * @param buf The buffer to write from (the contents of the buffer may not be modified).
<> 144:ef7eb2e8f9f7 146 * @param len The number of bytes to write.
<> 144:ef7eb2e8f9f7 147 * @return On success: The actual number of bytes written. On Failure: Failure code
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #endif /* I2C_H_ */