Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/gpio_irq_api.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file gpio_irq_api.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a GPIO irq handlers
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev:
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-11-04 $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup gpio
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 *
<> 144:ef7eb2e8f9f7 25 * @internal
<> 144:ef7eb2e8f9f7 26 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 27 * <p>
<> 144:ef7eb2e8f9f7 28 * Reference document: IPC7203 APB GPIO Design Specification v1.2</a>
<> 144:ef7eb2e8f9f7 29 * </p>
<> 144:ef7eb2e8f9f7 30 * @endinternal
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 * <h1> Functional description (internal) </h1>
<> 144:ef7eb2e8f9f7 33 * <p>
<> 144:ef7eb2e8f9f7 34 * Each GPIO line can be independently programmed as an input or an output. Separate Set
<> 144:ef7eb2e8f9f7 35 * and Clear registers are provided since it is likely that different software tasks may be
<> 144:ef7eb2e8f9f7 36 * servicing different I/O signals. Inputs are synchronized to the system clock
<> 144:ef7eb2e8f9f7 37 * through a pair of flip-flops. Each input can be programmed
<> 144:ef7eb2e8f9f7 38 * to cause an interrupt to be generated. The interrupt can be programmed to be level-sensitive
<> 144:ef7eb2e8f9f7 39 * or edge-sensitive and the level (high or low) or edge (rising, falling or either) that causes
<> 144:ef7eb2e8f9f7 40 * the interrupt can be selected. Interrupts can be individually enabled or disabled.
<> 144:ef7eb2e8f9f7 41 * Level-sensitive interrupts stay asserted until the interrupting condition is cleared.
<> 144:ef7eb2e8f9f7 42 * Edge-triggered interrupts are cleared by writing to the GPIO interrupt clear register.
<> 144:ef7eb2e8f9f7 43 * </p>
<> 144:ef7eb2e8f9f7 44 *
<> 144:ef7eb2e8f9f7 45 * <h1> Use of GPIO driver in SW </h1>
<> 144:ef7eb2e8f9f7 46 * <p>
<> 144:ef7eb2e8f9f7 47 * The user of the GPIO driver should set the pin as GPIO, using crossbar.
<> 144:ef7eb2e8f9f7 48 * Init the GPIO and configure the mode and direction.This will return a device pointer. One device controls all GPIO's. It is not
<> 144:ef7eb2e8f9f7 49 * needed nor supported to create a device per GPIO.
<> 144:ef7eb2e8f9f7 50 * Next, the user should call the fGpioOpen function with the device and options as paramter.
<> 144:ef7eb2e8f9f7 51 * </p>
<> 144:ef7eb2e8f9f7 52 * <p>
<> 144:ef7eb2e8f9f7 53 * Use the device driver fGpioIoctl function to change the behavior of the GPIO's and to register an
<> 144:ef7eb2e8f9f7 54 * interrupt handler for each IO that has an interrupt enabled. There is one interrupt for all GPIO's.
<> 144:ef7eb2e8f9f7 55 * The GPIO driver will look up what IO caused the interrupt and call the respective interrupt handler.
<> 144:ef7eb2e8f9f7 56 * </p>
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #include "gpio.h"
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Include files from the mbed-hal layer */
<> 144:ef7eb2e8f9f7 64 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #include "device.h"
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #if DEVICE_INTERRUPTIN
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /* Handler for the GPIO pin */
<> 144:ef7eb2e8f9f7 71 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 72 static uint32_t gpioIds[NUMBER_OF_GPIO] = {0};
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** Main GPIO IRQ handler called from vector table handler
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * @param gpioBase The GPIO register base address
<> 144:ef7eb2e8f9f7 77 * @return void
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 void fGpioHandler(void)
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 uint8_t index;
<> 144:ef7eb2e8f9f7 82 uint32_t active_interrupts = 0;
<> 144:ef7eb2e8f9f7 83 gpio_irq_event event;
<> 144:ef7eb2e8f9f7 84 GpioReg_pt gpioBase;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 87 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 gpioBase = GPIOREG;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** - Store all active interrupts */
<> 144:ef7eb2e8f9f7 92 active_interrupts = gpioBase->R_IRQ_W_CLEAR;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 for (index=0; index < NUMBER_OF_GPIO; index++) {
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* Check the pin for which IRQ is raised */
<> 144:ef7eb2e8f9f7 97 if ((active_interrupts >> index) & 0x01) {
<> 144:ef7eb2e8f9f7 98 /* Check if it is edge triggered and clear the interrupt */
<> 144:ef7eb2e8f9f7 99 if ((gpioBase->IRQ_EDGE >> index) & 0x01) {
<> 144:ef7eb2e8f9f7 100 if ((gpioBase->IRQ_POLARITY_SET >> index) &0x01) {
<> 144:ef7eb2e8f9f7 101 /* Edge triggered high */
<> 144:ef7eb2e8f9f7 102 event = IRQ_RISE;
<> 144:ef7eb2e8f9f7 103 } else if ((gpioBase->IRQ_POLARITY_CLEAR >> index) &0x01) {
<> 144:ef7eb2e8f9f7 104 /* Edge triggered low */
<> 144:ef7eb2e8f9f7 105 event = IRQ_FALL;
<> 144:ef7eb2e8f9f7 106 } else {
<> 144:ef7eb2e8f9f7 107 /* Edge none */
<> 144:ef7eb2e8f9f7 108 event = IRQ_NONE;
<> 144:ef7eb2e8f9f7 109 }
<> 144:ef7eb2e8f9f7 110 }
<> 144:ef7eb2e8f9f7 111 gpioBase->IRQ_CLEAR |= (0x1 << index);
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Call the handler registered to the pin */
<> 144:ef7eb2e8f9f7 114 irq_handler(gpioIds[index], event);
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 }
<> 144:ef7eb2e8f9f7 118 }
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** Initialize the GPIO IRQ pin
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * @param obj The GPIO object to initialize
<> 144:ef7eb2e8f9f7 123 * @param pin The GPIO pin name
<> 144:ef7eb2e8f9f7 124 * @param handler The handler to be attached to GPIO IRQ
<> 144:ef7eb2e8f9f7 125 * @param id The object ID
<> 144:ef7eb2e8f9f7 126 * @return -1 if pin is NC, 0 otherwise
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 /* If Pin is not connected; then return -1 */
<> 144:ef7eb2e8f9f7 131 if (pin == NC) {
<> 144:ef7eb2e8f9f7 132 return(-1);
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Store the pin for which handler is registered */
<> 144:ef7eb2e8f9f7 136 obj->pin = pin;
<> 144:ef7eb2e8f9f7 137 obj->pinMask = (0x1 << pin);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Store the ID, this is required by registered handler function */
<> 144:ef7eb2e8f9f7 140 gpioIds[pin] = id;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 143 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* Initialize the GPIO membase */
<> 144:ef7eb2e8f9f7 146 obj->GPIOMEMBASE = GPIOREG;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Set default values for the pin interrupt */
<> 144:ef7eb2e8f9f7 149 /* TODO: Only one DIO line is configured using this function; overrides other DIO line setting
<> 144:ef7eb2e8f9f7 150 * If mbed layer wants to call this function repeatedly for setting multiple DIO lines as input
<> 144:ef7eb2e8f9f7 151 * then change this setting to obj->GPIOMEMBASE->W_IN |= obj->pinMask. All parameter setting needs to change from = to |=
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 obj->GPIOMEMBASE->W_IN = obj->pinMask;
<> 144:ef7eb2e8f9f7 154 obj->GPIOMEMBASE->IRQ_ENABLE_SET = obj->pinMask;
<> 144:ef7eb2e8f9f7 155 obj->GPIOMEMBASE->IRQ_EDGE = obj->pinMask;
<> 144:ef7eb2e8f9f7 156 obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
<> 144:ef7eb2e8f9f7 157 obj->GPIOMEMBASE->ANYEDGE_SET = IO_NONE;
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Register the handler for this pin */
<> 144:ef7eb2e8f9f7 160 irq_handler = handler;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Enable interruption associated with the gpio */
<> 144:ef7eb2e8f9f7 163 NVIC_ClearPendingIRQ(Gpio_IRQn);
<> 144:ef7eb2e8f9f7 164 NVIC_EnableIRQ(Gpio_IRQn);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 return(0);
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** Release the GPIO IRQ PIN
<> 144:ef7eb2e8f9f7 170 *
<> 144:ef7eb2e8f9f7 171 * @param obj The gpio object
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 void gpio_irq_free(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 176 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 obj->GPIOMEMBASE->W_IN = (IO_ALL ^ (obj->pinMask));
<> 144:ef7eb2e8f9f7 179 gpioIds[obj->pin] = 0;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** Enable/disable pin IRQ event
<> 144:ef7eb2e8f9f7 183 *
<> 144:ef7eb2e8f9f7 184 * @param obj The GPIO object
<> 144:ef7eb2e8f9f7 185 * @param event The GPIO IRQ event
<> 144:ef7eb2e8f9f7 186 * @param enable The enable flag
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 192 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 switch(event) {
<> 144:ef7eb2e8f9f7 195 case IRQ_RISE:
<> 144:ef7eb2e8f9f7 196 obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
<> 144:ef7eb2e8f9f7 197 obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
<> 144:ef7eb2e8f9f7 198 /* Enable is an integer; hence checking for 1 or 0*/
<> 144:ef7eb2e8f9f7 199 if (enable == 1) {
<> 144:ef7eb2e8f9f7 200 /* Enable rising edge */
<> 144:ef7eb2e8f9f7 201 obj->GPIOMEMBASE->IRQ_POLARITY_SET = (obj->pinMask);
<> 144:ef7eb2e8f9f7 202 } else if (enable == 0) {
<> 144:ef7eb2e8f9f7 203 /* Disable rising edge */
<> 144:ef7eb2e8f9f7 204 obj->GPIOMEMBASE->IRQ_POLARITY_SET = (IO_ALL ^ (obj->pinMask));
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206 break;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 case IRQ_FALL:
<> 144:ef7eb2e8f9f7 209 obj->GPIOMEMBASE->IRQ_EDGE = (obj->pinMask);
<> 144:ef7eb2e8f9f7 210 obj->GPIOMEMBASE->IRQ_LEVEL = (IO_ALL ^ (obj->pinMask));
<> 144:ef7eb2e8f9f7 211 /* Enable is an integer; hence checking for 1 or 0*/
<> 144:ef7eb2e8f9f7 212 if (enable == 1) {
<> 144:ef7eb2e8f9f7 213 /* Enable falling edge */
<> 144:ef7eb2e8f9f7 214 obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (obj->pinMask);
<> 144:ef7eb2e8f9f7 215 } else if (enable == 0) {
<> 144:ef7eb2e8f9f7 216 /* Disable falling edge */
<> 144:ef7eb2e8f9f7 217 obj->GPIOMEMBASE->IRQ_POLARITY_CLEAR = (IO_ALL ^ (obj->pinMask));
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219 break;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 default:
<> 144:ef7eb2e8f9f7 222 /* No event is set */
<> 144:ef7eb2e8f9f7 223 break;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** Enable GPIO IRQ
<> 144:ef7eb2e8f9f7 229 *
<> 144:ef7eb2e8f9f7 230 * This is target dependent, as it might enable the entire port or just a pin
<> 144:ef7eb2e8f9f7 231 * @param obj The GPIO object
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 void gpio_irq_enable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 236 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 obj->GPIOMEMBASE->IRQ_ENABLE_SET = (obj->pinMask);
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** Disable GPIO IRQ
<> 144:ef7eb2e8f9f7 242 *
<> 144:ef7eb2e8f9f7 243 * This is target dependent, as it might disable the entire port or just a pin
<> 144:ef7eb2e8f9f7 244 * @param obj The GPIO object
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 void gpio_irq_disable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 /* Enable the GPIO clock */
<> 144:ef7eb2e8f9f7 249 CLOCK_ENABLE(CLOCK_GPIO);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 obj->GPIOMEMBASE->IRQ_ENABLE_CLEAR = (obj->pinMask);
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #endif //DEVICE_INTERRUPTIN