Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/dma_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file dma_map.h
<> 144:ef7eb2e8f9f7 4 * @brief DMA hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3415 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-06-05 13:29:52 +0530 (Fri, 05 Jun 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup dma
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifndef DMA_MAP_H_
<> 144:ef7eb2e8f9f7 27 #define DMA_MAP_H_
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 30 * *
<> 144:ef7eb2e8f9f7 31 * Header files *
<> 144:ef7eb2e8f9f7 32 * *
<> 144:ef7eb2e8f9f7 33 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #include "architecture.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 * Type definitions *
<> 144:ef7eb2e8f9f7 40 * *
<> 144:ef7eb2e8f9f7 41 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** DMA control HW registers structure overlay */
<> 144:ef7eb2e8f9f7 44 #ifdef REVB
<> 144:ef7eb2e8f9f7 45 typedef struct {
<> 144:ef7eb2e8f9f7 46 __IO uint32_t CONTROL; /**< Write 1 to enable DMA, write 0 to disable */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t STATUS; /**< To be debined */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t INT_ENABLE; /**< Enable interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t INT_CLEAR_ENABLE; /**< Clear Interrupt source by writing 1. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 53 __I uint32_t INT_STATUS; /**< Current interrupt status. Bit 0: DMA done, Bit 1: Source Error, Bit 2: Destination Error */
<> 144:ef7eb2e8f9f7 54 } DmaReg_t, *DmaReg_pt;
<> 144:ef7eb2e8f9f7 55 #endif /* REVB */
<> 144:ef7eb2e8f9f7 56 #ifdef REVD
<> 144:ef7eb2e8f9f7 57 typedef struct {
<> 144:ef7eb2e8f9f7 58 union {
<> 144:ef7eb2e8f9f7 59 struct {
<> 144:ef7eb2e8f9f7 60 __IO uint32_t ENABLE:1; /**< DMA enable: 1 to enable; 0 to disable */
<> 144:ef7eb2e8f9f7 61 __IO uint32_t MODE :2; /**< DMA mode: 00 – Memory to memory; 01 – Memory to peripheral; 10 – Peripheral to memory; 11 – Peripheral to peripheral */
<> 144:ef7eb2e8f9f7 62 } BITS;
<> 144:ef7eb2e8f9f7 63 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 64 } CONTROL; /**< Control register */
<> 144:ef7eb2e8f9f7 65 __IO uint32_t SOURCE; /**< Address of source, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 66 __IO uint32_t DESTINATION; /**< Address of destination, read to get the number of bytes written */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t SIZE; /**< Lenght of the entire transfer */
<> 144:ef7eb2e8f9f7 68 union {
<> 144:ef7eb2e8f9f7 69 struct {
<> 144:ef7eb2e8f9f7 70 __I uint32_t COMPLETED:1; /**< Done: 0 – Not complete, 1 – Complete */
<> 144:ef7eb2e8f9f7 71 __I uint32_t SOURCE_ERROR:1; /**< Source Error: 0 – No Error, 1 – Error */
<> 144:ef7eb2e8f9f7 72 __I uint32_t DESTINATION_ERROR:1; /**< Destination Error: 0 – No Error, 1 – Source Error */
<> 144:ef7eb2e8f9f7 73 } BITS;
<> 144:ef7eb2e8f9f7 74 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 75 } STATUS; /**< Status register */
<> 144:ef7eb2e8f9f7 76 union {
<> 144:ef7eb2e8f9f7 77 struct {
<> 144:ef7eb2e8f9f7 78 __IO uint32_t COMPLETED:1; /**< A write of ‘1’ enables the interrupt generated by a DMA transfer complete */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t SOURCE_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the source side of the DMA transfer */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t DESTINATION_ERROR:1; /**< A write of ‘1’ enables the interrupt generated by an error on the destination side of the DMA transfer */
<> 144:ef7eb2e8f9f7 81 } BITS;
<> 144:ef7eb2e8f9f7 82 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 83 } INT_ENABLE; /**< Interrupt enable */
<> 144:ef7eb2e8f9f7 84 union {
<> 144:ef7eb2e8f9f7 85 struct {
<> 144:ef7eb2e8f9f7 86 __IO uint32_t COMPLETED:1; /**< A write clears the interrupt generated by a DMA transfer complete */
<> 144:ef7eb2e8f9f7 87 __IO uint32_t SOURCE_ERROR:1; /**< A write clears the interrupt generated by an error on the source side of the DMA transfer */
<> 144:ef7eb2e8f9f7 88 __IO uint32_t DESTINATION_ERROR:1; /**< A write clears the interrupt generated by an error on the destination side of the DMA transfer */
<> 144:ef7eb2e8f9f7 89 } BITS;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 91 } INT_CLEAR; /**< Interrupt clear */
<> 144:ef7eb2e8f9f7 92 union {
<> 144:ef7eb2e8f9f7 93 struct {
<> 144:ef7eb2e8f9f7 94 __I uint32_t COMPLETED:1; /**< Transfer complete interrupt */
<> 144:ef7eb2e8f9f7 95 __I uint32_t SOURCE_ERROR:1; /**< Source error interrupt */
<> 144:ef7eb2e8f9f7 96 __I uint32_t DESTINATION_ERROR:1; /**< Destination error interrupt */
<> 144:ef7eb2e8f9f7 97 } BITS;
<> 144:ef7eb2e8f9f7 98 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 99 } INT_STATUS; /**< Interrupt status */
<> 144:ef7eb2e8f9f7 100 } DmaReg_t, *DmaReg_pt;
<> 144:ef7eb2e8f9f7 101 #endif /* REVD */
<> 144:ef7eb2e8f9f7 102 #endif /* DMA_MAP_H_ */