Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file clock_map.h
<> 144:ef7eb2e8f9f7 4 * @brief CLOCK hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2848 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup clock
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifndef CLOCK_MAP_H_
<> 144:ef7eb2e8f9f7 27 #define CLOCK_MAP_H_
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 30 * *
<> 144:ef7eb2e8f9f7 31 * Header files *
<> 144:ef7eb2e8f9f7 32 * *
<> 144:ef7eb2e8f9f7 33 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #include "architecture.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 * Type definitions *
<> 144:ef7eb2e8f9f7 40 * *
<> 144:ef7eb2e8f9f7 41 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** Clock control HW structure overlay */
<> 144:ef7eb2e8f9f7 44 typedef struct {
<> 144:ef7eb2e8f9f7 45 union {
<> 144:ef7eb2e8f9f7 46 struct {
<> 144:ef7eb2e8f9f7 47 __IO uint32_t OSC_SEL:1;
<> 144:ef7eb2e8f9f7 48 __IO uint32_t PAD0:1;
<> 144:ef7eb2e8f9f7 49 __IO uint32_t CAL32K:1;
<> 144:ef7eb2e8f9f7 50 __IO uint32_t CAL32M:1;
<> 144:ef7eb2e8f9f7 51 __IO uint32_t RTCEN:1;
<> 144:ef7eb2e8f9f7 52 } BITS;
<> 144:ef7eb2e8f9f7 53 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 54 } CCR; /**< 0x4001B000 Clock control register */
<> 144:ef7eb2e8f9f7 55 union {
<> 144:ef7eb2e8f9f7 56 struct {
<> 144:ef7eb2e8f9f7 57 __I uint32_t XTAL32M:1;
<> 144:ef7eb2e8f9f7 58 __I uint32_t XTAL32K:1;
<> 144:ef7eb2e8f9f7 59 __I uint32_t CAL32K:1;
<> 144:ef7eb2e8f9f7 60 __I uint32_t DONE32K:1;
<> 144:ef7eb2e8f9f7 61 __I uint32_t CAL32MFAIL:1;
<> 144:ef7eb2e8f9f7 62 __I uint32_t CAL32MDONE:1;
<> 144:ef7eb2e8f9f7 63 } BITS;
<> 144:ef7eb2e8f9f7 64 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 65 } CSR; /**< 0x4001B004 Clock status register */
<> 144:ef7eb2e8f9f7 66 union {
<> 144:ef7eb2e8f9f7 67 struct {
<> 144:ef7eb2e8f9f7 68 __IO uint32_t IE32K:1;
<> 144:ef7eb2e8f9f7 69 __IO uint32_t IE32M:1;
<> 144:ef7eb2e8f9f7 70 } BITS;
<> 144:ef7eb2e8f9f7 71 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 72 } IER; /**< 0x4001B008 Interrup enable register */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
<> 144:ef7eb2e8f9f7 74 union {
<> 144:ef7eb2e8f9f7 75 struct {
<> 144:ef7eb2e8f9f7 76 __IO uint32_t TIMER0:1;
<> 144:ef7eb2e8f9f7 77 __IO uint32_t TIMER1:1;
<> 144:ef7eb2e8f9f7 78 __IO uint32_t TIMER2:1;
<> 144:ef7eb2e8f9f7 79 __IO uint32_t PAD0:2;
<> 144:ef7eb2e8f9f7 80 __IO uint32_t UART1:1;
<> 144:ef7eb2e8f9f7 81 __IO uint32_t SPI:1;
<> 144:ef7eb2e8f9f7 82 __IO uint32_t I2C:1;
<> 144:ef7eb2e8f9f7 83 __IO uint32_t UART2:1;
<> 144:ef7eb2e8f9f7 84 __IO uint32_t PAD1:1;
<> 144:ef7eb2e8f9f7 85 __IO uint32_t WDOG:1;
<> 144:ef7eb2e8f9f7 86 __IO uint32_t PWM:1;
<> 144:ef7eb2e8f9f7 87 __IO uint32_t GPIO:1;
<> 144:ef7eb2e8f9f7 88 __IO uint32_t PAD2:2;
<> 144:ef7eb2e8f9f7 89 __IO uint32_t RTC:1;
<> 144:ef7eb2e8f9f7 90 __IO uint32_t XBAR:1;
<> 144:ef7eb2e8f9f7 91 __IO uint32_t RAND:1;
<> 144:ef7eb2e8f9f7 92 __IO uint32_t PAD3:2;
<> 144:ef7eb2e8f9f7 93 __IO uint32_t MACHW:1;
<> 144:ef7eb2e8f9f7 94 __IO uint32_t ADC:1;
<> 144:ef7eb2e8f9f7 95 __IO uint32_t AES:1;
<> 144:ef7eb2e8f9f7 96 __IO uint32_t FLASH:1;
<> 144:ef7eb2e8f9f7 97 __IO uint32_t PAD4:1;
<> 144:ef7eb2e8f9f7 98 __IO uint32_t RFANA:1;
<> 144:ef7eb2e8f9f7 99 __IO uint32_t IO:1;
<> 144:ef7eb2e8f9f7 100 __IO uint32_t PAD5:1;
<> 144:ef7eb2e8f9f7 101 __IO uint32_t PAD:1;
<> 144:ef7eb2e8f9f7 102 __IO uint32_t PMU:1;
<> 144:ef7eb2e8f9f7 103 __IO uint32_t PAD6:1;
<> 144:ef7eb2e8f9f7 104 __IO uint32_t TEST:1;
<> 144:ef7eb2e8f9f7 105 } BITS;
<> 144:ef7eb2e8f9f7 106 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 107 } PDIS; /**< 0x4001B010 Periphery disable */
<> 144:ef7eb2e8f9f7 108 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
<> 144:ef7eb2e8f9f7 109 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
<> 144:ef7eb2e8f9f7 110 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
<> 144:ef7eb2e8f9f7 111 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
<> 144:ef7eb2e8f9f7 112 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
<> 144:ef7eb2e8f9f7 113 __IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
<> 144:ef7eb2e8f9f7 114 __IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
<> 144:ef7eb2e8f9f7 115 union {
<> 144:ef7eb2e8f9f7 116 struct {
<> 144:ef7eb2e8f9f7 117 __IO uint32_t OV32M;
<> 144:ef7eb2e8f9f7 118 __IO uint32_t EN32M;
<> 144:ef7eb2e8f9f7 119 __IO uint32_t OV32K;
<> 144:ef7eb2e8f9f7 120 __IO uint32_t EN32K;
<> 144:ef7eb2e8f9f7 121 } BITS;
<> 144:ef7eb2e8f9f7 122 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 123 } CER; /**< 0x4001B038 clock enable register*/
<> 144:ef7eb2e8f9f7 124 } ClockReg_t, *ClockReg_pt;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #endif /* CLOCK_MAP_H_ */