added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file aes_map.h
<> 144:ef7eb2e8f9f7 4 * @brief AES HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev: 2110 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup aes
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * AES HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 */
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 30 #pragma anon_unions
<> 144:ef7eb2e8f9f7 31 #endif
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef AES_MAP_H_
<> 144:ef7eb2e8f9f7 34 #define AES_MAP_H_
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "architecture.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /** AES Encryption HW Structure Overlay */
<> 144:ef7eb2e8f9f7 39 typedef struct {
<> 144:ef7eb2e8f9f7 40 __IO uint32_t KEY0; /**< Bits[31:00] of the 128-bit key */
<> 144:ef7eb2e8f9f7 41 __IO uint32_t KEY1; /**< Bits[63:32] of the 128-bit key */
<> 144:ef7eb2e8f9f7 42 __IO uint32_t KEY2; /**< Bits[95:64] of the 128-bit key */
<> 144:ef7eb2e8f9f7 43 __IO uint32_t KEY3; /**< Bits[127:96] of the 128-bit key */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t KEY4; /**< Bits[159:128] of the 256-bit key */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t KEY5; /**< Bits[191:160] of the 256-bit key */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t KEY6; /**< Bits[223:192] of the 256-bit key */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t KEY7; /**< Bits[255:224] of the 256-bit key */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 __IO uint32_t CNTi0; /**< Bits[31:00] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t CNTi1; /**< Bits[63:32] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t CNTi2; /**< Bits[95:64] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t CNTi3; /**< Bits[127:96] of the 128-bit counter value used in counter mode */
<> 144:ef7eb2e8f9f7 53 __I uint32_t CNTo0; /**< Bits[31:00] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 54 __I uint32_t CNTo1; /**< Bits[63:32] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 55 __I uint32_t CNTo2; /**< Bits[95:64] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 56 __I uint32_t CNTo3; /**< Bits[127:96] of the 128-bit counter result */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 __I uint32_t CBCo0; /**< Bits[31:00] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 59 __I uint32_t CBCo1; /**< Bits[63:32] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 60 __I uint32_t CBCo2; /**< Bits[95:64] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 61 __I uint32_t CBCo3; /**< Bits[127:96] of the 128-bit CBC result */
<> 144:ef7eb2e8f9f7 62 union {
<> 144:ef7eb2e8f9f7 63 struct {
<> 144:ef7eb2e8f9f7 64 __O uint32_t START:1; /**< start the encryption : 0 = no-effect , 1 = enable */
<> 144:ef7eb2e8f9f7 65 __O uint32_t ACC_CLR:1; /**< Clear the CBC accumulator : 0 = no-effect 1 = clears the CBC accumulator */
<> 144:ef7eb2e8f9f7 66 __O uint32_t INT_CLEAR:1; /**< interrupt clear : 0 = no-effect 1 = clear the interrupt */
<> 144:ef7eb2e8f9f7 67 __O uint32_t KEY_LENGTH:1; /**< Key Length: 0 = 128 Bit Encryption 1 = 256 Bit Encryption */
<> 144:ef7eb2e8f9f7 68 } BITS;
<> 144:ef7eb2e8f9f7 69 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 70 } CTL;
<> 144:ef7eb2e8f9f7 71 union {
<> 144:ef7eb2e8f9f7 72 struct {
<> 144:ef7eb2e8f9f7 73 __IO uint32_t CBC_MODE:1; /**< counter mode : 0 = counter mode , 1 = CBC mode */
<> 144:ef7eb2e8f9f7 74 __IO uint32_t BYPASS:1; /**< encryption : 0 = Normal Mode , 1 = Bypasss any encryption */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t INT_EN:1; /**< interrupt mask : 0 = disabled 1 = enabled */
<> 144:ef7eb2e8f9f7 76 } BITS;
<> 144:ef7eb2e8f9f7 77 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 78 } MODE;
<> 144:ef7eb2e8f9f7 79 union {
<> 144:ef7eb2e8f9f7 80 struct {
<> 144:ef7eb2e8f9f7 81 __I uint32_t COMPLETE:1;/**< status : 0 = not complete , 1 = complete */
<> 144:ef7eb2e8f9f7 82 } BITS;
<> 144:ef7eb2e8f9f7 83 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 84 } STAT;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 __O uint32_t MAC_INIT0; /**< Bits[31:00] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 87 __O uint32_t MAC_INIT1; /**< Bits[63:32] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 88 __O uint32_t MAC_INIT2; /**< Bits[95:64] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 89 __O uint32_t MAC_INIT3; /**< Bits[127:96] of the CBC Initialization Vector */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 __IO uint32_t RESERVED;
<> 144:ef7eb2e8f9f7 92 __O uint32_t DATA0; /**< Bits[31:00] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 93 __O uint32_t DATA1; /**< Bits[63:32] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 94 __O uint32_t DATA2; /**< Bits[95:64] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 95 __O uint32_t DATA3; /**< Bits[127:96] of the 128-bit data to encrypt */
<> 144:ef7eb2e8f9f7 96 } AesReg_t, *AesReg_pt;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 #endif /* AES_MAP_H_ */