Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/twi/twi.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
107:414e9c822e99 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 107:414e9c822e99 1 /**
mbed_official 107:414e9c822e99 2 * \file
mbed_official 107:414e9c822e99 3 *
mbed_official 107:414e9c822e99 4 * \brief Two-Wire Interface (TWI) driver for SAM.
mbed_official 107:414e9c822e99 5 *
mbed_official 107:414e9c822e99 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
mbed_official 107:414e9c822e99 7 *
mbed_official 107:414e9c822e99 8 * \asf_license_start
mbed_official 107:414e9c822e99 9 *
mbed_official 107:414e9c822e99 10 * \page License
mbed_official 107:414e9c822e99 11 *
mbed_official 107:414e9c822e99 12 * Redistribution and use in source and binary forms, with or without
mbed_official 107:414e9c822e99 13 * modification, are permitted provided that the following conditions are met:
mbed_official 107:414e9c822e99 14 *
mbed_official 107:414e9c822e99 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 107:414e9c822e99 16 * this list of conditions and the following disclaimer.
mbed_official 107:414e9c822e99 17 *
mbed_official 107:414e9c822e99 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 107:414e9c822e99 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 107:414e9c822e99 20 * and/or other materials provided with the distribution.
mbed_official 107:414e9c822e99 21 *
mbed_official 107:414e9c822e99 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 107:414e9c822e99 23 * from this software without specific prior written permission.
mbed_official 107:414e9c822e99 24 *
mbed_official 107:414e9c822e99 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 107:414e9c822e99 26 * Atmel microcontroller product.
mbed_official 107:414e9c822e99 27 *
mbed_official 107:414e9c822e99 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 107:414e9c822e99 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 107:414e9c822e99 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 107:414e9c822e99 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 107:414e9c822e99 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 107:414e9c822e99 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 107:414e9c822e99 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 107:414e9c822e99 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 107:414e9c822e99 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 107:414e9c822e99 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 107:414e9c822e99 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 107:414e9c822e99 39 *
mbed_official 107:414e9c822e99 40 * \asf_license_stop
mbed_official 107:414e9c822e99 41 *
mbed_official 107:414e9c822e99 42 */
mbed_official 107:414e9c822e99 43 /*
mbed_official 107:414e9c822e99 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 107:414e9c822e99 45 */
mbed_official 107:414e9c822e99 46
mbed_official 107:414e9c822e99 47 #include "twi.h"
mbed_official 107:414e9c822e99 48
mbed_official 107:414e9c822e99 49 /// @cond 0
mbed_official 107:414e9c822e99 50 /**INDENT-OFF**/
mbed_official 107:414e9c822e99 51 #ifdef __cplusplus
mbed_official 107:414e9c822e99 52 extern "C" {
mbed_official 107:414e9c822e99 53 #endif
mbed_official 107:414e9c822e99 54 /**INDENT-ON**/
mbed_official 107:414e9c822e99 55 /// @endcond
mbed_official 107:414e9c822e99 56
mbed_official 107:414e9c822e99 57 /**
mbed_official 107:414e9c822e99 58 * \defgroup sam_drivers_twi_group Two-Wire Interface (TWI)
mbed_official 107:414e9c822e99 59 *
mbed_official 107:414e9c822e99 60 * Driver for the TWI (Two-Wire Interface). This driver provides access to the main
mbed_official 107:414e9c822e99 61 * features of the TWI controller.
mbed_official 107:414e9c822e99 62 * The TWI interconnects components on a unique two-wire bus.
mbed_official 107:414e9c822e99 63 * The TWI is programmable as a master or a slave with sequential or single-byte access.
mbed_official 107:414e9c822e99 64 * Multiple master capability is supported.
mbed_official 107:414e9c822e99 65 *
mbed_official 107:414e9c822e99 66 * \par Usage
mbed_official 107:414e9c822e99 67 *
mbed_official 107:414e9c822e99 68 * -# Enable the TWI peripheral clock in the PMC.
mbed_official 107:414e9c822e99 69 * -# Enable the required TWI PIOs (see pio.h).
mbed_official 107:414e9c822e99 70 * -# Enable TWI master mode by calling twi_enable_master_mode if it is a master on the I2C bus.
mbed_official 107:414e9c822e99 71 * -# Configure the TWI in master mode by calling twi_master_init.
mbed_official 107:414e9c822e99 72 * -# Send data to a slave device on the I2C bus by calling twi_master_write.
mbed_official 107:414e9c822e99 73 * -# Receive data from a slave device on the I2C bus by calling the twi_master_read.
mbed_official 107:414e9c822e99 74 * -# Enable TWI slave mode by calling twi_enable_slave_mode if it is a slave on the I2C bus.
mbed_official 107:414e9c822e99 75 * -# Configure the TWI in slave mode by calling twi_slave_init.
mbed_official 107:414e9c822e99 76 *
mbed_official 107:414e9c822e99 77 * @{
mbed_official 107:414e9c822e99 78 */
mbed_official 107:414e9c822e99 79
mbed_official 107:414e9c822e99 80 #define I2C_FAST_MODE_SPEED 400000
mbed_official 107:414e9c822e99 81 #define TWI_CLK_DIVIDER 2
mbed_official 107:414e9c822e99 82 #define TWI_CLK_CALC_ARGU 4
mbed_official 107:414e9c822e99 83 #define TWI_CLK_DIV_MAX 0xFF
mbed_official 107:414e9c822e99 84 #define TWI_CLK_DIV_MIN 7
mbed_official 107:414e9c822e99 85
mbed_official 107:414e9c822e99 86 #define TWI_WP_KEY_VALUE TWI_WPMR_WPKEY_PASSWD
mbed_official 107:414e9c822e99 87
mbed_official 107:414e9c822e99 88 /**
mbed_official 107:414e9c822e99 89 * \brief Enable TWI master mode.
mbed_official 107:414e9c822e99 90 *
mbed_official 107:414e9c822e99 91 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 92 */
mbed_official 107:414e9c822e99 93 void twi_enable_master_mode(Twi *p_twi)
mbed_official 107:414e9c822e99 94 {
mbed_official 107:414e9c822e99 95 /* Set Master Disable bit and Slave Disable bit */
mbed_official 107:414e9c822e99 96 p_twi->TWI_CR = TWI_CR_MSDIS;
mbed_official 107:414e9c822e99 97 p_twi->TWI_CR = TWI_CR_SVDIS;
mbed_official 107:414e9c822e99 98
mbed_official 107:414e9c822e99 99 /* Set Master Enable bit */
mbed_official 107:414e9c822e99 100 p_twi->TWI_CR = TWI_CR_MSEN;
mbed_official 107:414e9c822e99 101 }
mbed_official 107:414e9c822e99 102
mbed_official 107:414e9c822e99 103 /**
mbed_official 107:414e9c822e99 104 * \brief Disable TWI master mode.
mbed_official 107:414e9c822e99 105 *
mbed_official 107:414e9c822e99 106 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 107 */
mbed_official 107:414e9c822e99 108 void twi_disable_master_mode(Twi *p_twi)
mbed_official 107:414e9c822e99 109 {
mbed_official 107:414e9c822e99 110 /* Set Master Disable bit */
mbed_official 107:414e9c822e99 111 p_twi->TWI_CR = TWI_CR_MSDIS;
mbed_official 107:414e9c822e99 112 }
mbed_official 107:414e9c822e99 113
mbed_official 107:414e9c822e99 114 /**
mbed_official 107:414e9c822e99 115 * \brief Initialize TWI master mode.
mbed_official 107:414e9c822e99 116 *
mbed_official 107:414e9c822e99 117 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 118 * \param p_opt Options for initializing the TWI module (see \ref twi_options_t).
mbed_official 107:414e9c822e99 119 *
mbed_official 107:414e9c822e99 120 * \return TWI_SUCCESS if initialization is complete, error code otherwise.
mbed_official 107:414e9c822e99 121 */
mbed_official 107:414e9c822e99 122 uint32_t twi_master_init(Twi *p_twi, const twi_options_t *p_opt)
mbed_official 107:414e9c822e99 123 {
mbed_official 107:414e9c822e99 124 uint32_t status = TWI_SUCCESS;
mbed_official 107:414e9c822e99 125
mbed_official 107:414e9c822e99 126 /* Disable TWI interrupts */
mbed_official 107:414e9c822e99 127 p_twi->TWI_IDR = ~0UL;
mbed_official 107:414e9c822e99 128
mbed_official 107:414e9c822e99 129 /* Dummy read in status register */
mbed_official 107:414e9c822e99 130 p_twi->TWI_SR;
mbed_official 107:414e9c822e99 131
mbed_official 107:414e9c822e99 132 /* Reset TWI peripheral */
mbed_official 107:414e9c822e99 133 twi_reset(p_twi);
mbed_official 107:414e9c822e99 134
mbed_official 107:414e9c822e99 135 twi_enable_master_mode(p_twi);
mbed_official 107:414e9c822e99 136
mbed_official 107:414e9c822e99 137 /* Select the speed */
mbed_official 107:414e9c822e99 138 if (twi_set_speed(p_twi, p_opt->speed, p_opt->master_clk) == FAIL) {
mbed_official 107:414e9c822e99 139 /* The desired speed setting is rejected */
mbed_official 107:414e9c822e99 140 status = TWI_INVALID_ARGUMENT;
mbed_official 107:414e9c822e99 141 }
mbed_official 107:414e9c822e99 142
mbed_official 107:414e9c822e99 143 if (p_opt->smbus == 1) {
mbed_official 107:414e9c822e99 144 p_twi->TWI_CR = TWI_CR_QUICK;
mbed_official 107:414e9c822e99 145 }
mbed_official 107:414e9c822e99 146
mbed_official 107:414e9c822e99 147 return status;
mbed_official 107:414e9c822e99 148 }
mbed_official 107:414e9c822e99 149
mbed_official 107:414e9c822e99 150 /**
mbed_official 107:414e9c822e99 151 * \brief Set the I2C bus speed in conjunction with the clock frequency.
mbed_official 107:414e9c822e99 152 *
mbed_official 107:414e9c822e99 153 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 154 * \param ul_speed The desired I2C bus speed (in Hz).
mbed_official 107:414e9c822e99 155 * \param ul_mck Main clock of the device (in Hz).
mbed_official 107:414e9c822e99 156 *
mbed_official 107:414e9c822e99 157 * \retval PASS New speed setting is accepted.
mbed_official 107:414e9c822e99 158 * \retval FAIL New speed setting is rejected.
mbed_official 107:414e9c822e99 159 */
mbed_official 107:414e9c822e99 160 uint32_t twi_set_speed(Twi *p_twi, uint32_t ul_speed, uint32_t ul_mck)
mbed_official 107:414e9c822e99 161 {
mbed_official 107:414e9c822e99 162 uint32_t ckdiv = 0;
mbed_official 107:414e9c822e99 163 uint32_t c_lh_div;
mbed_official 107:414e9c822e99 164
mbed_official 107:414e9c822e99 165 if (ul_speed > I2C_FAST_MODE_SPEED) {
mbed_official 107:414e9c822e99 166 return FAIL;
mbed_official 107:414e9c822e99 167 }
mbed_official 107:414e9c822e99 168
mbed_official 107:414e9c822e99 169 c_lh_div = ul_mck / (ul_speed * TWI_CLK_DIVIDER) - TWI_CLK_CALC_ARGU;
mbed_official 107:414e9c822e99 170
mbed_official 107:414e9c822e99 171 /* cldiv must fit in 8 bits, ckdiv must fit in 3 bits */
mbed_official 107:414e9c822e99 172 while ((c_lh_div > TWI_CLK_DIV_MAX) && (ckdiv < TWI_CLK_DIV_MIN)) {
mbed_official 107:414e9c822e99 173 /* Increase clock divider */
mbed_official 107:414e9c822e99 174 ckdiv++;
mbed_official 107:414e9c822e99 175 /* Divide cldiv value */
mbed_official 107:414e9c822e99 176 c_lh_div /= TWI_CLK_DIVIDER;
mbed_official 107:414e9c822e99 177 }
mbed_official 107:414e9c822e99 178
mbed_official 107:414e9c822e99 179 /* set clock waveform generator register */
mbed_official 107:414e9c822e99 180 p_twi->TWI_CWGR =
mbed_official 107:414e9c822e99 181 TWI_CWGR_CLDIV(c_lh_div) | TWI_CWGR_CHDIV(c_lh_div) |
mbed_official 107:414e9c822e99 182 TWI_CWGR_CKDIV(ckdiv);
mbed_official 107:414e9c822e99 183
mbed_official 107:414e9c822e99 184 return PASS;
mbed_official 107:414e9c822e99 185 }
mbed_official 107:414e9c822e99 186
mbed_official 107:414e9c822e99 187 /**
mbed_official 107:414e9c822e99 188 * \brief Test if a chip answers a given I2C address.
mbed_official 107:414e9c822e99 189 *
mbed_official 107:414e9c822e99 190 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 191 * \param uc_slave_addr Address of the remote chip to search for.
mbed_official 107:414e9c822e99 192 *
mbed_official 107:414e9c822e99 193 * \return TWI_SUCCESS if a chip was found, error code otherwise.
mbed_official 107:414e9c822e99 194 */
mbed_official 107:414e9c822e99 195 uint32_t twi_probe(Twi *p_twi, uint8_t uc_slave_addr)
mbed_official 107:414e9c822e99 196 {
mbed_official 107:414e9c822e99 197 twi_packet_t packet;
mbed_official 107:414e9c822e99 198 uint8_t data = 0;
mbed_official 107:414e9c822e99 199
mbed_official 107:414e9c822e99 200 /* Data to send */
mbed_official 107:414e9c822e99 201 packet.buffer = &data;
mbed_official 107:414e9c822e99 202 /* Data length */
mbed_official 107:414e9c822e99 203 packet.length = 1;
mbed_official 107:414e9c822e99 204 /* Slave chip address */
mbed_official 107:414e9c822e99 205 packet.chip = (uint32_t) uc_slave_addr;
mbed_official 107:414e9c822e99 206 /* Internal chip address */
mbed_official 107:414e9c822e99 207 packet.addr[0] = 0;
mbed_official 107:414e9c822e99 208 /* Address length */
mbed_official 107:414e9c822e99 209 packet.addr_length = 0;
mbed_official 107:414e9c822e99 210
mbed_official 107:414e9c822e99 211 /* Perform a master write access */
mbed_official 107:414e9c822e99 212 return (twi_master_write(p_twi, &packet));
mbed_official 107:414e9c822e99 213 }
mbed_official 107:414e9c822e99 214
mbed_official 107:414e9c822e99 215
mbed_official 107:414e9c822e99 216 /**
mbed_official 107:414e9c822e99 217 * \internal
mbed_official 107:414e9c822e99 218 * \brief Construct the TWI module address register field
mbed_official 107:414e9c822e99 219 *
mbed_official 107:414e9c822e99 220 * The TWI module address register is sent out MSB first. And the size controls
mbed_official 107:414e9c822e99 221 * which byte is the MSB to start with.
mbed_official 107:414e9c822e99 222 *
mbed_official 107:414e9c822e99 223 * Please see the device datasheet for details on this.
mbed_official 107:414e9c822e99 224 */
mbed_official 107:414e9c822e99 225 static uint32_t twi_mk_addr(const uint8_t *addr, int len)
mbed_official 107:414e9c822e99 226 {
mbed_official 107:414e9c822e99 227 uint32_t val;
mbed_official 107:414e9c822e99 228
mbed_official 107:414e9c822e99 229 if (len == 0)
mbed_official 107:414e9c822e99 230 return 0;
mbed_official 107:414e9c822e99 231
mbed_official 107:414e9c822e99 232 val = addr[0];
mbed_official 107:414e9c822e99 233 if (len > 1) {
mbed_official 107:414e9c822e99 234 val <<= 8;
mbed_official 107:414e9c822e99 235 val |= addr[1];
mbed_official 107:414e9c822e99 236 }
mbed_official 107:414e9c822e99 237 if (len > 2) {
mbed_official 107:414e9c822e99 238 val <<= 8;
mbed_official 107:414e9c822e99 239 val |= addr[2];
mbed_official 107:414e9c822e99 240 }
mbed_official 107:414e9c822e99 241 return val;
mbed_official 107:414e9c822e99 242 }
mbed_official 107:414e9c822e99 243
mbed_official 107:414e9c822e99 244 /**
mbed_official 107:414e9c822e99 245 * \brief Read multiple bytes from a TWI compatible slave device.
mbed_official 107:414e9c822e99 246 *
mbed_official 107:414e9c822e99 247 * \note This function will NOT return until all data has been read or error occurs.
mbed_official 107:414e9c822e99 248 *
mbed_official 107:414e9c822e99 249 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 250 * \param p_packet Packet information and data (see \ref twi_packet_t).
mbed_official 107:414e9c822e99 251 *
mbed_official 107:414e9c822e99 252 * \return TWI_SUCCESS if all bytes were read, error code otherwise.
mbed_official 107:414e9c822e99 253 */
mbed_official 107:414e9c822e99 254 uint32_t twi_master_read(Twi *p_twi, twi_packet_t *p_packet)
mbed_official 107:414e9c822e99 255 {
mbed_official 107:414e9c822e99 256 uint32_t status;
mbed_official 107:414e9c822e99 257 uint32_t cnt = p_packet->length;
mbed_official 107:414e9c822e99 258 uint8_t *buffer = p_packet->buffer;
mbed_official 107:414e9c822e99 259 uint8_t stop_sent = 0;
mbed_official 107:414e9c822e99 260 uint32_t timeout = TWI_TIMEOUT;;
mbed_official 107:414e9c822e99 261
mbed_official 107:414e9c822e99 262 /* Check argument */
mbed_official 107:414e9c822e99 263 if (cnt == 0) {
mbed_official 107:414e9c822e99 264 return TWI_INVALID_ARGUMENT;
mbed_official 107:414e9c822e99 265 }
mbed_official 107:414e9c822e99 266
mbed_official 107:414e9c822e99 267 /* Set read mode, slave address and 3 internal address byte lengths */
mbed_official 107:414e9c822e99 268 p_twi->TWI_MMR = 0;
mbed_official 107:414e9c822e99 269 p_twi->TWI_MMR = TWI_MMR_MREAD | TWI_MMR_DADR(p_packet->chip) |
mbed_official 107:414e9c822e99 270 ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
mbed_official 107:414e9c822e99 271 TWI_MMR_IADRSZ_Msk);
mbed_official 107:414e9c822e99 272
mbed_official 107:414e9c822e99 273 /* Set internal address for remote chip */
mbed_official 107:414e9c822e99 274 p_twi->TWI_IADR = 0;
mbed_official 107:414e9c822e99 275 p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
mbed_official 107:414e9c822e99 276
mbed_official 107:414e9c822e99 277 /* Send a START condition */
mbed_official 107:414e9c822e99 278 if (cnt == 1) {
mbed_official 107:414e9c822e99 279 p_twi->TWI_CR = TWI_CR_START | TWI_CR_STOP;
mbed_official 107:414e9c822e99 280 stop_sent = 1;
mbed_official 107:414e9c822e99 281 } else {
mbed_official 107:414e9c822e99 282 p_twi->TWI_CR = TWI_CR_START;
mbed_official 107:414e9c822e99 283 stop_sent = 0;
mbed_official 107:414e9c822e99 284 }
mbed_official 107:414e9c822e99 285
mbed_official 107:414e9c822e99 286 while (cnt > 0) {
mbed_official 107:414e9c822e99 287 status = p_twi->TWI_SR;
mbed_official 107:414e9c822e99 288 if (status & TWI_SR_NACK) {
mbed_official 107:414e9c822e99 289 return TWI_RECEIVE_NACK;
mbed_official 107:414e9c822e99 290 }
mbed_official 107:414e9c822e99 291
mbed_official 107:414e9c822e99 292 if (!timeout--) {
mbed_official 107:414e9c822e99 293 return TWI_ERROR_TIMEOUT;
mbed_official 107:414e9c822e99 294 }
mbed_official 107:414e9c822e99 295
mbed_official 107:414e9c822e99 296 /* Last byte ? */
mbed_official 107:414e9c822e99 297 if (cnt == 1 && !stop_sent) {
mbed_official 107:414e9c822e99 298 p_twi->TWI_CR = TWI_CR_STOP;
mbed_official 107:414e9c822e99 299 stop_sent = 1;
mbed_official 107:414e9c822e99 300 }
mbed_official 107:414e9c822e99 301
mbed_official 107:414e9c822e99 302 if (!(status & TWI_SR_RXRDY)) {
mbed_official 107:414e9c822e99 303 continue;
mbed_official 107:414e9c822e99 304 }
mbed_official 107:414e9c822e99 305 *buffer++ = p_twi->TWI_RHR;
mbed_official 107:414e9c822e99 306
mbed_official 107:414e9c822e99 307 cnt--;
mbed_official 107:414e9c822e99 308 timeout = TWI_TIMEOUT;
mbed_official 107:414e9c822e99 309 }
mbed_official 107:414e9c822e99 310
mbed_official 107:414e9c822e99 311 while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
mbed_official 107:414e9c822e99 312 }
mbed_official 107:414e9c822e99 313
mbed_official 107:414e9c822e99 314 p_twi->TWI_SR;
mbed_official 107:414e9c822e99 315
mbed_official 107:414e9c822e99 316 return TWI_SUCCESS;
mbed_official 107:414e9c822e99 317 }
mbed_official 107:414e9c822e99 318
mbed_official 107:414e9c822e99 319 /**
mbed_official 107:414e9c822e99 320 * \brief Write multiple bytes to a TWI compatible slave device.
mbed_official 107:414e9c822e99 321 *
mbed_official 107:414e9c822e99 322 * \note This function will NOT return until all data has been written or error occurred.
mbed_official 107:414e9c822e99 323 *
mbed_official 107:414e9c822e99 324 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 325 * \param p_packet Packet information and data (see \ref twi_packet_t).
mbed_official 107:414e9c822e99 326 *
mbed_official 107:414e9c822e99 327 * \return TWI_SUCCESS if all bytes were written, error code otherwise.
mbed_official 107:414e9c822e99 328 */
mbed_official 107:414e9c822e99 329 uint32_t twi_master_write(Twi *p_twi, twi_packet_t *p_packet)
mbed_official 107:414e9c822e99 330 {
mbed_official 107:414e9c822e99 331 uint32_t status;
mbed_official 107:414e9c822e99 332 uint32_t cnt = p_packet->length;
mbed_official 107:414e9c822e99 333 uint8_t *buffer = p_packet->buffer;
mbed_official 107:414e9c822e99 334
mbed_official 107:414e9c822e99 335 /* Check argument */
mbed_official 107:414e9c822e99 336 if (cnt == 0) {
mbed_official 107:414e9c822e99 337 return TWI_INVALID_ARGUMENT;
mbed_official 107:414e9c822e99 338 }
mbed_official 107:414e9c822e99 339
mbed_official 107:414e9c822e99 340 /* Set write mode, slave address and 3 internal address byte lengths */
mbed_official 107:414e9c822e99 341 p_twi->TWI_MMR = 0;
mbed_official 107:414e9c822e99 342 p_twi->TWI_MMR = TWI_MMR_DADR(p_packet->chip) |
mbed_official 107:414e9c822e99 343 ((p_packet->addr_length << TWI_MMR_IADRSZ_Pos) &
mbed_official 107:414e9c822e99 344 TWI_MMR_IADRSZ_Msk);
mbed_official 107:414e9c822e99 345
mbed_official 107:414e9c822e99 346 /* Set internal address for remote chip */
mbed_official 107:414e9c822e99 347 p_twi->TWI_IADR = 0;
mbed_official 107:414e9c822e99 348 p_twi->TWI_IADR = twi_mk_addr(p_packet->addr, p_packet->addr_length);
mbed_official 107:414e9c822e99 349
mbed_official 107:414e9c822e99 350 /* Send all bytes */
mbed_official 107:414e9c822e99 351 while (cnt > 0) {
mbed_official 107:414e9c822e99 352 status = p_twi->TWI_SR;
mbed_official 107:414e9c822e99 353 if (status & TWI_SR_NACK) {
mbed_official 107:414e9c822e99 354 return TWI_RECEIVE_NACK;
mbed_official 107:414e9c822e99 355 }
mbed_official 107:414e9c822e99 356
mbed_official 107:414e9c822e99 357 if (!(status & TWI_SR_TXRDY)) {
mbed_official 107:414e9c822e99 358 continue;
mbed_official 107:414e9c822e99 359 }
mbed_official 107:414e9c822e99 360 p_twi->TWI_THR = *buffer++;
mbed_official 107:414e9c822e99 361
mbed_official 107:414e9c822e99 362 cnt--;
mbed_official 107:414e9c822e99 363 }
mbed_official 107:414e9c822e99 364
mbed_official 107:414e9c822e99 365 while (1) {
mbed_official 107:414e9c822e99 366 status = p_twi->TWI_SR;
mbed_official 107:414e9c822e99 367 if (status & TWI_SR_NACK) {
mbed_official 107:414e9c822e99 368 return TWI_RECEIVE_NACK;
mbed_official 107:414e9c822e99 369 }
mbed_official 107:414e9c822e99 370
mbed_official 107:414e9c822e99 371 if (status & TWI_SR_TXRDY) {
mbed_official 107:414e9c822e99 372 break;
mbed_official 107:414e9c822e99 373 }
mbed_official 107:414e9c822e99 374 }
mbed_official 107:414e9c822e99 375
mbed_official 107:414e9c822e99 376 p_twi->TWI_CR = TWI_CR_STOP;
mbed_official 107:414e9c822e99 377
mbed_official 107:414e9c822e99 378 while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) {
mbed_official 107:414e9c822e99 379 }
mbed_official 107:414e9c822e99 380
mbed_official 107:414e9c822e99 381 return TWI_SUCCESS;
mbed_official 107:414e9c822e99 382 }
mbed_official 107:414e9c822e99 383
mbed_official 107:414e9c822e99 384 /**
mbed_official 107:414e9c822e99 385 * \brief Enable TWI interrupts.
mbed_official 107:414e9c822e99 386 *
mbed_official 107:414e9c822e99 387 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 388 * \param ul_sources Interrupts to be enabled.
mbed_official 107:414e9c822e99 389 */
mbed_official 107:414e9c822e99 390 void twi_enable_interrupt(Twi *p_twi, uint32_t ul_sources)
mbed_official 107:414e9c822e99 391 {
mbed_official 107:414e9c822e99 392 /* Enable the specified interrupts */
mbed_official 107:414e9c822e99 393 p_twi->TWI_IER = ul_sources;
mbed_official 107:414e9c822e99 394 }
mbed_official 107:414e9c822e99 395
mbed_official 107:414e9c822e99 396 /**
mbed_official 107:414e9c822e99 397 * \brief Disable TWI interrupts.
mbed_official 107:414e9c822e99 398 *
mbed_official 107:414e9c822e99 399 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 400 * \param ul_sources Interrupts to be disabled.
mbed_official 107:414e9c822e99 401 */
mbed_official 107:414e9c822e99 402 void twi_disable_interrupt(Twi *p_twi, uint32_t ul_sources)
mbed_official 107:414e9c822e99 403 {
mbed_official 107:414e9c822e99 404 /* Disable the specified interrupts */
mbed_official 107:414e9c822e99 405 p_twi->TWI_IDR = ul_sources;
mbed_official 107:414e9c822e99 406 /* Dummy read */
mbed_official 107:414e9c822e99 407 p_twi->TWI_SR;
mbed_official 107:414e9c822e99 408 }
mbed_official 107:414e9c822e99 409
mbed_official 107:414e9c822e99 410 /**
mbed_official 107:414e9c822e99 411 * \brief Get TWI interrupt status.
mbed_official 107:414e9c822e99 412 *
mbed_official 107:414e9c822e99 413 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 414 *
mbed_official 107:414e9c822e99 415 * \retval TWI interrupt status.
mbed_official 107:414e9c822e99 416 */
mbed_official 107:414e9c822e99 417 uint32_t twi_get_interrupt_status(Twi *p_twi)
mbed_official 107:414e9c822e99 418 {
mbed_official 107:414e9c822e99 419 return p_twi->TWI_SR;
mbed_official 107:414e9c822e99 420 }
mbed_official 107:414e9c822e99 421
mbed_official 107:414e9c822e99 422 /**
mbed_official 107:414e9c822e99 423 * \brief Read TWI interrupt mask.
mbed_official 107:414e9c822e99 424 *
mbed_official 107:414e9c822e99 425 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 426 *
mbed_official 107:414e9c822e99 427 * \return The interrupt mask value.
mbed_official 107:414e9c822e99 428 */
mbed_official 107:414e9c822e99 429 uint32_t twi_get_interrupt_mask(Twi *p_twi)
mbed_official 107:414e9c822e99 430 {
mbed_official 107:414e9c822e99 431 return p_twi->TWI_IMR;
mbed_official 107:414e9c822e99 432 }
mbed_official 107:414e9c822e99 433
mbed_official 107:414e9c822e99 434 /**
mbed_official 107:414e9c822e99 435 * \brief Reads a byte from the TWI bus.
mbed_official 107:414e9c822e99 436 *
mbed_official 107:414e9c822e99 437 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 438 *
mbed_official 107:414e9c822e99 439 * \return The byte read.
mbed_official 107:414e9c822e99 440 */
mbed_official 107:414e9c822e99 441 uint8_t twi_read_byte(Twi *p_twi)
mbed_official 107:414e9c822e99 442 {
mbed_official 107:414e9c822e99 443 return p_twi->TWI_RHR;
mbed_official 107:414e9c822e99 444 }
mbed_official 107:414e9c822e99 445
mbed_official 107:414e9c822e99 446 /**
mbed_official 107:414e9c822e99 447 * \brief Sends a byte of data to one of the TWI slaves on the bus.
mbed_official 107:414e9c822e99 448 *
mbed_official 107:414e9c822e99 449 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 450 * \param byte The byte to send.
mbed_official 107:414e9c822e99 451 */
mbed_official 107:414e9c822e99 452 void twi_write_byte(Twi *p_twi, uint8_t uc_byte)
mbed_official 107:414e9c822e99 453 {
mbed_official 107:414e9c822e99 454 p_twi->TWI_THR = uc_byte;
mbed_official 107:414e9c822e99 455 }
mbed_official 107:414e9c822e99 456
mbed_official 107:414e9c822e99 457 /**
mbed_official 107:414e9c822e99 458 * \brief Enable TWI slave mode.
mbed_official 107:414e9c822e99 459 *
mbed_official 107:414e9c822e99 460 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 461 */
mbed_official 107:414e9c822e99 462 void twi_enable_slave_mode(Twi *p_twi)
mbed_official 107:414e9c822e99 463 {
mbed_official 107:414e9c822e99 464 /* Set Master Disable bit and Slave Disable bit */
mbed_official 107:414e9c822e99 465 p_twi->TWI_CR = TWI_CR_MSDIS;
mbed_official 107:414e9c822e99 466 p_twi->TWI_CR = TWI_CR_SVDIS;
mbed_official 107:414e9c822e99 467
mbed_official 107:414e9c822e99 468 /* Set Slave Enable bit */
mbed_official 107:414e9c822e99 469 p_twi->TWI_CR = TWI_CR_SVEN;
mbed_official 107:414e9c822e99 470 }
mbed_official 107:414e9c822e99 471
mbed_official 107:414e9c822e99 472 /**
mbed_official 107:414e9c822e99 473 * \brief Disable TWI slave mode.
mbed_official 107:414e9c822e99 474 *
mbed_official 107:414e9c822e99 475 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 476 */
mbed_official 107:414e9c822e99 477 void twi_disable_slave_mode(Twi *p_twi)
mbed_official 107:414e9c822e99 478 {
mbed_official 107:414e9c822e99 479 /* Set Slave Disable bit */
mbed_official 107:414e9c822e99 480 p_twi->TWI_CR = TWI_CR_SVDIS;
mbed_official 107:414e9c822e99 481 }
mbed_official 107:414e9c822e99 482
mbed_official 107:414e9c822e99 483 /**
mbed_official 107:414e9c822e99 484 * \brief Initialize TWI slave mode.
mbed_official 107:414e9c822e99 485 *
mbed_official 107:414e9c822e99 486 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 487 * \param ul_device_addr Device address of the SAM slave device on the I2C bus.
mbed_official 107:414e9c822e99 488 */
mbed_official 107:414e9c822e99 489 void twi_slave_init(Twi *p_twi, uint32_t ul_device_addr)
mbed_official 107:414e9c822e99 490 {
mbed_official 107:414e9c822e99 491 /* Disable TWI interrupts */
mbed_official 107:414e9c822e99 492 p_twi->TWI_IDR = ~0UL;
mbed_official 107:414e9c822e99 493 p_twi->TWI_SR;
mbed_official 107:414e9c822e99 494
mbed_official 107:414e9c822e99 495 /* Reset TWI */
mbed_official 107:414e9c822e99 496 twi_reset(p_twi);
mbed_official 107:414e9c822e99 497
mbed_official 107:414e9c822e99 498 /* Set slave address in slave mode */
mbed_official 107:414e9c822e99 499 p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
mbed_official 107:414e9c822e99 500
mbed_official 107:414e9c822e99 501 /* Enable slave mode */
mbed_official 107:414e9c822e99 502 twi_enable_slave_mode(p_twi);
mbed_official 107:414e9c822e99 503 }
mbed_official 107:414e9c822e99 504
mbed_official 107:414e9c822e99 505 /**
mbed_official 107:414e9c822e99 506 * \brief Set TWI slave address.
mbed_official 107:414e9c822e99 507 *
mbed_official 107:414e9c822e99 508 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 509 * \param ul_device_addr Device address of the SAM slave device on the I2C bus.
mbed_official 107:414e9c822e99 510 */
mbed_official 107:414e9c822e99 511 void twi_set_slave_addr(Twi *p_twi, uint32_t ul_device_addr)
mbed_official 107:414e9c822e99 512 {
mbed_official 107:414e9c822e99 513 /* Set slave address */
mbed_official 107:414e9c822e99 514 p_twi->TWI_SMR = TWI_SMR_SADR(ul_device_addr);
mbed_official 107:414e9c822e99 515 }
mbed_official 107:414e9c822e99 516
mbed_official 107:414e9c822e99 517 /**
mbed_official 107:414e9c822e99 518 * \brief Read data from master.
mbed_official 107:414e9c822e99 519 *
mbed_official 107:414e9c822e99 520 * \note This function will NOT return until master sends a STOP condition.
mbed_official 107:414e9c822e99 521 *
mbed_official 107:414e9c822e99 522 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 523 * \param p_data Pointer to the data buffer where data received will be stored.
mbed_official 107:414e9c822e99 524 *
mbed_official 107:414e9c822e99 525 * \return Number of bytes read.
mbed_official 107:414e9c822e99 526 */
mbed_official 107:414e9c822e99 527 uint32_t twi_slave_read(Twi *p_twi, uint8_t *p_data)
mbed_official 107:414e9c822e99 528 {
mbed_official 107:414e9c822e99 529 uint32_t status, cnt = 0;
mbed_official 107:414e9c822e99 530
mbed_official 107:414e9c822e99 531 do {
mbed_official 107:414e9c822e99 532 status = p_twi->TWI_SR;
mbed_official 107:414e9c822e99 533 if (status & TWI_SR_SVACC) {
mbed_official 107:414e9c822e99 534 if (!(status & TWI_SR_GACC) &&
mbed_official 107:414e9c822e99 535 ((status & (TWI_SR_SVREAD | TWI_SR_RXRDY))
mbed_official 107:414e9c822e99 536 == (TWI_SR_SVREAD | TWI_SR_RXRDY))) {
mbed_official 107:414e9c822e99 537 *p_data++ = (uint8_t) p_twi->TWI_RHR;
mbed_official 107:414e9c822e99 538 cnt++;
mbed_official 107:414e9c822e99 539 }
mbed_official 107:414e9c822e99 540 } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
mbed_official 107:414e9c822e99 541 == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
mbed_official 107:414e9c822e99 542 break;
mbed_official 107:414e9c822e99 543 }
mbed_official 107:414e9c822e99 544 } while (1);
mbed_official 107:414e9c822e99 545
mbed_official 107:414e9c822e99 546 return cnt;
mbed_official 107:414e9c822e99 547 }
mbed_official 107:414e9c822e99 548
mbed_official 107:414e9c822e99 549 /**
mbed_official 107:414e9c822e99 550 * \brief Write data to TWI bus.
mbed_official 107:414e9c822e99 551 *
mbed_official 107:414e9c822e99 552 * \note This function will NOT return until master sends a STOP condition.
mbed_official 107:414e9c822e99 553 *
mbed_official 107:414e9c822e99 554 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 555 * \param p_data Pointer to the data buffer to be sent.
mbed_official 107:414e9c822e99 556 *
mbed_official 107:414e9c822e99 557 * \return Number of bytes written.
mbed_official 107:414e9c822e99 558 */
mbed_official 107:414e9c822e99 559 uint32_t twi_slave_write(Twi *p_twi, uint8_t *p_data)
mbed_official 107:414e9c822e99 560 {
mbed_official 107:414e9c822e99 561 uint32_t status, cnt = 0;
mbed_official 107:414e9c822e99 562
mbed_official 107:414e9c822e99 563 do {
mbed_official 107:414e9c822e99 564 status = p_twi->TWI_SR;
mbed_official 107:414e9c822e99 565 if (status & TWI_SR_SVACC) {
mbed_official 107:414e9c822e99 566 if (!(status & (TWI_SR_GACC | TWI_SR_SVREAD)) &&
mbed_official 107:414e9c822e99 567 (status & TWI_SR_TXRDY)) {
mbed_official 107:414e9c822e99 568 p_twi->TWI_THR = *p_data++;
mbed_official 107:414e9c822e99 569 cnt++;
mbed_official 107:414e9c822e99 570 }
mbed_official 107:414e9c822e99 571 } else if ((status & (TWI_SR_EOSACC | TWI_SR_TXCOMP))
mbed_official 107:414e9c822e99 572 == (TWI_SR_EOSACC | TWI_SR_TXCOMP)) {
mbed_official 107:414e9c822e99 573 break;
mbed_official 107:414e9c822e99 574 }
mbed_official 107:414e9c822e99 575 } while (1);
mbed_official 107:414e9c822e99 576
mbed_official 107:414e9c822e99 577 return cnt;
mbed_official 107:414e9c822e99 578 }
mbed_official 107:414e9c822e99 579
mbed_official 107:414e9c822e99 580 /**
mbed_official 107:414e9c822e99 581 * \brief Reset TWI.
mbed_official 107:414e9c822e99 582 *
mbed_official 107:414e9c822e99 583 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 584 */
mbed_official 107:414e9c822e99 585 void twi_reset(Twi *p_twi)
mbed_official 107:414e9c822e99 586 {
mbed_official 107:414e9c822e99 587 /* Set SWRST bit to reset TWI peripheral */
mbed_official 107:414e9c822e99 588 p_twi->TWI_CR = TWI_CR_SWRST;
mbed_official 107:414e9c822e99 589 p_twi->TWI_RHR;
mbed_official 107:414e9c822e99 590 }
mbed_official 107:414e9c822e99 591
mbed_official 107:414e9c822e99 592 /**
mbed_official 107:414e9c822e99 593 * \brief Get TWI PDC base address.
mbed_official 107:414e9c822e99 594 *
mbed_official 107:414e9c822e99 595 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 596 *
mbed_official 107:414e9c822e99 597 * \return TWI PDC registers base for PDC driver to access.
mbed_official 107:414e9c822e99 598 */
mbed_official 107:414e9c822e99 599 Pdc *twi_get_pdc_base(Twi *p_twi)
mbed_official 107:414e9c822e99 600 {
mbed_official 107:414e9c822e99 601 Pdc *p_pdc_base = NULL;
mbed_official 107:414e9c822e99 602 #if !SAMG
mbed_official 107:414e9c822e99 603 if (p_twi == TWI0) {
mbed_official 107:414e9c822e99 604 p_pdc_base = PDC_TWI0;
mbed_official 107:414e9c822e99 605 } else
mbed_official 107:414e9c822e99 606 #endif
mbed_official 107:414e9c822e99 607 #ifdef PDC_TWI1
mbed_official 107:414e9c822e99 608 if (p_twi == TWI1) {
mbed_official 107:414e9c822e99 609 p_pdc_base = PDC_TWI1;
mbed_official 107:414e9c822e99 610 } else
mbed_official 107:414e9c822e99 611 #endif
mbed_official 107:414e9c822e99 612 #ifdef PDC_TWI2
mbed_official 107:414e9c822e99 613 if (p_twi == TWI2) {
mbed_official 107:414e9c822e99 614 p_pdc_base = PDC_TWI2;
mbed_official 107:414e9c822e99 615 } else
mbed_official 107:414e9c822e99 616 #endif
mbed_official 107:414e9c822e99 617 {
mbed_official 107:414e9c822e99 618 Assert(false);
mbed_official 107:414e9c822e99 619 }
mbed_official 107:414e9c822e99 620
mbed_official 107:414e9c822e99 621 return p_pdc_base;
mbed_official 107:414e9c822e99 622 }
mbed_official 107:414e9c822e99 623
mbed_official 107:414e9c822e99 624 #if (SAM4E || SAM4C || SAMG || SAM4CP || SAM4CM)
mbed_official 107:414e9c822e99 625 /**
mbed_official 107:414e9c822e99 626 * \brief Enables/Disables write protection mode.
mbed_official 107:414e9c822e99 627 *
mbed_official 107:414e9c822e99 628 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 629 * \param flag ture for enable, false for disable.
mbed_official 107:414e9c822e99 630 */
mbed_official 107:414e9c822e99 631 void twi_set_write_protection(Twi *p_twi, bool flag)
mbed_official 107:414e9c822e99 632 {
mbed_official 107:414e9c822e99 633
mbed_official 107:414e9c822e99 634 p_twi->TWI_WPMR = (flag ? TWI_WPMR_WPEN : 0) | TWI_WP_KEY_VALUE;
mbed_official 107:414e9c822e99 635 }
mbed_official 107:414e9c822e99 636
mbed_official 107:414e9c822e99 637 /**
mbed_official 107:414e9c822e99 638 * \brief Read the write protection status.
mbed_official 107:414e9c822e99 639 *
mbed_official 107:414e9c822e99 640 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 641 * \param p_status Pointer to save the status.
mbed_official 107:414e9c822e99 642 */
mbed_official 107:414e9c822e99 643 void twi_read_write_protection_status(Twi *p_twi, uint32_t *p_status)
mbed_official 107:414e9c822e99 644 {
mbed_official 107:414e9c822e99 645
mbed_official 107:414e9c822e99 646 *p_status = p_twi->TWI_WPSR;
mbed_official 107:414e9c822e99 647 }
mbed_official 107:414e9c822e99 648 #endif
mbed_official 107:414e9c822e99 649
mbed_official 107:414e9c822e99 650 #if SAMG55
mbed_official 107:414e9c822e99 651 /**
mbed_official 107:414e9c822e99 652 * \brief Set the prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles for SMBUS mode.
mbed_official 107:414e9c822e99 653 *
mbed_official 107:414e9c822e99 654 * \param p_twi Base address of the TWI instance.
mbed_official 107:414e9c822e99 655 * \param ul_timing Parameter for prescaler, TLOW:SEXT, TLOW:MEXT and clock high max cycles.
mbed_official 107:414e9c822e99 656 */
mbed_official 107:414e9c822e99 657 void twi_smbus_set_timing(Twi *p_twi, uint32_t ul_timing)
mbed_official 107:414e9c822e99 658 {
mbed_official 107:414e9c822e99 659 p_twi->TWI_SMBTR = ul_timing;;
mbed_official 107:414e9c822e99 660 }
mbed_official 107:414e9c822e99 661
mbed_official 107:414e9c822e99 662 /**
mbed_official 107:414e9c822e99 663 * \brief Set length/direction/PEC for alternative command mode.
mbed_official 107:414e9c822e99 664 *
mbed_official 107:414e9c822e99 665 * \param p_twi Base address of the TWI instance.
mbed_official 107:414e9c822e99 666 * \param ul_alt_cmd Alternative command parameters.
mbed_official 107:414e9c822e99 667 */
mbed_official 107:414e9c822e99 668 void twi_set_alternative_command(Twi *p_twi, uint32_t ul_alt_cmd)
mbed_official 107:414e9c822e99 669 {
mbed_official 107:414e9c822e99 670 p_twi->TWI_ACR = ul_alt_cmd;;
mbed_official 107:414e9c822e99 671 }
mbed_official 107:414e9c822e99 672
mbed_official 107:414e9c822e99 673 /**
mbed_official 107:414e9c822e99 674 * \brief Set the filter for TWI.
mbed_official 107:414e9c822e99 675 *
mbed_official 107:414e9c822e99 676 * \param p_twi Base address of the TWI instance.
mbed_official 107:414e9c822e99 677 * \param ul_filter Filter value.
mbed_official 107:414e9c822e99 678 */
mbed_official 107:414e9c822e99 679 void twi_set_filter(Twi *p_twi, uint32_t ul_filter)
mbed_official 107:414e9c822e99 680 {
mbed_official 107:414e9c822e99 681 p_twi->TWI_FILTR = ul_filter;;
mbed_official 107:414e9c822e99 682 }
mbed_official 107:414e9c822e99 683
mbed_official 107:414e9c822e99 684 /**
mbed_official 107:414e9c822e99 685 * \brief A mask can be applied on the slave device address in slave mode in order to allow multiple
mbed_official 107:414e9c822e99 686 * address answer. For each bit of the MASK field set to one the corresponding SADR bit will be masked.
mbed_official 107:414e9c822e99 687 *
mbed_official 107:414e9c822e99 688 * \param p_twi Base address of the TWI instance.
mbed_official 107:414e9c822e99 689 * \param ul_mask Mask value.
mbed_official 107:414e9c822e99 690 */
mbed_official 107:414e9c822e99 691 void twi_mask_slave_addr(Twi *p_twi, uint32_t ul_mask)
mbed_official 107:414e9c822e99 692 {
mbed_official 107:414e9c822e99 693 p_twi->TWI_SMR |= TWI_SMR_MASK(ul_mask);
mbed_official 107:414e9c822e99 694 }
mbed_official 107:414e9c822e99 695
mbed_official 107:414e9c822e99 696 /**
mbed_official 107:414e9c822e99 697 * \brief Set sleepwalking match mode.
mbed_official 107:414e9c822e99 698 *
mbed_official 107:414e9c822e99 699 * \param p_twi Pointer to a TWI instance.
mbed_official 107:414e9c822e99 700 * \param ul_matching_addr1 Address 1 value.
mbed_official 107:414e9c822e99 701 * \param ul_matching_addr2 Address 2 value.
mbed_official 107:414e9c822e99 702 * \param ul_matching_addr3 Address 3 value.
mbed_official 107:414e9c822e99 703 * \param ul_matching_data Data value.
mbed_official 107:414e9c822e99 704 * \param flag1 ture for set, false for no.
mbed_official 107:414e9c822e99 705 * \param flag2 ture for set, false for no.
mbed_official 107:414e9c822e99 706 * \param flag3 ture for set, false for no.
mbed_official 107:414e9c822e99 707 * \param flag ture for set, false for no.
mbed_official 107:414e9c822e99 708 */
mbed_official 107:414e9c822e99 709 void twi_set_sleepwalking(Twi *p_twi,
mbed_official 107:414e9c822e99 710 uint32_t ul_matching_addr1, bool flag1,
mbed_official 107:414e9c822e99 711 uint32_t ul_matching_addr2, bool flag2,
mbed_official 107:414e9c822e99 712 uint32_t ul_matching_addr3, bool flag3,
mbed_official 107:414e9c822e99 713 uint32_t ul_matching_data, bool flag)
mbed_official 107:414e9c822e99 714 {
mbed_official 107:414e9c822e99 715 uint32_t temp = 0;
mbed_official 107:414e9c822e99 716
mbed_official 107:414e9c822e99 717 if (flag1) {
mbed_official 107:414e9c822e99 718 temp |= TWI_SWMR_SADR1(ul_matching_addr1);
mbed_official 107:414e9c822e99 719 }
mbed_official 107:414e9c822e99 720
mbed_official 107:414e9c822e99 721 if (flag2) {
mbed_official 107:414e9c822e99 722 temp |= TWI_SWMR_SADR2(ul_matching_addr2);
mbed_official 107:414e9c822e99 723 }
mbed_official 107:414e9c822e99 724
mbed_official 107:414e9c822e99 725 if (flag3) {
mbed_official 107:414e9c822e99 726 temp |= TWI_SWMR_SADR3(ul_matching_addr3);
mbed_official 107:414e9c822e99 727 }
mbed_official 107:414e9c822e99 728
mbed_official 107:414e9c822e99 729 if (flag) {
mbed_official 107:414e9c822e99 730 temp |= TWI_SWMR_DATAM(ul_matching_data);
mbed_official 107:414e9c822e99 731 }
mbed_official 107:414e9c822e99 732
mbed_official 107:414e9c822e99 733 p_twi->TWI_SWMR = temp;
mbed_official 107:414e9c822e99 734 }
mbed_official 107:414e9c822e99 735 #endif
mbed_official 107:414e9c822e99 736 //@}
mbed_official 107:414e9c822e99 737
mbed_official 107:414e9c822e99 738 /// @cond 0
mbed_official 107:414e9c822e99 739 /**INDENT-OFF**/
mbed_official 107:414e9c822e99 740 #ifdef __cplusplus
mbed_official 107:414e9c822e99 741 }
mbed_official 107:414e9c822e99 742 #endif
mbed_official 107:414e9c822e99 743 /**INDENT-ON**/
mbed_official 107:414e9c822e99 744 /// @endcond