Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/pmc.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
107:414e9c822e99 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 107:414e9c822e99 1 /**
mbed_official 107:414e9c822e99 2 * \file
mbed_official 107:414e9c822e99 3 *
mbed_official 107:414e9c822e99 4 * \brief Power Management Controller (PMC) driver for SAM.
mbed_official 107:414e9c822e99 5 *
mbed_official 107:414e9c822e99 6 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
mbed_official 107:414e9c822e99 7 *
mbed_official 107:414e9c822e99 8 * \asf_license_start
mbed_official 107:414e9c822e99 9 *
mbed_official 107:414e9c822e99 10 * \page License
mbed_official 107:414e9c822e99 11 *
mbed_official 107:414e9c822e99 12 * Redistribution and use in source and binary forms, with or without
mbed_official 107:414e9c822e99 13 * modification, are permitted provided that the following conditions are met:
mbed_official 107:414e9c822e99 14 *
mbed_official 107:414e9c822e99 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 107:414e9c822e99 16 * this list of conditions and the following disclaimer.
mbed_official 107:414e9c822e99 17 *
mbed_official 107:414e9c822e99 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 107:414e9c822e99 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 107:414e9c822e99 20 * and/or other materials provided with the distribution.
mbed_official 107:414e9c822e99 21 *
mbed_official 107:414e9c822e99 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 107:414e9c822e99 23 * from this software without specific prior written permission.
mbed_official 107:414e9c822e99 24 *
mbed_official 107:414e9c822e99 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 107:414e9c822e99 26 * Atmel microcontroller product.
mbed_official 107:414e9c822e99 27 *
mbed_official 107:414e9c822e99 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 107:414e9c822e99 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 107:414e9c822e99 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 107:414e9c822e99 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 107:414e9c822e99 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 107:414e9c822e99 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 107:414e9c822e99 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 107:414e9c822e99 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 107:414e9c822e99 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 107:414e9c822e99 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 107:414e9c822e99 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 107:414e9c822e99 39 *
mbed_official 107:414e9c822e99 40 * \asf_license_stop
mbed_official 107:414e9c822e99 41 *
mbed_official 107:414e9c822e99 42 */
mbed_official 107:414e9c822e99 43 /*
mbed_official 107:414e9c822e99 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 107:414e9c822e99 45 */
mbed_official 107:414e9c822e99 46
mbed_official 107:414e9c822e99 47 #include "pmc.h"
mbed_official 107:414e9c822e99 48
mbed_official 107:414e9c822e99 49 #if (SAM3N)
mbed_official 107:414e9c822e99 50 # define MAX_PERIPH_ID 31
mbed_official 107:414e9c822e99 51 #elif (SAM3XA)
mbed_official 107:414e9c822e99 52 # define MAX_PERIPH_ID 44
mbed_official 107:414e9c822e99 53 #elif (SAM3U)
mbed_official 107:414e9c822e99 54 # define MAX_PERIPH_ID 29
mbed_official 107:414e9c822e99 55 #elif (SAM3S || SAM4S)
mbed_official 107:414e9c822e99 56 # define MAX_PERIPH_ID 34
mbed_official 107:414e9c822e99 57 #elif (SAM4E)
mbed_official 107:414e9c822e99 58 # define MAX_PERIPH_ID 47
mbed_official 107:414e9c822e99 59 #elif (SAMV71)
mbed_official 107:414e9c822e99 60 # define MAX_PERIPH_ID 63
mbed_official 107:414e9c822e99 61 #elif (SAMV70)
mbed_official 107:414e9c822e99 62 # define MAX_PERIPH_ID 63
mbed_official 107:414e9c822e99 63 #elif (SAME70)
mbed_official 107:414e9c822e99 64 # define MAX_PERIPH_ID 63
mbed_official 107:414e9c822e99 65 #elif (SAMS70)
mbed_official 107:414e9c822e99 66 # define MAX_PERIPH_ID 63
mbed_official 107:414e9c822e99 67 #elif (SAM4N)
mbed_official 107:414e9c822e99 68 # define MAX_PERIPH_ID 31
mbed_official 107:414e9c822e99 69 #elif (SAM4C || SAM4CM || SAM4CP)
mbed_official 107:414e9c822e99 70 # define MAX_PERIPH_ID 43
mbed_official 107:414e9c822e99 71 #elif (SAMG51)
mbed_official 107:414e9c822e99 72 # define MAX_PERIPH_ID 47
mbed_official 107:414e9c822e99 73 #elif (SAMG53)
mbed_official 107:414e9c822e99 74 # define MAX_PERIPH_ID 47
mbed_official 107:414e9c822e99 75 #elif (SAMG54)
mbed_official 107:414e9c822e99 76 # define MAX_PERIPH_ID 47
mbed_official 107:414e9c822e99 77 #elif (SAMG55)
mbed_official 107:414e9c822e99 78 # define MAX_PERIPH_ID 50
mbed_official 107:414e9c822e99 79 #endif
mbed_official 107:414e9c822e99 80
mbed_official 107:414e9c822e99 81 /// @cond 0
mbed_official 107:414e9c822e99 82 /**INDENT-OFF**/
mbed_official 107:414e9c822e99 83 #ifdef __cplusplus
mbed_official 107:414e9c822e99 84 extern "C" {
mbed_official 107:414e9c822e99 85 #endif
mbed_official 107:414e9c822e99 86 /**INDENT-ON**/
mbed_official 107:414e9c822e99 87 /// @endcond
mbed_official 107:414e9c822e99 88
mbed_official 107:414e9c822e99 89 /**
mbed_official 107:414e9c822e99 90 * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
mbed_official 107:414e9c822e99 91 *
mbed_official 107:414e9c822e99 92 * \par Purpose
mbed_official 107:414e9c822e99 93 *
mbed_official 107:414e9c822e99 94 * The Power Management Controller (PMC) optimizes power consumption by
mbed_official 107:414e9c822e99 95 * controlling all system and user peripheral clocks. The PMC enables/disables
mbed_official 107:414e9c822e99 96 * the clock inputs to many of the peripherals and the Cortex-M Processor.
mbed_official 107:414e9c822e99 97 *
mbed_official 107:414e9c822e99 98 * @{
mbed_official 107:414e9c822e99 99 */
mbed_official 107:414e9c822e99 100
mbed_official 107:414e9c822e99 101 /**
mbed_official 107:414e9c822e99 102 * \brief Set the prescaler of the MCK.
mbed_official 107:414e9c822e99 103 *
mbed_official 107:414e9c822e99 104 * \param ul_pres Prescaler value.
mbed_official 107:414e9c822e99 105 */
mbed_official 107:414e9c822e99 106 void pmc_mck_set_prescaler(uint32_t ul_pres)
mbed_official 107:414e9c822e99 107 {
mbed_official 107:414e9c822e99 108 PMC->PMC_MCKR =
mbed_official 107:414e9c822e99 109 (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 110 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
mbed_official 107:414e9c822e99 111 }
mbed_official 107:414e9c822e99 112
mbed_official 107:414e9c822e99 113 #if SAMV71 || SAMV70 || SAME70 || SAMS70
mbed_official 107:414e9c822e99 114 /**
mbed_official 107:414e9c822e99 115 * \brief Set the division of the MCK.
mbed_official 107:414e9c822e99 116 *
mbed_official 107:414e9c822e99 117 * \param ul_div Division value.
mbed_official 107:414e9c822e99 118 */
mbed_official 107:414e9c822e99 119 void pmc_mck_set_division(uint32_t ul_div)
mbed_official 107:414e9c822e99 120 {
mbed_official 107:414e9c822e99 121 switch (ul_div) {
mbed_official 107:414e9c822e99 122 case 1:
mbed_official 107:414e9c822e99 123 ul_div = PMC_MCKR_MDIV_EQ_PCK;
mbed_official 107:414e9c822e99 124 break;
mbed_official 107:414e9c822e99 125 case 2:
mbed_official 107:414e9c822e99 126 ul_div = PMC_MCKR_MDIV_PCK_DIV2;
mbed_official 107:414e9c822e99 127 break;
mbed_official 107:414e9c822e99 128 case 3:
mbed_official 107:414e9c822e99 129 ul_div = PMC_MCKR_MDIV_PCK_DIV3;
mbed_official 107:414e9c822e99 130 break;
mbed_official 107:414e9c822e99 131 case 4:
mbed_official 107:414e9c822e99 132 ul_div = PMC_MCKR_MDIV_PCK_DIV4;
mbed_official 107:414e9c822e99 133 break;
mbed_official 107:414e9c822e99 134 default:
mbed_official 107:414e9c822e99 135 ul_div = PMC_MCKR_MDIV_EQ_PCK;
mbed_official 107:414e9c822e99 136 break;
mbed_official 107:414e9c822e99 137 }
mbed_official 107:414e9c822e99 138 PMC->PMC_MCKR =
mbed_official 107:414e9c822e99 139 (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
mbed_official 107:414e9c822e99 140 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
mbed_official 107:414e9c822e99 141 }
mbed_official 107:414e9c822e99 142 #endif
mbed_official 107:414e9c822e99 143
mbed_official 107:414e9c822e99 144 /**
mbed_official 107:414e9c822e99 145 * \brief Set the source of the MCK.
mbed_official 107:414e9c822e99 146 *
mbed_official 107:414e9c822e99 147 * \param ul_source Source selection value.
mbed_official 107:414e9c822e99 148 */
mbed_official 107:414e9c822e99 149 void pmc_mck_set_source(uint32_t ul_source)
mbed_official 107:414e9c822e99 150 {
mbed_official 107:414e9c822e99 151 PMC->PMC_MCKR =
mbed_official 107:414e9c822e99 152 (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
mbed_official 107:414e9c822e99 153 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
mbed_official 107:414e9c822e99 154 }
mbed_official 107:414e9c822e99 155
mbed_official 107:414e9c822e99 156 /**
mbed_official 107:414e9c822e99 157 * \brief Switch master clock source selection to slow clock.
mbed_official 107:414e9c822e99 158 *
mbed_official 107:414e9c822e99 159 * \param ul_pres Processor clock prescaler.
mbed_official 107:414e9c822e99 160 *
mbed_official 107:414e9c822e99 161 * \retval 0 Success.
mbed_official 107:414e9c822e99 162 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 163 */
mbed_official 107:414e9c822e99 164 uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
mbed_official 107:414e9c822e99 165 {
mbed_official 107:414e9c822e99 166 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 167
mbed_official 107:414e9c822e99 168 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
mbed_official 107:414e9c822e99 169 PMC_MCKR_CSS_SLOW_CLK;
mbed_official 107:414e9c822e99 170 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 171 --ul_timeout) {
mbed_official 107:414e9c822e99 172 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 173 return 1;
mbed_official 107:414e9c822e99 174 }
mbed_official 107:414e9c822e99 175 }
mbed_official 107:414e9c822e99 176
mbed_official 107:414e9c822e99 177 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 178 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 179 --ul_timeout) {
mbed_official 107:414e9c822e99 180 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 181 return 1;
mbed_official 107:414e9c822e99 182 }
mbed_official 107:414e9c822e99 183 }
mbed_official 107:414e9c822e99 184
mbed_official 107:414e9c822e99 185 return 0;
mbed_official 107:414e9c822e99 186 }
mbed_official 107:414e9c822e99 187
mbed_official 107:414e9c822e99 188 /**
mbed_official 107:414e9c822e99 189 * \brief Switch master clock source selection to main clock.
mbed_official 107:414e9c822e99 190 *
mbed_official 107:414e9c822e99 191 * \param ul_pres Processor clock prescaler.
mbed_official 107:414e9c822e99 192 *
mbed_official 107:414e9c822e99 193 * \retval 0 Success.
mbed_official 107:414e9c822e99 194 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 195 */
mbed_official 107:414e9c822e99 196 uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
mbed_official 107:414e9c822e99 197 {
mbed_official 107:414e9c822e99 198 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 199
mbed_official 107:414e9c822e99 200 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
mbed_official 107:414e9c822e99 201 PMC_MCKR_CSS_MAIN_CLK;
mbed_official 107:414e9c822e99 202 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 203 --ul_timeout) {
mbed_official 107:414e9c822e99 204 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 205 return 1;
mbed_official 107:414e9c822e99 206 }
mbed_official 107:414e9c822e99 207 }
mbed_official 107:414e9c822e99 208
mbed_official 107:414e9c822e99 209 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 210 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 211 --ul_timeout) {
mbed_official 107:414e9c822e99 212 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 213 return 1;
mbed_official 107:414e9c822e99 214 }
mbed_official 107:414e9c822e99 215 }
mbed_official 107:414e9c822e99 216
mbed_official 107:414e9c822e99 217 return 0;
mbed_official 107:414e9c822e99 218 }
mbed_official 107:414e9c822e99 219
mbed_official 107:414e9c822e99 220 /**
mbed_official 107:414e9c822e99 221 * \brief Switch master clock source selection to PLLA clock.
mbed_official 107:414e9c822e99 222 *
mbed_official 107:414e9c822e99 223 * \param ul_pres Processor clock prescaler.
mbed_official 107:414e9c822e99 224 *
mbed_official 107:414e9c822e99 225 * \retval 0 Success.
mbed_official 107:414e9c822e99 226 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 227 */
mbed_official 107:414e9c822e99 228 uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
mbed_official 107:414e9c822e99 229 {
mbed_official 107:414e9c822e99 230 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 231
mbed_official 107:414e9c822e99 232 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 233 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 234 --ul_timeout) {
mbed_official 107:414e9c822e99 235 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 236 return 1;
mbed_official 107:414e9c822e99 237 }
mbed_official 107:414e9c822e99 238 }
mbed_official 107:414e9c822e99 239
mbed_official 107:414e9c822e99 240 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
mbed_official 107:414e9c822e99 241 PMC_MCKR_CSS_PLLA_CLK;
mbed_official 107:414e9c822e99 242
mbed_official 107:414e9c822e99 243 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 244 --ul_timeout) {
mbed_official 107:414e9c822e99 245 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 246 return 1;
mbed_official 107:414e9c822e99 247 }
mbed_official 107:414e9c822e99 248 }
mbed_official 107:414e9c822e99 249
mbed_official 107:414e9c822e99 250 return 0;
mbed_official 107:414e9c822e99 251 }
mbed_official 107:414e9c822e99 252
mbed_official 107:414e9c822e99 253 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
mbed_official 107:414e9c822e99 254 /**
mbed_official 107:414e9c822e99 255 * \brief Switch master clock source selection to PLLB clock.
mbed_official 107:414e9c822e99 256 *
mbed_official 107:414e9c822e99 257 * \param ul_pres Processor clock prescaler.
mbed_official 107:414e9c822e99 258 *
mbed_official 107:414e9c822e99 259 * \retval 0 Success.
mbed_official 107:414e9c822e99 260 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 261 */
mbed_official 107:414e9c822e99 262 uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
mbed_official 107:414e9c822e99 263 {
mbed_official 107:414e9c822e99 264 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 265
mbed_official 107:414e9c822e99 266 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 267 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 268 --ul_timeout) {
mbed_official 107:414e9c822e99 269 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 270 return 1;
mbed_official 107:414e9c822e99 271 }
mbed_official 107:414e9c822e99 272 }
mbed_official 107:414e9c822e99 273
mbed_official 107:414e9c822e99 274 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
mbed_official 107:414e9c822e99 275 PMC_MCKR_CSS_PLLB_CLK;
mbed_official 107:414e9c822e99 276 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 277 --ul_timeout) {
mbed_official 107:414e9c822e99 278 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 279 return 1;
mbed_official 107:414e9c822e99 280 }
mbed_official 107:414e9c822e99 281 }
mbed_official 107:414e9c822e99 282
mbed_official 107:414e9c822e99 283 return 0;
mbed_official 107:414e9c822e99 284 }
mbed_official 107:414e9c822e99 285 #endif
mbed_official 107:414e9c822e99 286
mbed_official 107:414e9c822e99 287 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 288 /**
mbed_official 107:414e9c822e99 289 * \brief Switch master clock source selection to UPLL clock.
mbed_official 107:414e9c822e99 290 *
mbed_official 107:414e9c822e99 291 * \param ul_pres Processor clock prescaler.
mbed_official 107:414e9c822e99 292 *
mbed_official 107:414e9c822e99 293 * \retval 0 Success.
mbed_official 107:414e9c822e99 294 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 295 */
mbed_official 107:414e9c822e99 296 uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
mbed_official 107:414e9c822e99 297 {
mbed_official 107:414e9c822e99 298 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 299
mbed_official 107:414e9c822e99 300 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
mbed_official 107:414e9c822e99 301 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 302 --ul_timeout) {
mbed_official 107:414e9c822e99 303 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 304 return 1;
mbed_official 107:414e9c822e99 305 }
mbed_official 107:414e9c822e99 306 }
mbed_official 107:414e9c822e99 307
mbed_official 107:414e9c822e99 308 PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
mbed_official 107:414e9c822e99 309 PMC_MCKR_CSS_UPLL_CLK;
mbed_official 107:414e9c822e99 310 for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
mbed_official 107:414e9c822e99 311 --ul_timeout) {
mbed_official 107:414e9c822e99 312 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 313 return 1;
mbed_official 107:414e9c822e99 314 }
mbed_official 107:414e9c822e99 315 }
mbed_official 107:414e9c822e99 316
mbed_official 107:414e9c822e99 317 return 0;
mbed_official 107:414e9c822e99 318 }
mbed_official 107:414e9c822e99 319 #endif
mbed_official 107:414e9c822e99 320
mbed_official 107:414e9c822e99 321 /**
mbed_official 107:414e9c822e99 322 * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
mbed_official 107:414e9c822e99 323 *
mbed_official 107:414e9c822e99 324 * \note Switching SCLK back to 32krc is only possible by shutting down the
mbed_official 107:414e9c822e99 325 * VDDIO power supply.
mbed_official 107:414e9c822e99 326 *
mbed_official 107:414e9c822e99 327 * \param ul_bypass 0 for Xtal, 1 for bypass.
mbed_official 107:414e9c822e99 328 */
mbed_official 107:414e9c822e99 329 void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
mbed_official 107:414e9c822e99 330 {
mbed_official 107:414e9c822e99 331 /* Set Bypass mode if required */
mbed_official 107:414e9c822e99 332 if (ul_bypass == 1) {
mbed_official 107:414e9c822e99 333 SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
mbed_official 107:414e9c822e99 334 SUPC_MR_OSCBYPASS;
mbed_official 107:414e9c822e99 335 }
mbed_official 107:414e9c822e99 336
mbed_official 107:414e9c822e99 337 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
mbed_official 107:414e9c822e99 338 }
mbed_official 107:414e9c822e99 339
mbed_official 107:414e9c822e99 340 /**
mbed_official 107:414e9c822e99 341 * \brief Check if the external 32k Xtal is ready.
mbed_official 107:414e9c822e99 342 *
mbed_official 107:414e9c822e99 343 * \retval 1 External 32k Xtal is ready.
mbed_official 107:414e9c822e99 344 * \retval 0 External 32k Xtal is not ready.
mbed_official 107:414e9c822e99 345 */
mbed_official 107:414e9c822e99 346 uint32_t pmc_osc_is_ready_32kxtal(void)
mbed_official 107:414e9c822e99 347 {
mbed_official 107:414e9c822e99 348 return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
mbed_official 107:414e9c822e99 349 && (PMC->PMC_SR & PMC_SR_OSCSELS));
mbed_official 107:414e9c822e99 350 }
mbed_official 107:414e9c822e99 351
mbed_official 107:414e9c822e99 352 /**
mbed_official 107:414e9c822e99 353 * \brief Switch main clock source selection to internal fast RC.
mbed_official 107:414e9c822e99 354 *
mbed_official 107:414e9c822e99 355 * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
mbed_official 107:414e9c822e99 356 *
mbed_official 107:414e9c822e99 357 * \retval 0 Success.
mbed_official 107:414e9c822e99 358 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 359 * \retval 2 Invalid frequency.
mbed_official 107:414e9c822e99 360 */
mbed_official 107:414e9c822e99 361 void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
mbed_official 107:414e9c822e99 362 {
mbed_official 107:414e9c822e99 363 /* Enable Fast RC oscillator but DO NOT switch to RC now */
mbed_official 107:414e9c822e99 364 PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
mbed_official 107:414e9c822e99 365
mbed_official 107:414e9c822e99 366 /* Wait the Fast RC to stabilize */
mbed_official 107:414e9c822e99 367 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
mbed_official 107:414e9c822e99 368
mbed_official 107:414e9c822e99 369 /* Change Fast RC oscillator frequency */
mbed_official 107:414e9c822e99 370 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
mbed_official 107:414e9c822e99 371 CKGR_MOR_KEY_PASSWD | ul_moscrcf;
mbed_official 107:414e9c822e99 372
mbed_official 107:414e9c822e99 373 /* Wait the Fast RC to stabilize */
mbed_official 107:414e9c822e99 374 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
mbed_official 107:414e9c822e99 375
mbed_official 107:414e9c822e99 376 /* Switch to Fast RC */
mbed_official 107:414e9c822e99 377 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
mbed_official 107:414e9c822e99 378 CKGR_MOR_KEY_PASSWD;
mbed_official 107:414e9c822e99 379 }
mbed_official 107:414e9c822e99 380
mbed_official 107:414e9c822e99 381 /**
mbed_official 107:414e9c822e99 382 * \brief Enable fast RC oscillator.
mbed_official 107:414e9c822e99 383 *
mbed_official 107:414e9c822e99 384 * \param ul_rc Fast RC oscillator(4/8/12Mhz).
mbed_official 107:414e9c822e99 385 */
mbed_official 107:414e9c822e99 386 void pmc_osc_enable_fastrc(uint32_t ul_rc)
mbed_official 107:414e9c822e99 387 {
mbed_official 107:414e9c822e99 388 /* Enable Fast RC oscillator but DO NOT switch to RC */
mbed_official 107:414e9c822e99 389 PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
mbed_official 107:414e9c822e99 390 /* Wait the Fast RC to stabilize */
mbed_official 107:414e9c822e99 391 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
mbed_official 107:414e9c822e99 392
mbed_official 107:414e9c822e99 393 /* Change Fast RC oscillator frequency */
mbed_official 107:414e9c822e99 394 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
mbed_official 107:414e9c822e99 395 CKGR_MOR_KEY_PASSWD | ul_rc;
mbed_official 107:414e9c822e99 396 /* Wait the Fast RC to stabilize */
mbed_official 107:414e9c822e99 397 while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
mbed_official 107:414e9c822e99 398 }
mbed_official 107:414e9c822e99 399
mbed_official 107:414e9c822e99 400 /**
mbed_official 107:414e9c822e99 401 * \brief Disable the internal fast RC.
mbed_official 107:414e9c822e99 402 */
mbed_official 107:414e9c822e99 403 void pmc_osc_disable_fastrc(void)
mbed_official 107:414e9c822e99 404 {
mbed_official 107:414e9c822e99 405 /* Disable Fast RC oscillator */
mbed_official 107:414e9c822e99 406 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
mbed_official 107:414e9c822e99 407 ~CKGR_MOR_MOSCRCF_Msk)
mbed_official 107:414e9c822e99 408 | CKGR_MOR_KEY_PASSWD;
mbed_official 107:414e9c822e99 409 }
mbed_official 107:414e9c822e99 410
mbed_official 107:414e9c822e99 411 /**
mbed_official 107:414e9c822e99 412 * \brief Check if the main fastrc is ready.
mbed_official 107:414e9c822e99 413 *
mbed_official 107:414e9c822e99 414 * \retval 0 Xtal is not ready, otherwise ready.
mbed_official 107:414e9c822e99 415 */
mbed_official 107:414e9c822e99 416 uint32_t pmc_osc_is_ready_fastrc(void)
mbed_official 107:414e9c822e99 417 {
mbed_official 107:414e9c822e99 418 return (PMC->PMC_SR & PMC_SR_MOSCRCS);
mbed_official 107:414e9c822e99 419 }
mbed_official 107:414e9c822e99 420
mbed_official 107:414e9c822e99 421 /**
mbed_official 107:414e9c822e99 422 * \brief Enable main XTAL oscillator.
mbed_official 107:414e9c822e99 423 *
mbed_official 107:414e9c822e99 424 * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.
mbed_official 107:414e9c822e99 425 */
mbed_official 107:414e9c822e99 426 void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
mbed_official 107:414e9c822e99 427 {
mbed_official 107:414e9c822e99 428 uint32_t mor = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 429 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
mbed_official 107:414e9c822e99 430 mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
mbed_official 107:414e9c822e99 431 CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
mbed_official 107:414e9c822e99 432 PMC->CKGR_MOR = mor;
mbed_official 107:414e9c822e99 433 /* Wait the main Xtal to stabilize */
mbed_official 107:414e9c822e99 434 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
mbed_official 107:414e9c822e99 435 }
mbed_official 107:414e9c822e99 436
mbed_official 107:414e9c822e99 437 /**
mbed_official 107:414e9c822e99 438 * \brief Bypass main XTAL.
mbed_official 107:414e9c822e99 439 */
mbed_official 107:414e9c822e99 440 void pmc_osc_bypass_main_xtal(void)
mbed_official 107:414e9c822e99 441 {
mbed_official 107:414e9c822e99 442 uint32_t mor = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 443 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
mbed_official 107:414e9c822e99 444 mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
mbed_official 107:414e9c822e99 445 /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
mbed_official 107:414e9c822e99 446 PMC->CKGR_MOR = mor;
mbed_official 107:414e9c822e99 447 /* The MOSCXTS in PMC_SR is automatically set */
mbed_official 107:414e9c822e99 448 }
mbed_official 107:414e9c822e99 449
mbed_official 107:414e9c822e99 450 /**
mbed_official 107:414e9c822e99 451 * \brief Disable the main Xtal.
mbed_official 107:414e9c822e99 452 */
mbed_official 107:414e9c822e99 453 void pmc_osc_disable_main_xtal(void)
mbed_official 107:414e9c822e99 454 {
mbed_official 107:414e9c822e99 455 uint32_t mor = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 456 mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
mbed_official 107:414e9c822e99 457 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
mbed_official 107:414e9c822e99 458 }
mbed_official 107:414e9c822e99 459
mbed_official 107:414e9c822e99 460 /**
mbed_official 107:414e9c822e99 461 * \brief Check if the main crystal is bypassed.
mbed_official 107:414e9c822e99 462 *
mbed_official 107:414e9c822e99 463 * \retval 0 Xtal is bypassed, otherwise not.
mbed_official 107:414e9c822e99 464 */
mbed_official 107:414e9c822e99 465 uint32_t pmc_osc_is_bypassed_main_xtal(void)
mbed_official 107:414e9c822e99 466 {
mbed_official 107:414e9c822e99 467 return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
mbed_official 107:414e9c822e99 468 }
mbed_official 107:414e9c822e99 469
mbed_official 107:414e9c822e99 470 /**
mbed_official 107:414e9c822e99 471 * \brief Check if the main crystal is ready.
mbed_official 107:414e9c822e99 472 *
mbed_official 107:414e9c822e99 473 * \note If main crystal is bypassed, it's always ready.
mbed_official 107:414e9c822e99 474 *
mbed_official 107:414e9c822e99 475 * \retval 0 main crystal is not ready, otherwise ready.
mbed_official 107:414e9c822e99 476 */
mbed_official 107:414e9c822e99 477 uint32_t pmc_osc_is_ready_main_xtal(void)
mbed_official 107:414e9c822e99 478 {
mbed_official 107:414e9c822e99 479 return (PMC->PMC_SR & PMC_SR_MOSCXTS);
mbed_official 107:414e9c822e99 480 }
mbed_official 107:414e9c822e99 481
mbed_official 107:414e9c822e99 482 /**
mbed_official 107:414e9c822e99 483 * \brief Switch main clock source selection to external Xtal/Bypass.
mbed_official 107:414e9c822e99 484 *
mbed_official 107:414e9c822e99 485 * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid
mbed_official 107:414e9c822e99 486 * any system crash.
mbed_official 107:414e9c822e99 487 *
mbed_official 107:414e9c822e99 488 * \note If used in Xtal mode, the Xtal is automatically enabled.
mbed_official 107:414e9c822e99 489 *
mbed_official 107:414e9c822e99 490 * \param ul_bypass 0 for Xtal, 1 for bypass.
mbed_official 107:414e9c822e99 491 *
mbed_official 107:414e9c822e99 492 * \retval 0 Success.
mbed_official 107:414e9c822e99 493 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 494 */
mbed_official 107:414e9c822e99 495 void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
mbed_official 107:414e9c822e99 496 uint32_t ul_xtal_startup_time)
mbed_official 107:414e9c822e99 497 {
mbed_official 107:414e9c822e99 498 /* Enable Main Xtal oscillator */
mbed_official 107:414e9c822e99 499 if (ul_bypass) {
mbed_official 107:414e9c822e99 500 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
mbed_official 107:414e9c822e99 501 CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
mbed_official 107:414e9c822e99 502 CKGR_MOR_MOSCSEL;
mbed_official 107:414e9c822e99 503 } else {
mbed_official 107:414e9c822e99 504 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
mbed_official 107:414e9c822e99 505 CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
mbed_official 107:414e9c822e99 506 CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
mbed_official 107:414e9c822e99 507 /* Wait the Xtal to stabilize */
mbed_official 107:414e9c822e99 508 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
mbed_official 107:414e9c822e99 509
mbed_official 107:414e9c822e99 510 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
mbed_official 107:414e9c822e99 511 }
mbed_official 107:414e9c822e99 512 }
mbed_official 107:414e9c822e99 513
mbed_official 107:414e9c822e99 514 /**
mbed_official 107:414e9c822e99 515 * \brief Disable the external Xtal.
mbed_official 107:414e9c822e99 516 *
mbed_official 107:414e9c822e99 517 * \param ul_bypass 0 for Xtal, 1 for bypass.
mbed_official 107:414e9c822e99 518 */
mbed_official 107:414e9c822e99 519 void pmc_osc_disable_xtal(uint32_t ul_bypass)
mbed_official 107:414e9c822e99 520 {
mbed_official 107:414e9c822e99 521 /* Disable xtal oscillator */
mbed_official 107:414e9c822e99 522 if (ul_bypass) {
mbed_official 107:414e9c822e99 523 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
mbed_official 107:414e9c822e99 524 CKGR_MOR_KEY_PASSWD;
mbed_official 107:414e9c822e99 525 } else {
mbed_official 107:414e9c822e99 526 PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
mbed_official 107:414e9c822e99 527 CKGR_MOR_KEY_PASSWD;
mbed_official 107:414e9c822e99 528 }
mbed_official 107:414e9c822e99 529 }
mbed_official 107:414e9c822e99 530
mbed_official 107:414e9c822e99 531 /**
mbed_official 107:414e9c822e99 532 * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
mbed_official 107:414e9c822e99 533 * of Xtal, bypass or internal RC.
mbed_official 107:414e9c822e99 534 *
mbed_official 107:414e9c822e99 535 * \retval 1 Xtal is ready.
mbed_official 107:414e9c822e99 536 * \retval 0 Xtal is not ready.
mbed_official 107:414e9c822e99 537 */
mbed_official 107:414e9c822e99 538 uint32_t pmc_osc_is_ready_mainck(void)
mbed_official 107:414e9c822e99 539 {
mbed_official 107:414e9c822e99 540 return PMC->PMC_SR & PMC_SR_MOSCSELS;
mbed_official 107:414e9c822e99 541 }
mbed_official 107:414e9c822e99 542
mbed_official 107:414e9c822e99 543 /**
mbed_official 107:414e9c822e99 544 * \brief Select Main Crystal or internal RC as main clock source.
mbed_official 107:414e9c822e99 545 *
mbed_official 107:414e9c822e99 546 * \note This function will not enable/disable RC or Main Crystal.
mbed_official 107:414e9c822e99 547 *
mbed_official 107:414e9c822e99 548 * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.
mbed_official 107:414e9c822e99 549 */
mbed_official 107:414e9c822e99 550 void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
mbed_official 107:414e9c822e99 551 {
mbed_official 107:414e9c822e99 552 uint32_t mor = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 553 if (ul_xtal_rc) {
mbed_official 107:414e9c822e99 554 mor |= CKGR_MOR_MOSCSEL;
mbed_official 107:414e9c822e99 555 } else {
mbed_official 107:414e9c822e99 556 mor &= ~CKGR_MOR_MOSCSEL;
mbed_official 107:414e9c822e99 557 }
mbed_official 107:414e9c822e99 558 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
mbed_official 107:414e9c822e99 559 }
mbed_official 107:414e9c822e99 560
mbed_official 107:414e9c822e99 561 /**
mbed_official 107:414e9c822e99 562 * \brief Enable PLLA clock.
mbed_official 107:414e9c822e99 563 *
mbed_official 107:414e9c822e99 564 * \param mula PLLA multiplier.
mbed_official 107:414e9c822e99 565 * \param pllacount PLLA counter.
mbed_official 107:414e9c822e99 566 * \param diva Divider.
mbed_official 107:414e9c822e99 567 */
mbed_official 107:414e9c822e99 568 void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
mbed_official 107:414e9c822e99 569 {
mbed_official 107:414e9c822e99 570 /* first disable the PLL to unlock the lock */
mbed_official 107:414e9c822e99 571 pmc_disable_pllack();
mbed_official 107:414e9c822e99 572
mbed_official 107:414e9c822e99 573 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
mbed_official 107:414e9c822e99 574 PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
mbed_official 107:414e9c822e99 575 CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
mbed_official 107:414e9c822e99 576 #else
mbed_official 107:414e9c822e99 577 PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
mbed_official 107:414e9c822e99 578 CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
mbed_official 107:414e9c822e99 579 #endif
mbed_official 107:414e9c822e99 580 while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
mbed_official 107:414e9c822e99 581 }
mbed_official 107:414e9c822e99 582
mbed_official 107:414e9c822e99 583 /**
mbed_official 107:414e9c822e99 584 * \brief Disable PLLA clock.
mbed_official 107:414e9c822e99 585 */
mbed_official 107:414e9c822e99 586 void pmc_disable_pllack(void)
mbed_official 107:414e9c822e99 587 {
mbed_official 107:414e9c822e99 588 #if (SAM4C || SAM4CM || SAM4CP || SAMG)
mbed_official 107:414e9c822e99 589 PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
mbed_official 107:414e9c822e99 590 #else
mbed_official 107:414e9c822e99 591 PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
mbed_official 107:414e9c822e99 592 #endif
mbed_official 107:414e9c822e99 593 }
mbed_official 107:414e9c822e99 594
mbed_official 107:414e9c822e99 595 /**
mbed_official 107:414e9c822e99 596 * \brief Is PLLA locked?
mbed_official 107:414e9c822e99 597 *
mbed_official 107:414e9c822e99 598 * \retval 0 Not locked.
mbed_official 107:414e9c822e99 599 * \retval 1 Locked.
mbed_official 107:414e9c822e99 600 */
mbed_official 107:414e9c822e99 601 uint32_t pmc_is_locked_pllack(void)
mbed_official 107:414e9c822e99 602 {
mbed_official 107:414e9c822e99 603 return (PMC->PMC_SR & PMC_SR_LOCKA);
mbed_official 107:414e9c822e99 604 }
mbed_official 107:414e9c822e99 605
mbed_official 107:414e9c822e99 606 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
mbed_official 107:414e9c822e99 607 /**
mbed_official 107:414e9c822e99 608 * \brief Enable PLLB clock.
mbed_official 107:414e9c822e99 609 *
mbed_official 107:414e9c822e99 610 * \param mulb PLLB multiplier.
mbed_official 107:414e9c822e99 611 * \param pllbcount PLLB counter.
mbed_official 107:414e9c822e99 612 * \param divb Divider.
mbed_official 107:414e9c822e99 613 */
mbed_official 107:414e9c822e99 614 void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
mbed_official 107:414e9c822e99 615 {
mbed_official 107:414e9c822e99 616 /* first disable the PLL to unlock the lock */
mbed_official 107:414e9c822e99 617 pmc_disable_pllbck();
mbed_official 107:414e9c822e99 618
mbed_official 107:414e9c822e99 619 #if SAMG55
mbed_official 107:414e9c822e99 620 PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
mbed_official 107:414e9c822e99 621 CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
mbed_official 107:414e9c822e99 622 #else
mbed_official 107:414e9c822e99 623 PMC->CKGR_PLLBR =
mbed_official 107:414e9c822e99 624 CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
mbed_official 107:414e9c822e99 625 | CKGR_PLLBR_MULB(mulb);
mbed_official 107:414e9c822e99 626 #endif
mbed_official 107:414e9c822e99 627 while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
mbed_official 107:414e9c822e99 628 }
mbed_official 107:414e9c822e99 629
mbed_official 107:414e9c822e99 630 /**
mbed_official 107:414e9c822e99 631 * \brief Disable PLLB clock.
mbed_official 107:414e9c822e99 632 */
mbed_official 107:414e9c822e99 633 void pmc_disable_pllbck(void)
mbed_official 107:414e9c822e99 634 {
mbed_official 107:414e9c822e99 635 PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
mbed_official 107:414e9c822e99 636 }
mbed_official 107:414e9c822e99 637
mbed_official 107:414e9c822e99 638 /**
mbed_official 107:414e9c822e99 639 * \brief Is PLLB locked?
mbed_official 107:414e9c822e99 640 *
mbed_official 107:414e9c822e99 641 * \retval 0 Not locked.
mbed_official 107:414e9c822e99 642 * \retval 1 Locked.
mbed_official 107:414e9c822e99 643 */
mbed_official 107:414e9c822e99 644 uint32_t pmc_is_locked_pllbck(void)
mbed_official 107:414e9c822e99 645 {
mbed_official 107:414e9c822e99 646 return (PMC->PMC_SR & PMC_SR_LOCKB);
mbed_official 107:414e9c822e99 647 }
mbed_official 107:414e9c822e99 648 #endif
mbed_official 107:414e9c822e99 649
mbed_official 107:414e9c822e99 650 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 651 /**
mbed_official 107:414e9c822e99 652 * \brief Enable UPLL clock.
mbed_official 107:414e9c822e99 653 */
mbed_official 107:414e9c822e99 654 void pmc_enable_upll_clock(void)
mbed_official 107:414e9c822e99 655 {
mbed_official 107:414e9c822e99 656 PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
mbed_official 107:414e9c822e99 657
mbed_official 107:414e9c822e99 658 /* Wait UTMI PLL Lock Status */
mbed_official 107:414e9c822e99 659 while (!(PMC->PMC_SR & PMC_SR_LOCKU));
mbed_official 107:414e9c822e99 660 }
mbed_official 107:414e9c822e99 661
mbed_official 107:414e9c822e99 662 /**
mbed_official 107:414e9c822e99 663 * \brief Disable UPLL clock.
mbed_official 107:414e9c822e99 664 */
mbed_official 107:414e9c822e99 665 void pmc_disable_upll_clock(void)
mbed_official 107:414e9c822e99 666 {
mbed_official 107:414e9c822e99 667 PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
mbed_official 107:414e9c822e99 668 }
mbed_official 107:414e9c822e99 669
mbed_official 107:414e9c822e99 670 /**
mbed_official 107:414e9c822e99 671 * \brief Is UPLL locked?
mbed_official 107:414e9c822e99 672 *
mbed_official 107:414e9c822e99 673 * \retval 0 Not locked.
mbed_official 107:414e9c822e99 674 * \retval 1 Locked.
mbed_official 107:414e9c822e99 675 */
mbed_official 107:414e9c822e99 676 uint32_t pmc_is_locked_upll(void)
mbed_official 107:414e9c822e99 677 {
mbed_official 107:414e9c822e99 678 return (PMC->PMC_SR & PMC_SR_LOCKU);
mbed_official 107:414e9c822e99 679 }
mbed_official 107:414e9c822e99 680 #endif
mbed_official 107:414e9c822e99 681
mbed_official 107:414e9c822e99 682 /**
mbed_official 107:414e9c822e99 683 * \brief Enable the specified peripheral clock.
mbed_official 107:414e9c822e99 684 *
mbed_official 107:414e9c822e99 685 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
mbed_official 107:414e9c822e99 686 *
mbed_official 107:414e9c822e99 687 * \param ul_id Peripheral ID (ID_xxx).
mbed_official 107:414e9c822e99 688 *
mbed_official 107:414e9c822e99 689 * \retval 0 Success.
mbed_official 107:414e9c822e99 690 * \retval 1 Invalid parameter.
mbed_official 107:414e9c822e99 691 */
mbed_official 107:414e9c822e99 692 uint32_t pmc_enable_periph_clk(uint32_t ul_id)
mbed_official 107:414e9c822e99 693 {
mbed_official 107:414e9c822e99 694 if (ul_id > MAX_PERIPH_ID) {
mbed_official 107:414e9c822e99 695 return 1;
mbed_official 107:414e9c822e99 696 }
mbed_official 107:414e9c822e99 697
mbed_official 107:414e9c822e99 698 if (ul_id < 32) {
mbed_official 107:414e9c822e99 699 if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
mbed_official 107:414e9c822e99 700 PMC->PMC_PCER0 = 1 << ul_id;
mbed_official 107:414e9c822e99 701 }
mbed_official 107:414e9c822e99 702 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 703 } else {
mbed_official 107:414e9c822e99 704 ul_id -= 32;
mbed_official 107:414e9c822e99 705 if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
mbed_official 107:414e9c822e99 706 PMC->PMC_PCER1 = 1 << ul_id;
mbed_official 107:414e9c822e99 707 }
mbed_official 107:414e9c822e99 708 #endif
mbed_official 107:414e9c822e99 709 }
mbed_official 107:414e9c822e99 710
mbed_official 107:414e9c822e99 711 return 0;
mbed_official 107:414e9c822e99 712 }
mbed_official 107:414e9c822e99 713
mbed_official 107:414e9c822e99 714 /**
mbed_official 107:414e9c822e99 715 * \brief Disable the specified peripheral clock.
mbed_official 107:414e9c822e99 716 *
mbed_official 107:414e9c822e99 717 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
mbed_official 107:414e9c822e99 718 *
mbed_official 107:414e9c822e99 719 * \param ul_id Peripheral ID (ID_xxx).
mbed_official 107:414e9c822e99 720 *
mbed_official 107:414e9c822e99 721 * \retval 0 Success.
mbed_official 107:414e9c822e99 722 * \retval 1 Invalid parameter.
mbed_official 107:414e9c822e99 723 */
mbed_official 107:414e9c822e99 724 uint32_t pmc_disable_periph_clk(uint32_t ul_id)
mbed_official 107:414e9c822e99 725 {
mbed_official 107:414e9c822e99 726 if (ul_id > MAX_PERIPH_ID) {
mbed_official 107:414e9c822e99 727 return 1;
mbed_official 107:414e9c822e99 728 }
mbed_official 107:414e9c822e99 729
mbed_official 107:414e9c822e99 730 if (ul_id < 32) {
mbed_official 107:414e9c822e99 731 if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
mbed_official 107:414e9c822e99 732 PMC->PMC_PCDR0 = 1 << ul_id;
mbed_official 107:414e9c822e99 733 }
mbed_official 107:414e9c822e99 734 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
mbed_official 107:414e9c822e99 735 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 736 } else {
mbed_official 107:414e9c822e99 737 ul_id -= 32;
mbed_official 107:414e9c822e99 738 if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
mbed_official 107:414e9c822e99 739 PMC->PMC_PCDR1 = 1 << ul_id;
mbed_official 107:414e9c822e99 740 }
mbed_official 107:414e9c822e99 741 #endif
mbed_official 107:414e9c822e99 742 }
mbed_official 107:414e9c822e99 743 return 0;
mbed_official 107:414e9c822e99 744 }
mbed_official 107:414e9c822e99 745
mbed_official 107:414e9c822e99 746 /**
mbed_official 107:414e9c822e99 747 * \brief Enable all peripheral clocks.
mbed_official 107:414e9c822e99 748 */
mbed_official 107:414e9c822e99 749 void pmc_enable_all_periph_clk(void)
mbed_official 107:414e9c822e99 750 {
mbed_official 107:414e9c822e99 751 PMC->PMC_PCER0 = PMC_MASK_STATUS0;
mbed_official 107:414e9c822e99 752 while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
mbed_official 107:414e9c822e99 753
mbed_official 107:414e9c822e99 754 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
mbed_official 107:414e9c822e99 755 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 756 PMC->PMC_PCER1 = PMC_MASK_STATUS1;
mbed_official 107:414e9c822e99 757 while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
mbed_official 107:414e9c822e99 758 #endif
mbed_official 107:414e9c822e99 759 }
mbed_official 107:414e9c822e99 760
mbed_official 107:414e9c822e99 761 /**
mbed_official 107:414e9c822e99 762 * \brief Disable all peripheral clocks.
mbed_official 107:414e9c822e99 763 */
mbed_official 107:414e9c822e99 764 void pmc_disable_all_periph_clk(void)
mbed_official 107:414e9c822e99 765 {
mbed_official 107:414e9c822e99 766 PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
mbed_official 107:414e9c822e99 767 while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
mbed_official 107:414e9c822e99 768
mbed_official 107:414e9c822e99 769 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
mbed_official 107:414e9c822e99 770 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 771 PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
mbed_official 107:414e9c822e99 772 while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
mbed_official 107:414e9c822e99 773 #endif
mbed_official 107:414e9c822e99 774 }
mbed_official 107:414e9c822e99 775
mbed_official 107:414e9c822e99 776 /**
mbed_official 107:414e9c822e99 777 * \brief Check if the specified peripheral clock is enabled.
mbed_official 107:414e9c822e99 778 *
mbed_official 107:414e9c822e99 779 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
mbed_official 107:414e9c822e99 780 *
mbed_official 107:414e9c822e99 781 * \param ul_id Peripheral ID (ID_xxx).
mbed_official 107:414e9c822e99 782 *
mbed_official 107:414e9c822e99 783 * \retval 0 Peripheral clock is disabled or unknown.
mbed_official 107:414e9c822e99 784 * \retval 1 Peripheral clock is enabled.
mbed_official 107:414e9c822e99 785 */
mbed_official 107:414e9c822e99 786 uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
mbed_official 107:414e9c822e99 787 {
mbed_official 107:414e9c822e99 788 if (ul_id > MAX_PERIPH_ID) {
mbed_official 107:414e9c822e99 789 return 0;
mbed_official 107:414e9c822e99 790 }
mbed_official 107:414e9c822e99 791
mbed_official 107:414e9c822e99 792 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
mbed_official 107:414e9c822e99 793 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 794 if (ul_id < 32) {
mbed_official 107:414e9c822e99 795 #endif
mbed_official 107:414e9c822e99 796 if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
mbed_official 107:414e9c822e99 797 return 1;
mbed_official 107:414e9c822e99 798 } else {
mbed_official 107:414e9c822e99 799 return 0;
mbed_official 107:414e9c822e99 800 }
mbed_official 107:414e9c822e99 801 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
mbed_official 107:414e9c822e99 802 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 803 } else {
mbed_official 107:414e9c822e99 804 ul_id -= 32;
mbed_official 107:414e9c822e99 805 if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
mbed_official 107:414e9c822e99 806 return 1;
mbed_official 107:414e9c822e99 807 } else {
mbed_official 107:414e9c822e99 808 return 0;
mbed_official 107:414e9c822e99 809 }
mbed_official 107:414e9c822e99 810 }
mbed_official 107:414e9c822e99 811 #endif
mbed_official 107:414e9c822e99 812 }
mbed_official 107:414e9c822e99 813
mbed_official 107:414e9c822e99 814 /**
mbed_official 107:414e9c822e99 815 * \brief Set the prescaler for the specified programmable clock.
mbed_official 107:414e9c822e99 816 *
mbed_official 107:414e9c822e99 817 * \param ul_id Peripheral ID.
mbed_official 107:414e9c822e99 818 * \param ul_pres Prescaler value.
mbed_official 107:414e9c822e99 819 */
mbed_official 107:414e9c822e99 820 void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 821 {
mbed_official 107:414e9c822e99 822 PMC->PMC_PCK[ul_id] =
mbed_official 107:414e9c822e99 823 (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
mbed_official 107:414e9c822e99 824 while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
mbed_official 107:414e9c822e99 825 && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
mbed_official 107:414e9c822e99 826 }
mbed_official 107:414e9c822e99 827
mbed_official 107:414e9c822e99 828 /**
mbed_official 107:414e9c822e99 829 * \brief Set the source oscillator for the specified programmable clock.
mbed_official 107:414e9c822e99 830 *
mbed_official 107:414e9c822e99 831 * \param ul_id Peripheral ID.
mbed_official 107:414e9c822e99 832 * \param ul_source Source selection value.
mbed_official 107:414e9c822e99 833 */
mbed_official 107:414e9c822e99 834 void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
mbed_official 107:414e9c822e99 835 {
mbed_official 107:414e9c822e99 836 PMC->PMC_PCK[ul_id] =
mbed_official 107:414e9c822e99 837 (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
mbed_official 107:414e9c822e99 838 while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
mbed_official 107:414e9c822e99 839 && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
mbed_official 107:414e9c822e99 840 }
mbed_official 107:414e9c822e99 841
mbed_official 107:414e9c822e99 842 /**
mbed_official 107:414e9c822e99 843 * \brief Switch programmable clock source selection to slow clock.
mbed_official 107:414e9c822e99 844 *
mbed_official 107:414e9c822e99 845 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 846 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 847 *
mbed_official 107:414e9c822e99 848 * \retval 0 Success.
mbed_official 107:414e9c822e99 849 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 850 */
mbed_official 107:414e9c822e99 851 uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 852 {
mbed_official 107:414e9c822e99 853 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 854
mbed_official 107:414e9c822e99 855 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
mbed_official 107:414e9c822e99 856 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 857 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
mbed_official 107:414e9c822e99 858 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 859 return 1;
mbed_official 107:414e9c822e99 860 }
mbed_official 107:414e9c822e99 861 }
mbed_official 107:414e9c822e99 862
mbed_official 107:414e9c822e99 863 return 0;
mbed_official 107:414e9c822e99 864 }
mbed_official 107:414e9c822e99 865
mbed_official 107:414e9c822e99 866 /**
mbed_official 107:414e9c822e99 867 * \brief Switch programmable clock source selection to main clock.
mbed_official 107:414e9c822e99 868 *
mbed_official 107:414e9c822e99 869 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 870 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 871 *
mbed_official 107:414e9c822e99 872 * \retval 0 Success.
mbed_official 107:414e9c822e99 873 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 874 */
mbed_official 107:414e9c822e99 875 uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 876 {
mbed_official 107:414e9c822e99 877 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 878
mbed_official 107:414e9c822e99 879 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
mbed_official 107:414e9c822e99 880 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 881 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
mbed_official 107:414e9c822e99 882 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 883 return 1;
mbed_official 107:414e9c822e99 884 }
mbed_official 107:414e9c822e99 885 }
mbed_official 107:414e9c822e99 886
mbed_official 107:414e9c822e99 887 return 0;
mbed_official 107:414e9c822e99 888 }
mbed_official 107:414e9c822e99 889
mbed_official 107:414e9c822e99 890 /**
mbed_official 107:414e9c822e99 891 * \brief Switch programmable clock source selection to PLLA clock.
mbed_official 107:414e9c822e99 892 *
mbed_official 107:414e9c822e99 893 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 894 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 895 *
mbed_official 107:414e9c822e99 896 * \retval 0 Success.
mbed_official 107:414e9c822e99 897 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 898 */
mbed_official 107:414e9c822e99 899 uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 900 {
mbed_official 107:414e9c822e99 901 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 902
mbed_official 107:414e9c822e99 903 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
mbed_official 107:414e9c822e99 904 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 905 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
mbed_official 107:414e9c822e99 906 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 907 return 1;
mbed_official 107:414e9c822e99 908 }
mbed_official 107:414e9c822e99 909 }
mbed_official 107:414e9c822e99 910
mbed_official 107:414e9c822e99 911 return 0;
mbed_official 107:414e9c822e99 912 }
mbed_official 107:414e9c822e99 913
mbed_official 107:414e9c822e99 914 #if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
mbed_official 107:414e9c822e99 915 /**
mbed_official 107:414e9c822e99 916 * \brief Switch programmable clock source selection to PLLB clock.
mbed_official 107:414e9c822e99 917 *
mbed_official 107:414e9c822e99 918 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 919 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 920 *
mbed_official 107:414e9c822e99 921 * \retval 0 Success.
mbed_official 107:414e9c822e99 922 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 923 */
mbed_official 107:414e9c822e99 924 uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 925 {
mbed_official 107:414e9c822e99 926 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 927
mbed_official 107:414e9c822e99 928 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
mbed_official 107:414e9c822e99 929 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 930 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
mbed_official 107:414e9c822e99 931 --ul_timeout) {
mbed_official 107:414e9c822e99 932 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 933 return 1;
mbed_official 107:414e9c822e99 934 }
mbed_official 107:414e9c822e99 935 }
mbed_official 107:414e9c822e99 936
mbed_official 107:414e9c822e99 937 return 0;
mbed_official 107:414e9c822e99 938 }
mbed_official 107:414e9c822e99 939 #endif
mbed_official 107:414e9c822e99 940
mbed_official 107:414e9c822e99 941 #if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 942 /**
mbed_official 107:414e9c822e99 943 * \brief Switch programmable clock source selection to UPLL clock.
mbed_official 107:414e9c822e99 944 *
mbed_official 107:414e9c822e99 945 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 946 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 947 *
mbed_official 107:414e9c822e99 948 * \retval 0 Success.
mbed_official 107:414e9c822e99 949 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 950 */
mbed_official 107:414e9c822e99 951 uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 952 {
mbed_official 107:414e9c822e99 953 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 954
mbed_official 107:414e9c822e99 955 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
mbed_official 107:414e9c822e99 956 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 957 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
mbed_official 107:414e9c822e99 958 --ul_timeout) {
mbed_official 107:414e9c822e99 959 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 960 return 1;
mbed_official 107:414e9c822e99 961 }
mbed_official 107:414e9c822e99 962 }
mbed_official 107:414e9c822e99 963
mbed_official 107:414e9c822e99 964 return 0;
mbed_official 107:414e9c822e99 965 }
mbed_official 107:414e9c822e99 966 #endif
mbed_official 107:414e9c822e99 967
mbed_official 107:414e9c822e99 968 /**
mbed_official 107:414e9c822e99 969 * \brief Switch programmable clock source selection to mck.
mbed_official 107:414e9c822e99 970 *
mbed_official 107:414e9c822e99 971 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 972 * \param ul_pres Programmable clock prescaler.
mbed_official 107:414e9c822e99 973 *
mbed_official 107:414e9c822e99 974 * \retval 0 Success.
mbed_official 107:414e9c822e99 975 * \retval 1 Timeout error.
mbed_official 107:414e9c822e99 976 */
mbed_official 107:414e9c822e99 977 uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
mbed_official 107:414e9c822e99 978 {
mbed_official 107:414e9c822e99 979 uint32_t ul_timeout;
mbed_official 107:414e9c822e99 980
mbed_official 107:414e9c822e99 981 PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
mbed_official 107:414e9c822e99 982 for (ul_timeout = PMC_TIMEOUT;
mbed_official 107:414e9c822e99 983 !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
mbed_official 107:414e9c822e99 984 if (ul_timeout == 0) {
mbed_official 107:414e9c822e99 985 return 1;
mbed_official 107:414e9c822e99 986 }
mbed_official 107:414e9c822e99 987 }
mbed_official 107:414e9c822e99 988
mbed_official 107:414e9c822e99 989 return 0;
mbed_official 107:414e9c822e99 990 }
mbed_official 107:414e9c822e99 991
mbed_official 107:414e9c822e99 992 /**
mbed_official 107:414e9c822e99 993 * \brief Enable the specified programmable clock.
mbed_official 107:414e9c822e99 994 *
mbed_official 107:414e9c822e99 995 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 996 */
mbed_official 107:414e9c822e99 997 void pmc_enable_pck(uint32_t ul_id)
mbed_official 107:414e9c822e99 998 {
mbed_official 107:414e9c822e99 999 PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
mbed_official 107:414e9c822e99 1000 }
mbed_official 107:414e9c822e99 1001
mbed_official 107:414e9c822e99 1002 /**
mbed_official 107:414e9c822e99 1003 * \brief Disable the specified programmable clock.
mbed_official 107:414e9c822e99 1004 *
mbed_official 107:414e9c822e99 1005 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 1006 */
mbed_official 107:414e9c822e99 1007 void pmc_disable_pck(uint32_t ul_id)
mbed_official 107:414e9c822e99 1008 {
mbed_official 107:414e9c822e99 1009 PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
mbed_official 107:414e9c822e99 1010 }
mbed_official 107:414e9c822e99 1011
mbed_official 107:414e9c822e99 1012 /**
mbed_official 107:414e9c822e99 1013 * \brief Enable all programmable clocks.
mbed_official 107:414e9c822e99 1014 */
mbed_official 107:414e9c822e99 1015 void pmc_enable_all_pck(void)
mbed_official 107:414e9c822e99 1016 {
mbed_official 107:414e9c822e99 1017 PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
mbed_official 107:414e9c822e99 1018 }
mbed_official 107:414e9c822e99 1019
mbed_official 107:414e9c822e99 1020 /**
mbed_official 107:414e9c822e99 1021 * \brief Disable all programmable clocks.
mbed_official 107:414e9c822e99 1022 */
mbed_official 107:414e9c822e99 1023 void pmc_disable_all_pck(void)
mbed_official 107:414e9c822e99 1024 {
mbed_official 107:414e9c822e99 1025 PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
mbed_official 107:414e9c822e99 1026 }
mbed_official 107:414e9c822e99 1027
mbed_official 107:414e9c822e99 1028 /**
mbed_official 107:414e9c822e99 1029 * \brief Check if the specified programmable clock is enabled.
mbed_official 107:414e9c822e99 1030 *
mbed_official 107:414e9c822e99 1031 * \param ul_id Id of the programmable clock.
mbed_official 107:414e9c822e99 1032 *
mbed_official 107:414e9c822e99 1033 * \retval 0 Programmable clock is disabled or unknown.
mbed_official 107:414e9c822e99 1034 * \retval 1 Programmable clock is enabled.
mbed_official 107:414e9c822e99 1035 */
mbed_official 107:414e9c822e99 1036 uint32_t pmc_is_pck_enabled(uint32_t ul_id)
mbed_official 107:414e9c822e99 1037 {
mbed_official 107:414e9c822e99 1038 if (ul_id > 2) {
mbed_official 107:414e9c822e99 1039 return 0;
mbed_official 107:414e9c822e99 1040 }
mbed_official 107:414e9c822e99 1041
mbed_official 107:414e9c822e99 1042 return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
mbed_official 107:414e9c822e99 1043 }
mbed_official 107:414e9c822e99 1044
mbed_official 107:414e9c822e99 1045 #if (SAM4C || SAM4CM || SAM4CP)
mbed_official 107:414e9c822e99 1046 /**
mbed_official 107:414e9c822e99 1047 * \brief Enable Coprocessor Clocks.
mbed_official 107:414e9c822e99 1048 */
mbed_official 107:414e9c822e99 1049 void pmc_enable_cpck(void)
mbed_official 107:414e9c822e99 1050 {
mbed_official 107:414e9c822e99 1051 PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
mbed_official 107:414e9c822e99 1052 }
mbed_official 107:414e9c822e99 1053
mbed_official 107:414e9c822e99 1054 /**
mbed_official 107:414e9c822e99 1055 * \brief Disable Coprocessor Clocks.
mbed_official 107:414e9c822e99 1056 */
mbed_official 107:414e9c822e99 1057 void pmc_disable_cpck(void)
mbed_official 107:414e9c822e99 1058 {
mbed_official 107:414e9c822e99 1059 PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
mbed_official 107:414e9c822e99 1060 }
mbed_official 107:414e9c822e99 1061
mbed_official 107:414e9c822e99 1062 /**
mbed_official 107:414e9c822e99 1063 * \brief Check if the Coprocessor Clocks is enabled.
mbed_official 107:414e9c822e99 1064 *
mbed_official 107:414e9c822e99 1065 * \retval 0 Coprocessor Clocks is disabled.
mbed_official 107:414e9c822e99 1066 * \retval 1 Coprocessor Clocks is enabled.
mbed_official 107:414e9c822e99 1067 */
mbed_official 107:414e9c822e99 1068 bool pmc_is_cpck_enabled(void)
mbed_official 107:414e9c822e99 1069 {
mbed_official 107:414e9c822e99 1070 if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
mbed_official 107:414e9c822e99 1071 return 1;
mbed_official 107:414e9c822e99 1072 } else {
mbed_official 107:414e9c822e99 1073 return 0;
mbed_official 107:414e9c822e99 1074 }
mbed_official 107:414e9c822e99 1075 }
mbed_official 107:414e9c822e99 1076
mbed_official 107:414e9c822e99 1077 /**
mbed_official 107:414e9c822e99 1078 * \brief Enable Coprocessor Bus Master Clocks.
mbed_official 107:414e9c822e99 1079 */
mbed_official 107:414e9c822e99 1080 void pmc_enable_cpbmck(void)
mbed_official 107:414e9c822e99 1081 {
mbed_official 107:414e9c822e99 1082 PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
mbed_official 107:414e9c822e99 1083 }
mbed_official 107:414e9c822e99 1084
mbed_official 107:414e9c822e99 1085 /**
mbed_official 107:414e9c822e99 1086 * \brief Disable Coprocessor Bus Master Clocks.
mbed_official 107:414e9c822e99 1087 */
mbed_official 107:414e9c822e99 1088 void pmc_disable_cpbmck(void)
mbed_official 107:414e9c822e99 1089 {
mbed_official 107:414e9c822e99 1090 PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
mbed_official 107:414e9c822e99 1091 }
mbed_official 107:414e9c822e99 1092
mbed_official 107:414e9c822e99 1093 /**
mbed_official 107:414e9c822e99 1094 * \brief Check if the Coprocessor Bus Master Clocks is enabled.
mbed_official 107:414e9c822e99 1095 *
mbed_official 107:414e9c822e99 1096 * \retval 0 Coprocessor Bus Master Clocks is disabled.
mbed_official 107:414e9c822e99 1097 * \retval 1 Coprocessor Bus Master Clocks is enabled.
mbed_official 107:414e9c822e99 1098 */
mbed_official 107:414e9c822e99 1099 bool pmc_is_cpbmck_enabled(void)
mbed_official 107:414e9c822e99 1100 {
mbed_official 107:414e9c822e99 1101 if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
mbed_official 107:414e9c822e99 1102 return 1;
mbed_official 107:414e9c822e99 1103 } else {
mbed_official 107:414e9c822e99 1104 return 0;
mbed_official 107:414e9c822e99 1105 }
mbed_official 107:414e9c822e99 1106 }
mbed_official 107:414e9c822e99 1107
mbed_official 107:414e9c822e99 1108 /**
mbed_official 107:414e9c822e99 1109 * \brief Set the prescaler for the Coprocessor Master Clock.
mbed_official 107:414e9c822e99 1110 *
mbed_official 107:414e9c822e99 1111 * \param ul_pres Prescaler value.
mbed_official 107:414e9c822e99 1112 */
mbed_official 107:414e9c822e99 1113 void pmc_cpck_set_prescaler(uint32_t ul_pres)
mbed_official 107:414e9c822e99 1114 {
mbed_official 107:414e9c822e99 1115 PMC->PMC_MCKR =
mbed_official 107:414e9c822e99 1116 (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
mbed_official 107:414e9c822e99 1117 }
mbed_official 107:414e9c822e99 1118
mbed_official 107:414e9c822e99 1119 /**
mbed_official 107:414e9c822e99 1120 * \brief Set the source for the Coprocessor Master Clock.
mbed_official 107:414e9c822e99 1121 *
mbed_official 107:414e9c822e99 1122 * \param ul_source Source selection value.
mbed_official 107:414e9c822e99 1123 */
mbed_official 107:414e9c822e99 1124 void pmc_cpck_set_source(uint32_t ul_source)
mbed_official 107:414e9c822e99 1125 {
mbed_official 107:414e9c822e99 1126 PMC->PMC_MCKR =
mbed_official 107:414e9c822e99 1127 (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
mbed_official 107:414e9c822e99 1128 }
mbed_official 107:414e9c822e99 1129 #endif
mbed_official 107:414e9c822e99 1130
mbed_official 107:414e9c822e99 1131 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1132 /**
mbed_official 107:414e9c822e99 1133 * \brief Switch UDP (USB) clock source selection to PLLA clock.
mbed_official 107:414e9c822e99 1134 *
mbed_official 107:414e9c822e99 1135 * \param ul_usbdiv Clock divisor.
mbed_official 107:414e9c822e99 1136 */
mbed_official 107:414e9c822e99 1137 void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
mbed_official 107:414e9c822e99 1138 {
mbed_official 107:414e9c822e99 1139 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
mbed_official 107:414e9c822e99 1140 }
mbed_official 107:414e9c822e99 1141 #endif
mbed_official 107:414e9c822e99 1142
mbed_official 107:414e9c822e99 1143 #if (SAM3S || SAM4S || SAMG55)
mbed_official 107:414e9c822e99 1144 /**
mbed_official 107:414e9c822e99 1145 * \brief Switch UDP (USB) clock source selection to PLLB clock.
mbed_official 107:414e9c822e99 1146 *
mbed_official 107:414e9c822e99 1147 * \param ul_usbdiv Clock divisor.
mbed_official 107:414e9c822e99 1148 */
mbed_official 107:414e9c822e99 1149 void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
mbed_official 107:414e9c822e99 1150 {
mbed_official 107:414e9c822e99 1151 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
mbed_official 107:414e9c822e99 1152 }
mbed_official 107:414e9c822e99 1153 #endif
mbed_official 107:414e9c822e99 1154
mbed_official 107:414e9c822e99 1155 #if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1156 /**
mbed_official 107:414e9c822e99 1157 * \brief Switch UDP (USB) clock source selection to UPLL clock.
mbed_official 107:414e9c822e99 1158 *
mbed_official 107:414e9c822e99 1159 * \param ul_usbdiv Clock divisor.
mbed_official 107:414e9c822e99 1160 */
mbed_official 107:414e9c822e99 1161 void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
mbed_official 107:414e9c822e99 1162 {
mbed_official 107:414e9c822e99 1163 PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
mbed_official 107:414e9c822e99 1164 }
mbed_official 107:414e9c822e99 1165 #endif
mbed_official 107:414e9c822e99 1166
mbed_official 107:414e9c822e99 1167 #if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1168 /**
mbed_official 107:414e9c822e99 1169 * \brief Enable UDP (USB) clock.
mbed_official 107:414e9c822e99 1170 */
mbed_official 107:414e9c822e99 1171 void pmc_enable_udpck(void)
mbed_official 107:414e9c822e99 1172 {
mbed_official 107:414e9c822e99 1173 #if (SAM3S || SAM4S || SAM4E || SAMG55)
mbed_official 107:414e9c822e99 1174 PMC->PMC_SCER = PMC_SCER_UDP;
mbed_official 107:414e9c822e99 1175 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1176 PMC->PMC_SCER = PMC_SCER_USBCLK;
mbed_official 107:414e9c822e99 1177 #else
mbed_official 107:414e9c822e99 1178 PMC->PMC_SCER = PMC_SCER_UOTGCLK;
mbed_official 107:414e9c822e99 1179 # endif
mbed_official 107:414e9c822e99 1180 }
mbed_official 107:414e9c822e99 1181
mbed_official 107:414e9c822e99 1182 /**
mbed_official 107:414e9c822e99 1183 * \brief Disable UDP (USB) clock.
mbed_official 107:414e9c822e99 1184 */
mbed_official 107:414e9c822e99 1185 void pmc_disable_udpck(void)
mbed_official 107:414e9c822e99 1186 {
mbed_official 107:414e9c822e99 1187 #if (SAM3S || SAM4S || SAM4E || SAMG55)
mbed_official 107:414e9c822e99 1188 PMC->PMC_SCDR = PMC_SCDR_UDP;
mbed_official 107:414e9c822e99 1189 #elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1190 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
mbed_official 107:414e9c822e99 1191 #else
mbed_official 107:414e9c822e99 1192 PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
mbed_official 107:414e9c822e99 1193 # endif
mbed_official 107:414e9c822e99 1194 }
mbed_official 107:414e9c822e99 1195 #endif
mbed_official 107:414e9c822e99 1196
mbed_official 107:414e9c822e99 1197 #if SAMG55
mbed_official 107:414e9c822e99 1198 /**
mbed_official 107:414e9c822e99 1199 * \brief Switch UHP (USB) clock source selection to PLLA clock.
mbed_official 107:414e9c822e99 1200 *
mbed_official 107:414e9c822e99 1201 * \param ul_usbdiv Clock divisor.
mbed_official 107:414e9c822e99 1202 */
mbed_official 107:414e9c822e99 1203 void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
mbed_official 107:414e9c822e99 1204 {
mbed_official 107:414e9c822e99 1205 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
mbed_official 107:414e9c822e99 1206 }
mbed_official 107:414e9c822e99 1207
mbed_official 107:414e9c822e99 1208 /**
mbed_official 107:414e9c822e99 1209 * \brief Switch UHP (USB) clock source selection to PLLB clock.
mbed_official 107:414e9c822e99 1210 *
mbed_official 107:414e9c822e99 1211 * \param ul_usbdiv Clock divisor.
mbed_official 107:414e9c822e99 1212 */
mbed_official 107:414e9c822e99 1213 void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
mbed_official 107:414e9c822e99 1214 {
mbed_official 107:414e9c822e99 1215 PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
mbed_official 107:414e9c822e99 1216 }
mbed_official 107:414e9c822e99 1217
mbed_official 107:414e9c822e99 1218 /**
mbed_official 107:414e9c822e99 1219 * \brief Enable UHP (USB) clock.
mbed_official 107:414e9c822e99 1220 */
mbed_official 107:414e9c822e99 1221 void pmc_enable_uhpck(void)
mbed_official 107:414e9c822e99 1222 {
mbed_official 107:414e9c822e99 1223 PMC->PMC_SCER = PMC_SCER_UHP;
mbed_official 107:414e9c822e99 1224 }
mbed_official 107:414e9c822e99 1225 #endif
mbed_official 107:414e9c822e99 1226
mbed_official 107:414e9c822e99 1227 /**
mbed_official 107:414e9c822e99 1228 * \brief Enable PMC interrupts.
mbed_official 107:414e9c822e99 1229 *
mbed_official 107:414e9c822e99 1230 * \param ul_sources Interrupt sources bit map.
mbed_official 107:414e9c822e99 1231 */
mbed_official 107:414e9c822e99 1232 void pmc_enable_interrupt(uint32_t ul_sources)
mbed_official 107:414e9c822e99 1233 {
mbed_official 107:414e9c822e99 1234 PMC->PMC_IER = ul_sources;
mbed_official 107:414e9c822e99 1235 }
mbed_official 107:414e9c822e99 1236
mbed_official 107:414e9c822e99 1237 /**
mbed_official 107:414e9c822e99 1238 * \brief Disable PMC interrupts.
mbed_official 107:414e9c822e99 1239 *
mbed_official 107:414e9c822e99 1240 * \param ul_sources Interrupt sources bit map.
mbed_official 107:414e9c822e99 1241 */
mbed_official 107:414e9c822e99 1242 void pmc_disable_interrupt(uint32_t ul_sources)
mbed_official 107:414e9c822e99 1243 {
mbed_official 107:414e9c822e99 1244 PMC->PMC_IDR = ul_sources;
mbed_official 107:414e9c822e99 1245 }
mbed_official 107:414e9c822e99 1246
mbed_official 107:414e9c822e99 1247 /**
mbed_official 107:414e9c822e99 1248 * \brief Get PMC interrupt mask.
mbed_official 107:414e9c822e99 1249 *
mbed_official 107:414e9c822e99 1250 * \return The interrupt mask value.
mbed_official 107:414e9c822e99 1251 */
mbed_official 107:414e9c822e99 1252 uint32_t pmc_get_interrupt_mask(void)
mbed_official 107:414e9c822e99 1253 {
mbed_official 107:414e9c822e99 1254 return PMC->PMC_IMR;
mbed_official 107:414e9c822e99 1255 }
mbed_official 107:414e9c822e99 1256
mbed_official 107:414e9c822e99 1257 /**
mbed_official 107:414e9c822e99 1258 * \brief Get current status.
mbed_official 107:414e9c822e99 1259 *
mbed_official 107:414e9c822e99 1260 * \return The current PMC status.
mbed_official 107:414e9c822e99 1261 */
mbed_official 107:414e9c822e99 1262 uint32_t pmc_get_status(void)
mbed_official 107:414e9c822e99 1263 {
mbed_official 107:414e9c822e99 1264 return PMC->PMC_SR;
mbed_official 107:414e9c822e99 1265 }
mbed_official 107:414e9c822e99 1266
mbed_official 107:414e9c822e99 1267 /**
mbed_official 107:414e9c822e99 1268 * \brief Set the wake-up inputs for fast startup mode registers
mbed_official 107:414e9c822e99 1269 * (event generation).
mbed_official 107:414e9c822e99 1270 *
mbed_official 107:414e9c822e99 1271 * \param ul_inputs Wake up inputs to enable.
mbed_official 107:414e9c822e99 1272 */
mbed_official 107:414e9c822e99 1273 void pmc_set_fast_startup_input(uint32_t ul_inputs)
mbed_official 107:414e9c822e99 1274 {
mbed_official 107:414e9c822e99 1275 ul_inputs &= PMC_FAST_STARTUP_Msk;
mbed_official 107:414e9c822e99 1276 PMC->PMC_FSMR |= ul_inputs;
mbed_official 107:414e9c822e99 1277 }
mbed_official 107:414e9c822e99 1278
mbed_official 107:414e9c822e99 1279 /**
mbed_official 107:414e9c822e99 1280 * \brief Clear the wake-up inputs for fast startup mode registers
mbed_official 107:414e9c822e99 1281 * (remove event generation).
mbed_official 107:414e9c822e99 1282 *
mbed_official 107:414e9c822e99 1283 * \param ul_inputs Wake up inputs to disable.
mbed_official 107:414e9c822e99 1284 */
mbed_official 107:414e9c822e99 1285 void pmc_clr_fast_startup_input(uint32_t ul_inputs)
mbed_official 107:414e9c822e99 1286 {
mbed_official 107:414e9c822e99 1287 ul_inputs &= PMC_FAST_STARTUP_Msk;
mbed_official 107:414e9c822e99 1288 PMC->PMC_FSMR &= ~ul_inputs;
mbed_official 107:414e9c822e99 1289 }
mbed_official 107:414e9c822e99 1290
mbed_official 107:414e9c822e99 1291 #if (SAM4C || SAM4CM || SAM4CP)
mbed_official 107:414e9c822e99 1292 /**
mbed_official 107:414e9c822e99 1293 * \brief Set the wake-up inputs of coprocessor for fast startup mode registers
mbed_official 107:414e9c822e99 1294 * (event generation).
mbed_official 107:414e9c822e99 1295 *
mbed_official 107:414e9c822e99 1296 * \param ul_inputs Wake up inputs to enable.
mbed_official 107:414e9c822e99 1297 */
mbed_official 107:414e9c822e99 1298 void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
mbed_official 107:414e9c822e99 1299 {
mbed_official 107:414e9c822e99 1300 ul_inputs &= PMC_FAST_STARTUP_Msk;
mbed_official 107:414e9c822e99 1301 PMC->PMC_CPFSMR |= ul_inputs;
mbed_official 107:414e9c822e99 1302 }
mbed_official 107:414e9c822e99 1303
mbed_official 107:414e9c822e99 1304 /**
mbed_official 107:414e9c822e99 1305 * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers
mbed_official 107:414e9c822e99 1306 * (remove event generation).
mbed_official 107:414e9c822e99 1307 *
mbed_official 107:414e9c822e99 1308 * \param ul_inputs Wake up inputs to disable.
mbed_official 107:414e9c822e99 1309 */
mbed_official 107:414e9c822e99 1310 void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
mbed_official 107:414e9c822e99 1311 {
mbed_official 107:414e9c822e99 1312 ul_inputs &= PMC_FAST_STARTUP_Msk;
mbed_official 107:414e9c822e99 1313 PMC->PMC_CPFSMR &= ~ul_inputs;
mbed_official 107:414e9c822e99 1314 }
mbed_official 107:414e9c822e99 1315 #endif
mbed_official 107:414e9c822e99 1316
mbed_official 107:414e9c822e99 1317 #if (!(SAMG51 || SAMG53 || SAMG54))
mbed_official 107:414e9c822e99 1318 /**
mbed_official 107:414e9c822e99 1319 * \brief Enable Sleep Mode.
mbed_official 107:414e9c822e99 1320 * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
mbed_official 107:414e9c822e99 1321 *
mbed_official 107:414e9c822e99 1322 * \param uc_type 0 for wait for interrupt, 1 for wait for event.
mbed_official 107:414e9c822e99 1323 * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series,
mbed_official 107:414e9c822e99 1324 * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0.
mbed_official 107:414e9c822e99 1325 */
mbed_official 107:414e9c822e99 1326 void pmc_enable_sleepmode(uint8_t uc_type)
mbed_official 107:414e9c822e99 1327 {
mbed_official 107:414e9c822e99 1328 #if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1329 PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
mbed_official 107:414e9c822e99 1330 #endif
mbed_official 107:414e9c822e99 1331 SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
mbed_official 107:414e9c822e99 1332
mbed_official 107:414e9c822e99 1333 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1334 UNUSED(uc_type);
mbed_official 107:414e9c822e99 1335 __WFI();
mbed_official 107:414e9c822e99 1336 #else
mbed_official 107:414e9c822e99 1337 if (uc_type == 0) {
mbed_official 107:414e9c822e99 1338 __WFI();
mbed_official 107:414e9c822e99 1339 } else {
mbed_official 107:414e9c822e99 1340 __WFE();
mbed_official 107:414e9c822e99 1341 }
mbed_official 107:414e9c822e99 1342 #endif
mbed_official 107:414e9c822e99 1343 }
mbed_official 107:414e9c822e99 1344 #endif
mbed_official 107:414e9c822e99 1345
mbed_official 107:414e9c822e99 1346 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1347 static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
mbed_official 107:414e9c822e99 1348 /**
mbed_official 107:414e9c822e99 1349 * \brief Set the embedded flash state in wait mode
mbed_official 107:414e9c822e99 1350 *
mbed_official 107:414e9c822e99 1351 * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,
mbed_official 107:414e9c822e99 1352 * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.
mbed_official 107:414e9c822e99 1353 */
mbed_official 107:414e9c822e99 1354 void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
mbed_official 107:414e9c822e99 1355 {
mbed_official 107:414e9c822e99 1356 ul_flash_in_wait_mode = ul_flash_state;
mbed_official 107:414e9c822e99 1357 }
mbed_official 107:414e9c822e99 1358
mbed_official 107:414e9c822e99 1359 /**
mbed_official 107:414e9c822e99 1360 * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
mbed_official 107:414e9c822e99 1361 *
mbed_official 107:414e9c822e99 1362 * \note In this function, FLPM will retain, WAITMODE bit will be set,
mbed_official 107:414e9c822e99 1363 * Generally, this function will be called by pmc_sleep() in order to
mbed_official 107:414e9c822e99 1364 * complete all sequence entering wait mode.
mbed_official 107:414e9c822e99 1365 * See \ref pmc_sleep() for entering different sleep modes.
mbed_official 107:414e9c822e99 1366 */
mbed_official 107:414e9c822e99 1367 void pmc_enable_waitmode(void)
mbed_official 107:414e9c822e99 1368 {
mbed_official 107:414e9c822e99 1369 uint32_t i;
mbed_official 107:414e9c822e99 1370
mbed_official 107:414e9c822e99 1371 /* Flash in wait mode */
mbed_official 107:414e9c822e99 1372 i = PMC->PMC_FSMR;
mbed_official 107:414e9c822e99 1373 i &= ~PMC_FSMR_FLPM_Msk;
mbed_official 107:414e9c822e99 1374 i |= ul_flash_in_wait_mode;
mbed_official 107:414e9c822e99 1375 PMC->PMC_FSMR = i;
mbed_official 107:414e9c822e99 1376
mbed_official 107:414e9c822e99 1377 /* Set the WAITMODE bit = 1 */
mbed_official 107:414e9c822e99 1378 PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
mbed_official 107:414e9c822e99 1379
mbed_official 107:414e9c822e99 1380 /* Waiting for Master Clock Ready MCKRDY = 1 */
mbed_official 107:414e9c822e99 1381 while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
mbed_official 107:414e9c822e99 1382
mbed_official 107:414e9c822e99 1383 /* Waiting for MOSCRCEN bit cleared is strongly recommended
mbed_official 107:414e9c822e99 1384 * to ensure that the core will not execute undesired instructions
mbed_official 107:414e9c822e99 1385 */
mbed_official 107:414e9c822e99 1386 for (i = 0; i < 500; i++) {
mbed_official 107:414e9c822e99 1387 __NOP();
mbed_official 107:414e9c822e99 1388 }
mbed_official 107:414e9c822e99 1389 while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
mbed_official 107:414e9c822e99 1390
mbed_official 107:414e9c822e99 1391 #if (!SAMG)
mbed_official 107:414e9c822e99 1392 /* Restore Flash in idle mode */
mbed_official 107:414e9c822e99 1393 i = PMC->PMC_FSMR;
mbed_official 107:414e9c822e99 1394 i &= ~PMC_FSMR_FLPM_Msk;
mbed_official 107:414e9c822e99 1395 i |= PMC_WAIT_MODE_FLASH_IDLE;
mbed_official 107:414e9c822e99 1396 PMC->PMC_FSMR = i;
mbed_official 107:414e9c822e99 1397 #endif
mbed_official 107:414e9c822e99 1398 }
mbed_official 107:414e9c822e99 1399 #else
mbed_official 107:414e9c822e99 1400 /**
mbed_official 107:414e9c822e99 1401 * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +
mbed_official 107:414e9c822e99 1402 * (LPM bit = 1)
mbed_official 107:414e9c822e99 1403 */
mbed_official 107:414e9c822e99 1404 void pmc_enable_waitmode(void)
mbed_official 107:414e9c822e99 1405 {
mbed_official 107:414e9c822e99 1406 uint32_t i;
mbed_official 107:414e9c822e99 1407
mbed_official 107:414e9c822e99 1408 PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
mbed_official 107:414e9c822e99 1409 SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
mbed_official 107:414e9c822e99 1410
mbed_official 107:414e9c822e99 1411 __WFE();
mbed_official 107:414e9c822e99 1412
mbed_official 107:414e9c822e99 1413 /* Waiting for MOSCRCEN bit cleared is strongly recommended
mbed_official 107:414e9c822e99 1414 * to ensure that the core will not execute undesired instructions
mbed_official 107:414e9c822e99 1415 */
mbed_official 107:414e9c822e99 1416 for (i = 0; i < 500; i++) {
mbed_official 107:414e9c822e99 1417 __NOP();
mbed_official 107:414e9c822e99 1418 }
mbed_official 107:414e9c822e99 1419 while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
mbed_official 107:414e9c822e99 1420
mbed_official 107:414e9c822e99 1421 }
mbed_official 107:414e9c822e99 1422 #endif
mbed_official 107:414e9c822e99 1423
mbed_official 107:414e9c822e99 1424 #if (!(SAMG51 || SAMG53 || SAMG54))
mbed_official 107:414e9c822e99 1425 /**
mbed_official 107:414e9c822e99 1426 * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +
mbed_official 107:414e9c822e99 1427 * (SLEEPDEEP bit = 1)
mbed_official 107:414e9c822e99 1428 */
mbed_official 107:414e9c822e99 1429 void pmc_enable_backupmode(void)
mbed_official 107:414e9c822e99 1430 {
mbed_official 107:414e9c822e99 1431 #if (SAM4C || SAM4CM || SAM4CP)
mbed_official 107:414e9c822e99 1432 uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
mbed_official 107:414e9c822e99 1433 SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
mbed_official 107:414e9c822e99 1434 while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
mbed_official 107:414e9c822e99 1435 #endif
mbed_official 107:414e9c822e99 1436 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
mbed_official 107:414e9c822e99 1437 #if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1438 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
mbed_official 107:414e9c822e99 1439 __WFE();
mbed_official 107:414e9c822e99 1440 __WFI();
mbed_official 107:414e9c822e99 1441 #else
mbed_official 107:414e9c822e99 1442 __WFE();
mbed_official 107:414e9c822e99 1443 #endif
mbed_official 107:414e9c822e99 1444 }
mbed_official 107:414e9c822e99 1445 #endif
mbed_official 107:414e9c822e99 1446
mbed_official 107:414e9c822e99 1447 /**
mbed_official 107:414e9c822e99 1448 * \brief Enable Clock Failure Detector.
mbed_official 107:414e9c822e99 1449 */
mbed_official 107:414e9c822e99 1450 void pmc_enable_clock_failure_detector(void)
mbed_official 107:414e9c822e99 1451 {
mbed_official 107:414e9c822e99 1452 uint32_t ul_reg = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 1453
mbed_official 107:414e9c822e99 1454 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
mbed_official 107:414e9c822e99 1455 }
mbed_official 107:414e9c822e99 1456
mbed_official 107:414e9c822e99 1457 /**
mbed_official 107:414e9c822e99 1458 * \brief Disable Clock Failure Detector.
mbed_official 107:414e9c822e99 1459 */
mbed_official 107:414e9c822e99 1460 void pmc_disable_clock_failure_detector(void)
mbed_official 107:414e9c822e99 1461 {
mbed_official 107:414e9c822e99 1462 uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
mbed_official 107:414e9c822e99 1463
mbed_official 107:414e9c822e99 1464 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
mbed_official 107:414e9c822e99 1465 }
mbed_official 107:414e9c822e99 1466
mbed_official 107:414e9c822e99 1467 #if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1468 /**
mbed_official 107:414e9c822e99 1469 * \brief Enable Slow Crystal Oscillator Frequency Monitoring.
mbed_official 107:414e9c822e99 1470 */
mbed_official 107:414e9c822e99 1471 void pmc_enable_sclk_osc_freq_monitor(void)
mbed_official 107:414e9c822e99 1472 {
mbed_official 107:414e9c822e99 1473 uint32_t ul_reg = PMC->CKGR_MOR;
mbed_official 107:414e9c822e99 1474
mbed_official 107:414e9c822e99 1475 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
mbed_official 107:414e9c822e99 1476 }
mbed_official 107:414e9c822e99 1477
mbed_official 107:414e9c822e99 1478 /**
mbed_official 107:414e9c822e99 1479 * \brief Disable Slow Crystal Oscillator Frequency Monitoring.
mbed_official 107:414e9c822e99 1480 */
mbed_official 107:414e9c822e99 1481 void pmc_disable_sclk_osc_freq_monitor(void)
mbed_official 107:414e9c822e99 1482 {
mbed_official 107:414e9c822e99 1483 uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
mbed_official 107:414e9c822e99 1484
mbed_official 107:414e9c822e99 1485 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
mbed_official 107:414e9c822e99 1486 }
mbed_official 107:414e9c822e99 1487 #endif
mbed_official 107:414e9c822e99 1488
mbed_official 107:414e9c822e99 1489 /**
mbed_official 107:414e9c822e99 1490 * \brief Enable or disable write protect of PMC registers.
mbed_official 107:414e9c822e99 1491 *
mbed_official 107:414e9c822e99 1492 * \param ul_enable 1 to enable, 0 to disable.
mbed_official 107:414e9c822e99 1493 */
mbed_official 107:414e9c822e99 1494 void pmc_set_writeprotect(uint32_t ul_enable)
mbed_official 107:414e9c822e99 1495 {
mbed_official 107:414e9c822e99 1496 if (ul_enable) {
mbed_official 107:414e9c822e99 1497 PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
mbed_official 107:414e9c822e99 1498 } else {
mbed_official 107:414e9c822e99 1499 PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
mbed_official 107:414e9c822e99 1500 }
mbed_official 107:414e9c822e99 1501 }
mbed_official 107:414e9c822e99 1502
mbed_official 107:414e9c822e99 1503 /**
mbed_official 107:414e9c822e99 1504 * \brief Return write protect status.
mbed_official 107:414e9c822e99 1505 *
mbed_official 107:414e9c822e99 1506 * \return Return write protect status.
mbed_official 107:414e9c822e99 1507 */
mbed_official 107:414e9c822e99 1508 uint32_t pmc_get_writeprotect_status(void)
mbed_official 107:414e9c822e99 1509 {
mbed_official 107:414e9c822e99 1510 return PMC->PMC_WPSR;
mbed_official 107:414e9c822e99 1511 }
mbed_official 107:414e9c822e99 1512
mbed_official 107:414e9c822e99 1513 #if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1514 /**
mbed_official 107:414e9c822e99 1515 * \brief Enable the specified peripheral clock.
mbed_official 107:414e9c822e99 1516 *
mbed_official 107:414e9c822e99 1517 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
mbed_official 107:414e9c822e99 1518 *
mbed_official 107:414e9c822e99 1519 * \param ul_id Peripheral ID (ID_xxx).
mbed_official 107:414e9c822e99 1520 *
mbed_official 107:414e9c822e99 1521 * \retval 0 Success.
mbed_official 107:414e9c822e99 1522 * \retval 1 Fail.
mbed_official 107:414e9c822e99 1523 */
mbed_official 107:414e9c822e99 1524 uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
mbed_official 107:414e9c822e99 1525 {
mbed_official 107:414e9c822e99 1526 uint32_t temp;
mbed_official 107:414e9c822e99 1527 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1528 if ((7 <= ul_id) && (ul_id<= 29)) {
mbed_official 107:414e9c822e99 1529 #else
mbed_official 107:414e9c822e99 1530 if ((8 <= ul_id) && (ul_id<= 29)) {
mbed_official 107:414e9c822e99 1531 #endif
mbed_official 107:414e9c822e99 1532 temp = pmc_get_active_status0();
mbed_official 107:414e9c822e99 1533 if (temp & (1 << ul_id)) {
mbed_official 107:414e9c822e99 1534 return 1;
mbed_official 107:414e9c822e99 1535 }
mbed_official 107:414e9c822e99 1536 PMC->PMC_SLPWK_ER0 = 1 << ul_id;
mbed_official 107:414e9c822e99 1537 temp = pmc_get_active_status0();
mbed_official 107:414e9c822e99 1538 if (temp & (1 << ul_id)) {
mbed_official 107:414e9c822e99 1539 pmc_disable_sleepwalking(ul_id);
mbed_official 107:414e9c822e99 1540 return 1;
mbed_official 107:414e9c822e99 1541 }
mbed_official 107:414e9c822e99 1542 return 0;
mbed_official 107:414e9c822e99 1543 }
mbed_official 107:414e9c822e99 1544 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1545 else if ((32 <= ul_id) && (ul_id<= 60)) {
mbed_official 107:414e9c822e99 1546 ul_id -= 32;
mbed_official 107:414e9c822e99 1547 temp = pmc_get_active_status1();
mbed_official 107:414e9c822e99 1548 if (temp & (1 << ul_id)) {
mbed_official 107:414e9c822e99 1549 return 1;
mbed_official 107:414e9c822e99 1550 }
mbed_official 107:414e9c822e99 1551 PMC->PMC_SLPWK_ER1 = 1 << ul_id;
mbed_official 107:414e9c822e99 1552 temp = pmc_get_active_status1();
mbed_official 107:414e9c822e99 1553 if (temp & (1 << ul_id)) {
mbed_official 107:414e9c822e99 1554 pmc_disable_sleepwalking(ul_id);
mbed_official 107:414e9c822e99 1555 return 1;
mbed_official 107:414e9c822e99 1556 }
mbed_official 107:414e9c822e99 1557 return 0;
mbed_official 107:414e9c822e99 1558 }
mbed_official 107:414e9c822e99 1559 #endif
mbed_official 107:414e9c822e99 1560 else {
mbed_official 107:414e9c822e99 1561 return 1;
mbed_official 107:414e9c822e99 1562 }
mbed_official 107:414e9c822e99 1563 }
mbed_official 107:414e9c822e99 1564
mbed_official 107:414e9c822e99 1565 /**
mbed_official 107:414e9c822e99 1566 * \brief Disable the sleepwalking of specified peripheral.
mbed_official 107:414e9c822e99 1567 *
mbed_official 107:414e9c822e99 1568 * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
mbed_official 107:414e9c822e99 1569 *
mbed_official 107:414e9c822e99 1570 * \param ul_id Peripheral ID (ID_xxx).
mbed_official 107:414e9c822e99 1571 *
mbed_official 107:414e9c822e99 1572 * \retval 0 Success.
mbed_official 107:414e9c822e99 1573 * \retval 1 Invalid parameter.
mbed_official 107:414e9c822e99 1574 */
mbed_official 107:414e9c822e99 1575 uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
mbed_official 107:414e9c822e99 1576 {
mbed_official 107:414e9c822e99 1577 #if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1578 if ((7 <= ul_id) && (ul_id<= 29)) {
mbed_official 107:414e9c822e99 1579 #else
mbed_official 107:414e9c822e99 1580 if ((8 <= ul_id) && (ul_id<= 29)) {
mbed_official 107:414e9c822e99 1581 #endif
mbed_official 107:414e9c822e99 1582 PMC->PMC_SLPWK_DR0 = 1 << ul_id;
mbed_official 107:414e9c822e99 1583 return 0;
mbed_official 107:414e9c822e99 1584 }
mbed_official 107:414e9c822e99 1585 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1586 else if ((32 <= ul_id) && (ul_id<= 60)) {
mbed_official 107:414e9c822e99 1587 ul_id -= 32;
mbed_official 107:414e9c822e99 1588 PMC->PMC_SLPWK_DR1 = 1 << ul_id;
mbed_official 107:414e9c822e99 1589 return 0;
mbed_official 107:414e9c822e99 1590 }
mbed_official 107:414e9c822e99 1591 #endif
mbed_official 107:414e9c822e99 1592 else {
mbed_official 107:414e9c822e99 1593 return 1;
mbed_official 107:414e9c822e99 1594 }
mbed_official 107:414e9c822e99 1595 }
mbed_official 107:414e9c822e99 1596
mbed_official 107:414e9c822e99 1597 /**
mbed_official 107:414e9c822e99 1598 * \brief Return peripheral sleepwalking enable status.
mbed_official 107:414e9c822e99 1599 *
mbed_official 107:414e9c822e99 1600 * \return the status register value.
mbed_official 107:414e9c822e99 1601 */
mbed_official 107:414e9c822e99 1602 uint32_t pmc_get_sleepwalking_status0(void)
mbed_official 107:414e9c822e99 1603 {
mbed_official 107:414e9c822e99 1604 return PMC->PMC_SLPWK_SR0;
mbed_official 107:414e9c822e99 1605 }
mbed_official 107:414e9c822e99 1606
mbed_official 107:414e9c822e99 1607 /**
mbed_official 107:414e9c822e99 1608 * \brief Return peripheral active status.
mbed_official 107:414e9c822e99 1609 *
mbed_official 107:414e9c822e99 1610 * \return the status register value.
mbed_official 107:414e9c822e99 1611 */
mbed_official 107:414e9c822e99 1612 uint32_t pmc_get_active_status0(void)
mbed_official 107:414e9c822e99 1613 {
mbed_official 107:414e9c822e99 1614 return PMC->PMC_SLPWK_ASR0;
mbed_official 107:414e9c822e99 1615 }
mbed_official 107:414e9c822e99 1616
mbed_official 107:414e9c822e99 1617 #endif
mbed_official 107:414e9c822e99 1618
mbed_official 107:414e9c822e99 1619 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
mbed_official 107:414e9c822e99 1620 /**
mbed_official 107:414e9c822e99 1621 * \brief Return peripheral sleepwalking enable status.
mbed_official 107:414e9c822e99 1622 *
mbed_official 107:414e9c822e99 1623 * \return the status register value.
mbed_official 107:414e9c822e99 1624 */
mbed_official 107:414e9c822e99 1625 uint32_t pmc_get_sleepwalking_status1(void)
mbed_official 107:414e9c822e99 1626 {
mbed_official 107:414e9c822e99 1627 return PMC->PMC_SLPWK_SR1;
mbed_official 107:414e9c822e99 1628 }
mbed_official 107:414e9c822e99 1629
mbed_official 107:414e9c822e99 1630 /**
mbed_official 107:414e9c822e99 1631 * \brief Return peripheral active status.
mbed_official 107:414e9c822e99 1632 *
mbed_official 107:414e9c822e99 1633 * \return the status register value.
mbed_official 107:414e9c822e99 1634 */
mbed_official 107:414e9c822e99 1635 uint32_t pmc_get_active_status1(void)
mbed_official 107:414e9c822e99 1636 {
mbed_official 107:414e9c822e99 1637 return PMC->PMC_SLPWK_ASR1;
mbed_official 107:414e9c822e99 1638 }
mbed_official 107:414e9c822e99 1639 #endif
mbed_official 107:414e9c822e99 1640
mbed_official 107:414e9c822e99 1641 /// @cond 0
mbed_official 107:414e9c822e99 1642 /**INDENT-OFF**/
mbed_official 107:414e9c822e99 1643 #ifdef __cplusplus
mbed_official 107:414e9c822e99 1644 }
mbed_official 107:414e9c822e99 1645 #endif
mbed_official 107:414e9c822e99 1646 /**INDENT-ON**/
mbed_official 107:414e9c822e99 1647 /// @endcond