Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_ll_sdmmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SDMMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_LL_SDMMC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_LL_SDMMC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SDMMC_LL
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief SDMMC Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
<> 144:ef7eb2e8f9f7 71 enabled or disabled.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
<> 144:ef7eb2e8f9f7 75 disabled when the bus is idle.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
<> 144:ef7eb2e8f9f7 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 }SDMMC_InitTypeDef;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief SDMMC Command Control structure
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 typedef struct
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
<> 144:ef7eb2e8f9f7 96 to a card as part of a command message. If a command
<> 144:ef7eb2e8f9f7 97 contains an argument, it must be loaded into this register
<> 144:ef7eb2e8f9f7 98 before writing the command to the command register. */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
<> 144:ef7eb2e8f9f7 101 Max_Data = 64 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 uint32_t Response; /*!< Specifies the SDMMC response type.
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref SDMMC_LL_Response_Type */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
<> 144:ef7eb2e8f9f7 107 enabled or disabled.
<> 144:ef7eb2e8f9f7 108 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
<> 144:ef7eb2e8f9f7 111 is enabled or disabled.
<> 144:ef7eb2e8f9f7 112 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
<> 144:ef7eb2e8f9f7 113 }SDMMC_CmdInitTypeDef;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief SDMMC Data Control structure
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<> 144:ef7eb2e8f9f7 126 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<> 144:ef7eb2e8f9f7 129 is a read or write.
<> 144:ef7eb2e8f9f7 130 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<> 144:ef7eb2e8f9f7 133 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
<> 144:ef7eb2e8f9f7 136 is enabled or disabled.
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
<> 144:ef7eb2e8f9f7 138 }SDMMC_DataInitTypeDef;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 153 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
<> 144:ef7eb2e8f9f7 156 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 165 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
<> 144:ef7eb2e8f9f7 168 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 177 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
<> 144:ef7eb2e8f9f7 180 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @}
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 189 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
<> 144:ef7eb2e8f9f7 190 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
<> 144:ef7eb2e8f9f7 193 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
<> 144:ef7eb2e8f9f7 194 ((WIDE) == SDMMC_BUS_WIDE_8B))
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 203 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
<> 144:ef7eb2e8f9f7 206 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @}
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup SDMMC_LL_Clock_Division Clock Division
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @}
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /** @defgroup SDMMC_LL_Command_Index Command Index
<> 144:ef7eb2e8f9f7 220 * @{
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup SDMMC_LL_Response_Type Response Type
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 231 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
<> 144:ef7eb2e8f9f7 232 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
<> 144:ef7eb2e8f9f7 235 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
<> 144:ef7eb2e8f9f7 236 ((RESPONSE) == SDMMC_RESPONSE_LONG))
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 245 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
<> 144:ef7eb2e8f9f7 246 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
<> 144:ef7eb2e8f9f7 249 ((WAIT) == SDMMC_WAIT_IT) || \
<> 144:ef7eb2e8f9f7 250 ((WAIT) == SDMMC_WAIT_PEND))
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup SDMMC_LL_CPSM_State CPSM State
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 259 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
<> 144:ef7eb2e8f9f7 262 ((CPSM) == SDMMC_CPSM_ENABLE))
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup SDMMC_LL_Response_Registers Response Register
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 271 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 272 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 273 #define SDMMC_RESP4 ((uint32_t)0x0000000C)
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
<> 144:ef7eb2e8f9f7 276 ((RESP) == SDMMC_RESP2) || \
<> 144:ef7eb2e8f9f7 277 ((RESP) == SDMMC_RESP3) || \
<> 144:ef7eb2e8f9f7 278 ((RESP) == SDMMC_RESP4))
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup SDMMC_LL_Data_Length Data Lenght
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 295 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
<> 144:ef7eb2e8f9f7 296 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
<> 144:ef7eb2e8f9f7 297 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
<> 144:ef7eb2e8f9f7 298 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
<> 144:ef7eb2e8f9f7 299 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 300 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 301 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
<> 144:ef7eb2e8f9f7 302 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
<> 144:ef7eb2e8f9f7 303 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 304 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 305 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 306 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 307 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 308 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
<> 144:ef7eb2e8f9f7 311 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
<> 144:ef7eb2e8f9f7 312 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
<> 144:ef7eb2e8f9f7 313 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
<> 144:ef7eb2e8f9f7 314 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
<> 144:ef7eb2e8f9f7 315 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
<> 144:ef7eb2e8f9f7 316 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
<> 144:ef7eb2e8f9f7 317 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
<> 144:ef7eb2e8f9f7 318 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
<> 144:ef7eb2e8f9f7 319 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
<> 144:ef7eb2e8f9f7 320 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
<> 144:ef7eb2e8f9f7 321 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
<> 144:ef7eb2e8f9f7 322 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
<> 144:ef7eb2e8f9f7 323 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
<> 144:ef7eb2e8f9f7 324 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 333 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
<> 144:ef7eb2e8f9f7 336 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 345 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
<> 144:ef7eb2e8f9f7 348 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /** @defgroup SDMMC_LL_DPSM_State DPSM State
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 357 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
<> 144:ef7eb2e8f9f7 360 ((DPSM) == SDMMC_DPSM_ENABLE))
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 369 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
<> 144:ef7eb2e8f9f7 372 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 381 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 382 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 383 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 384 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 385 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
<> 144:ef7eb2e8f9f7 386 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
<> 144:ef7eb2e8f9f7 387 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
<> 144:ef7eb2e8f9f7 388 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
<> 144:ef7eb2e8f9f7 389 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
<> 144:ef7eb2e8f9f7 390 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
<> 144:ef7eb2e8f9f7 391 #define SDMMC_IT_TXACT SDMMC_STA_TXACT
<> 144:ef7eb2e8f9f7 392 #define SDMMC_IT_RXACT SDMMC_STA_RXACT
<> 144:ef7eb2e8f9f7 393 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 394 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 395 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 396 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 397 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 398 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 399 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
<> 144:ef7eb2e8f9f7 400 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
<> 144:ef7eb2e8f9f7 401 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /** @defgroup SDMMC_LL_Flags Flags
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 410 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 411 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 412 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 413 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 414 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
<> 144:ef7eb2e8f9f7 415 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
<> 144:ef7eb2e8f9f7 416 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
<> 144:ef7eb2e8f9f7 417 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
<> 144:ef7eb2e8f9f7 418 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
<> 144:ef7eb2e8f9f7 419 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
<> 144:ef7eb2e8f9f7 420 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
<> 144:ef7eb2e8f9f7 421 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
<> 144:ef7eb2e8f9f7 422 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 423 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 424 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 425 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 426 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 427 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 428 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
<> 144:ef7eb2e8f9f7 429 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
<> 144:ef7eb2e8f9f7 430 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @}
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 440 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
<> 144:ef7eb2e8f9f7 441 * @{
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
<> 144:ef7eb2e8f9f7 445 * @brief SDMMC_LL registers bit address in the alias region
<> 144:ef7eb2e8f9f7 446 * @{
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 /* ---------------------- SDMMC registers bit mask --------------------------- */
<> 144:ef7eb2e8f9f7 449 /* --- CLKCR Register ---*/
<> 144:ef7eb2e8f9f7 450 /* CLKCR register clear mask */
<> 144:ef7eb2e8f9f7 451 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
<> 144:ef7eb2e8f9f7 452 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
<> 144:ef7eb2e8f9f7 453 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* --- DCTRL Register ---*/
<> 144:ef7eb2e8f9f7 456 /* SDMMC DCTRL Clear Mask */
<> 144:ef7eb2e8f9f7 457 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
<> 144:ef7eb2e8f9f7 458 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* --- CMD Register ---*/
<> 144:ef7eb2e8f9f7 461 /* CMD Register clear mask */
<> 144:ef7eb2e8f9f7 462 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
<> 144:ef7eb2e8f9f7 463 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
<> 144:ef7eb2e8f9f7 464 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /* SDMMC Initialization Frequency (400KHz max) */
<> 144:ef7eb2e8f9f7 467 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* SDMMC Data Transfer Frequency (25MHz max) */
<> 144:ef7eb2e8f9f7 470 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @}
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
<> 144:ef7eb2e8f9f7 477 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 478 * @{
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @brief Enable the SDMMC device.
<> 144:ef7eb2e8f9f7 483 * @param __INSTANCE__: SDMMC Instance
<> 144:ef7eb2e8f9f7 484 * @retval None
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Disable the SDMMC device.
<> 144:ef7eb2e8f9f7 490 * @param __INSTANCE__: SDMMC Instance
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief Enable the SDMMC DMA transfer.
<> 144:ef7eb2e8f9f7 497 * @param __INSTANCE__: SDMMC Instance
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @brief Disable the SDMMC DMA transfer.
<> 144:ef7eb2e8f9f7 503 * @param __INSTANCE__: SDMMC Instance
<> 144:ef7eb2e8f9f7 504 * @retval None
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Enable the SDMMC device interrupt.
<> 144:ef7eb2e8f9f7 510 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 511 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 512 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 513 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 514 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 515 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 516 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 517 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 518 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 519 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 520 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 521 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 522 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 523 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 524 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 525 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 526 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 527 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 528 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 529 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 530 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 531 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 532 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 533 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 534 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 535 * @retval None
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Disable the SDMMC device interrupt.
<> 144:ef7eb2e8f9f7 541 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 542 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 543 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 544 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 545 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 546 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 547 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 548 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 549 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 550 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 551 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 552 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 553 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 554 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 555 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 556 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 557 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 558 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 559 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 560 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 561 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 562 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 563 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 564 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 565 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 566 * @retval None
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /**
<> 144:ef7eb2e8f9f7 571 * @brief Checks whether the specified SDMMC flag is set or not.
<> 144:ef7eb2e8f9f7 572 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 573 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 574 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 575 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 576 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 577 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 578 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 579 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 580 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 581 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 582 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 583 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 584 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 585 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
<> 144:ef7eb2e8f9f7 586 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
<> 144:ef7eb2e8f9f7 587 * @arg SDMMC_FLAG_RXACT: Data receive in progress
<> 144:ef7eb2e8f9f7 588 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 144:ef7eb2e8f9f7 589 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 144:ef7eb2e8f9f7 590 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
<> 144:ef7eb2e8f9f7 591 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
<> 144:ef7eb2e8f9f7 592 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
<> 144:ef7eb2e8f9f7 593 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
<> 144:ef7eb2e8f9f7 594 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
<> 144:ef7eb2e8f9f7 595 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
<> 144:ef7eb2e8f9f7 596 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 597 * @retval The new state of SDMMC_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Clears the SDMMC pending flags.
<> 144:ef7eb2e8f9f7 604 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 605 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 606 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 607 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 608 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 609 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 610 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 611 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 612 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 613 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 614 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 615 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 616 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 617 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 618 * @retval None
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 624 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 625 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
<> 144:ef7eb2e8f9f7 626 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 627 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 628 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 629 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 630 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 631 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 632 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 633 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 634 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 635 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 636 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 637 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 638 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 639 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 640 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 641 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 642 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 643 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 644 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 645 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 646 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 647 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 648 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 649 * @retval The new state of SDMMC_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /**
<> 144:ef7eb2e8f9f7 654 * @brief Clears the SDMMC's interrupt pending bits.
<> 144:ef7eb2e8f9f7 655 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 656 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 657 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 658 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 659 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 660 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 661 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 662 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 663 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 664 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 665 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 666 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 667 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 668 * @retval None
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 674 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 675 * @retval None
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Disable Start the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 681 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 682 * @retval None
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 688 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 689 * @retval None
<> 144:ef7eb2e8f9f7 690 */
<> 144:ef7eb2e8f9f7 691 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /**
<> 144:ef7eb2e8f9f7 694 * @brief Disable Stop the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 695 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 696 * @retval None
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @brief Enable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 702 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 703 * @retval None
<> 144:ef7eb2e8f9f7 704 */
<> 144:ef7eb2e8f9f7 705 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 /**
<> 144:ef7eb2e8f9f7 708 * @brief Disable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 709 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 710 * @retval None
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Enable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 716 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 717 * @retval None
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /**
<> 144:ef7eb2e8f9f7 722 * @brief Disable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 723 * @param __INSTANCE__ : Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 724 * @retval None
<> 144:ef7eb2e8f9f7 725 */
<> 144:ef7eb2e8f9f7 726 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @}
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /**
<> 144:ef7eb2e8f9f7 733 * @}
<> 144:ef7eb2e8f9f7 734 */
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 737 /** @addtogroup SDMMC_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 738 * @{
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 742 /** @addtogroup HAL_SDMMC_LL_Group1
<> 144:ef7eb2e8f9f7 743 * @{
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
<> 144:ef7eb2e8f9f7 746 /**
<> 144:ef7eb2e8f9f7 747 * @}
<> 144:ef7eb2e8f9f7 748 */
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 751 /** @addtogroup HAL_SDMMC_LL_Group2
<> 144:ef7eb2e8f9f7 752 * @{
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 755 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 756 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
<> 144:ef7eb2e8f9f7 757 /**
<> 144:ef7eb2e8f9f7 758 * @}
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 762 /** @addtogroup HAL_SDMMC_LL_Group3
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 766 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 767 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Command path state machine (CPSM) management functions */
<> 144:ef7eb2e8f9f7 770 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
<> 144:ef7eb2e8f9f7 771 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 772 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Data path state machine (DPSM) management functions */
<> 144:ef7eb2e8f9f7 775 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
<> 144:ef7eb2e8f9f7 776 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 777 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 /* SDMMC Cards mode management functions */
<> 144:ef7eb2e8f9f7 780 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /**
<> 144:ef7eb2e8f9f7 783 * @}
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /**
<> 144:ef7eb2e8f9f7 787 * @}
<> 144:ef7eb2e8f9f7 788 */
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /**
<> 144:ef7eb2e8f9f7 791 * @}
<> 144:ef7eb2e8f9f7 792 */
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /**
<> 144:ef7eb2e8f9f7 795 * @}
<> 144:ef7eb2e8f9f7 796 */
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 #endif
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 #endif /* __STM32F7xx_LL_SDMMC_H */
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/