added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f7xx_hal_spdifrx.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.1.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 22-April-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief Header file of SPDIFRX HAL module. |
<> | 144:ef7eb2e8f9f7 | 8 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 9 | * @attention |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 14 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 16 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 18 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 19 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 21 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 22 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 23 | * |
<> | 144:ef7eb2e8f9f7 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 34 | * |
<> | 144:ef7eb2e8f9f7 | 35 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 36 | */ |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 39 | #ifndef __STM32F7xx_HAL_SPDIFRX_H |
<> | 144:ef7eb2e8f9f7 | 40 | #define __STM32F7xx_HAL_SPDIFRX_H |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 43 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 44 | #endif |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 47 | #include "stm32f7xx_hal_def.h" |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 50 | * @{ |
<> | 144:ef7eb2e8f9f7 | 51 | */ |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | /** @addtogroup SPDIFRX |
<> | 144:ef7eb2e8f9f7 | 54 | * @{ |
<> | 144:ef7eb2e8f9f7 | 55 | */ |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | /* Exported types ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 58 | /** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types |
<> | 144:ef7eb2e8f9f7 | 59 | * @{ |
<> | 144:ef7eb2e8f9f7 | 60 | */ |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | /** |
<> | 144:ef7eb2e8f9f7 | 63 | * @brief SPDIFRX Init structure definition |
<> | 144:ef7eb2e8f9f7 | 64 | */ |
<> | 144:ef7eb2e8f9f7 | 65 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 66 | { |
<> | 144:ef7eb2e8f9f7 | 67 | uint32_t InputSelection; /*!< Specifies the SPDIF input selection. |
<> | 144:ef7eb2e8f9f7 | 68 | This parameter can be a value of @ref SPDIFRX_Input_Selection */ |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase. |
<> | 144:ef7eb2e8f9f7 | 71 | This parameter can be a value of @ref SPDIFRX_Max_Retries */ |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. |
<> | 144:ef7eb2e8f9f7 | 74 | This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B. |
<> | 144:ef7eb2e8f9f7 | 77 | This parameter can be a value of @ref SPDIFRX_Channel_Selection */ |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). |
<> | 144:ef7eb2e8f9f7 | 80 | This parameter can be a value of @ref SPDIFRX_Data_Format */ |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. |
<> | 144:ef7eb2e8f9f7 | 83 | This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 86 | This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 89 | This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 92 | This parameter can be a value of @ref SPDIFRX_V_Mask */ |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 95 | This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | }SPDIFRX_InitTypeDef; |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /** |
<> | 144:ef7eb2e8f9f7 | 100 | * @brief SPDIFRX SetDataFormat structure definition |
<> | 144:ef7eb2e8f9f7 | 101 | */ |
<> | 144:ef7eb2e8f9f7 | 102 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 103 | { |
<> | 144:ef7eb2e8f9f7 | 104 | uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). |
<> | 144:ef7eb2e8f9f7 | 105 | This parameter can be a value of @ref SPDIFRX_Data_Format */ |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. |
<> | 144:ef7eb2e8f9f7 | 108 | This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 111 | This parameter can be a value of @ref SPDIFRX_PT_Mask */ |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 114 | This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 117 | This parameter can be a value of @ref SPDIFRX_V_Mask */ |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame. |
<> | 144:ef7eb2e8f9f7 | 120 | This parameter can be a value of @ref SPDIFRX_PE_Mask */ |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | }SPDIFRX_SetDataFormatTypeDef; |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /** |
<> | 144:ef7eb2e8f9f7 | 125 | * @brief HAL State structures definition |
<> | 144:ef7eb2e8f9f7 | 126 | */ |
<> | 144:ef7eb2e8f9f7 | 127 | typedef enum |
<> | 144:ef7eb2e8f9f7 | 128 | { |
<> | 144:ef7eb2e8f9f7 | 129 | HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */ |
<> | 144:ef7eb2e8f9f7 | 130 | HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */ |
<> | 144:ef7eb2e8f9f7 | 131 | HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 132 | HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 133 | HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 134 | HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */ |
<> | 144:ef7eb2e8f9f7 | 135 | }HAL_SPDIFRX_StateTypeDef; |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | /** |
<> | 144:ef7eb2e8f9f7 | 138 | * @brief SPDIFRX handle Structure definition |
<> | 144:ef7eb2e8f9f7 | 139 | */ |
<> | 144:ef7eb2e8f9f7 | 140 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 141 | { |
<> | 144:ef7eb2e8f9f7 | 142 | SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */ |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */ |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */ |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter |
<> | 144:ef7eb2e8f9f7 | 153 | (This field is initialized at the |
<> | 144:ef7eb2e8f9f7 | 154 | same value as transfer size at the |
<> | 144:ef7eb2e8f9f7 | 155 | beginning of the transfer and |
<> | 144:ef7eb2e8f9f7 | 156 | decremented when a sample is received. |
<> | 144:ef7eb2e8f9f7 | 157 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */ |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter |
<> | 144:ef7eb2e8f9f7 | 162 | (This field is initialized at the |
<> | 144:ef7eb2e8f9f7 | 163 | same value as transfer size at the |
<> | 144:ef7eb2e8f9f7 | 164 | beginning of the transfer and |
<> | 144:ef7eb2e8f9f7 | 165 | decremented when a sample is received. |
<> | 144:ef7eb2e8f9f7 | 166 | NbSamplesReceived = RxBufferSize-RxBufferCount) */ |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */ |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */ |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | __IO uint32_t ErrorCode; /* SPDIFRX Error code */ |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | }SPDIFRX_HandleTypeDef; |
<> | 144:ef7eb2e8f9f7 | 179 | /** |
<> | 144:ef7eb2e8f9f7 | 180 | * @} |
<> | 144:ef7eb2e8f9f7 | 181 | */ |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | /* Exported constants --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 184 | /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants |
<> | 144:ef7eb2e8f9f7 | 185 | * @{ |
<> | 144:ef7eb2e8f9f7 | 186 | */ |
<> | 144:ef7eb2e8f9f7 | 187 | /** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code |
<> | 144:ef7eb2e8f9f7 | 188 | * @{ |
<> | 144:ef7eb2e8f9f7 | 189 | */ |
<> | 144:ef7eb2e8f9f7 | 190 | #define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
<> | 144:ef7eb2e8f9f7 | 191 | #define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ |
<> | 144:ef7eb2e8f9f7 | 192 | #define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ |
<> | 144:ef7eb2e8f9f7 | 193 | #define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */ |
<> | 144:ef7eb2e8f9f7 | 194 | #define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ |
<> | 144:ef7eb2e8f9f7 | 195 | #define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */ |
<> | 144:ef7eb2e8f9f7 | 196 | /** |
<> | 144:ef7eb2e8f9f7 | 197 | * @} |
<> | 144:ef7eb2e8f9f7 | 198 | */ |
<> | 144:ef7eb2e8f9f7 | 199 | |
<> | 144:ef7eb2e8f9f7 | 200 | /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection |
<> | 144:ef7eb2e8f9f7 | 201 | * @{ |
<> | 144:ef7eb2e8f9f7 | 202 | */ |
<> | 144:ef7eb2e8f9f7 | 203 | #define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 204 | #define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) |
<> | 144:ef7eb2e8f9f7 | 205 | #define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) |
<> | 144:ef7eb2e8f9f7 | 206 | #define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) |
<> | 144:ef7eb2e8f9f7 | 207 | /** |
<> | 144:ef7eb2e8f9f7 | 208 | * @} |
<> | 144:ef7eb2e8f9f7 | 209 | */ |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | /** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries |
<> | 144:ef7eb2e8f9f7 | 212 | * @{ |
<> | 144:ef7eb2e8f9f7 | 213 | */ |
<> | 144:ef7eb2e8f9f7 | 214 | #define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 215 | #define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) |
<> | 144:ef7eb2e8f9f7 | 216 | #define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) |
<> | 144:ef7eb2e8f9f7 | 217 | #define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) |
<> | 144:ef7eb2e8f9f7 | 218 | /** |
<> | 144:ef7eb2e8f9f7 | 219 | * @} |
<> | 144:ef7eb2e8f9f7 | 220 | */ |
<> | 144:ef7eb2e8f9f7 | 221 | |
<> | 144:ef7eb2e8f9f7 | 222 | /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity |
<> | 144:ef7eb2e8f9f7 | 223 | * @{ |
<> | 144:ef7eb2e8f9f7 | 224 | */ |
<> | 144:ef7eb2e8f9f7 | 225 | #define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 226 | #define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) |
<> | 144:ef7eb2e8f9f7 | 227 | /** |
<> | 144:ef7eb2e8f9f7 | 228 | * @} |
<> | 144:ef7eb2e8f9f7 | 229 | */ |
<> | 144:ef7eb2e8f9f7 | 230 | |
<> | 144:ef7eb2e8f9f7 | 231 | /** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask |
<> | 144:ef7eb2e8f9f7 | 232 | * @{ |
<> | 144:ef7eb2e8f9f7 | 233 | */ |
<> | 144:ef7eb2e8f9f7 | 234 | #define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 235 | #define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) |
<> | 144:ef7eb2e8f9f7 | 236 | /** |
<> | 144:ef7eb2e8f9f7 | 237 | * @} |
<> | 144:ef7eb2e8f9f7 | 238 | */ |
<> | 144:ef7eb2e8f9f7 | 239 | |
<> | 144:ef7eb2e8f9f7 | 240 | /** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask |
<> | 144:ef7eb2e8f9f7 | 241 | * @{ |
<> | 144:ef7eb2e8f9f7 | 242 | */ |
<> | 144:ef7eb2e8f9f7 | 243 | #define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */ |
<> | 144:ef7eb2e8f9f7 | 244 | #define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/ |
<> | 144:ef7eb2e8f9f7 | 245 | /** |
<> | 144:ef7eb2e8f9f7 | 246 | * @} |
<> | 144:ef7eb2e8f9f7 | 247 | */ |
<> | 144:ef7eb2e8f9f7 | 248 | |
<> | 144:ef7eb2e8f9f7 | 249 | /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask |
<> | 144:ef7eb2e8f9f7 | 250 | * @{ |
<> | 144:ef7eb2e8f9f7 | 251 | */ |
<> | 144:ef7eb2e8f9f7 | 252 | #define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 253 | #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) |
<> | 144:ef7eb2e8f9f7 | 254 | /** |
<> | 144:ef7eb2e8f9f7 | 255 | * @} |
<> | 144:ef7eb2e8f9f7 | 256 | */ |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask |
<> | 144:ef7eb2e8f9f7 | 259 | * @{ |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | #define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 262 | #define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) |
<> | 144:ef7eb2e8f9f7 | 263 | /** |
<> | 144:ef7eb2e8f9f7 | 264 | * @} |
<> | 144:ef7eb2e8f9f7 | 265 | */ |
<> | 144:ef7eb2e8f9f7 | 266 | |
<> | 144:ef7eb2e8f9f7 | 267 | /** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection |
<> | 144:ef7eb2e8f9f7 | 268 | * @{ |
<> | 144:ef7eb2e8f9f7 | 269 | */ |
<> | 144:ef7eb2e8f9f7 | 270 | #define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 271 | #define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) |
<> | 144:ef7eb2e8f9f7 | 272 | /** |
<> | 144:ef7eb2e8f9f7 | 273 | * @} |
<> | 144:ef7eb2e8f9f7 | 274 | */ |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | /** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format |
<> | 144:ef7eb2e8f9f7 | 277 | * @{ |
<> | 144:ef7eb2e8f9f7 | 278 | */ |
<> | 144:ef7eb2e8f9f7 | 279 | #define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 280 | #define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) |
<> | 144:ef7eb2e8f9f7 | 281 | #define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) |
<> | 144:ef7eb2e8f9f7 | 282 | /** |
<> | 144:ef7eb2e8f9f7 | 283 | * @} |
<> | 144:ef7eb2e8f9f7 | 284 | */ |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode |
<> | 144:ef7eb2e8f9f7 | 287 | * @{ |
<> | 144:ef7eb2e8f9f7 | 288 | */ |
<> | 144:ef7eb2e8f9f7 | 289 | #define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) |
<> | 144:ef7eb2e8f9f7 | 290 | #define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) |
<> | 144:ef7eb2e8f9f7 | 291 | /** |
<> | 144:ef7eb2e8f9f7 | 292 | * @} |
<> | 144:ef7eb2e8f9f7 | 293 | */ |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /** @defgroup SPDIFRX_State SPDIFRX State |
<> | 144:ef7eb2e8f9f7 | 296 | * @{ |
<> | 144:ef7eb2e8f9f7 | 297 | */ |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | #define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) |
<> | 144:ef7eb2e8f9f7 | 300 | #define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) |
<> | 144:ef7eb2e8f9f7 | 301 | #define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) |
<> | 144:ef7eb2e8f9f7 | 302 | /** |
<> | 144:ef7eb2e8f9f7 | 303 | * @} |
<> | 144:ef7eb2e8f9f7 | 304 | */ |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition |
<> | 144:ef7eb2e8f9f7 | 307 | * @{ |
<> | 144:ef7eb2e8f9f7 | 308 | */ |
<> | 144:ef7eb2e8f9f7 | 309 | #define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) |
<> | 144:ef7eb2e8f9f7 | 310 | #define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) |
<> | 144:ef7eb2e8f9f7 | 311 | #define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) |
<> | 144:ef7eb2e8f9f7 | 312 | #define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) |
<> | 144:ef7eb2e8f9f7 | 313 | #define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) |
<> | 144:ef7eb2e8f9f7 | 314 | #define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) |
<> | 144:ef7eb2e8f9f7 | 315 | #define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) |
<> | 144:ef7eb2e8f9f7 | 316 | /** |
<> | 144:ef7eb2e8f9f7 | 317 | * @} |
<> | 144:ef7eb2e8f9f7 | 318 | */ |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition |
<> | 144:ef7eb2e8f9f7 | 321 | * @{ |
<> | 144:ef7eb2e8f9f7 | 322 | */ |
<> | 144:ef7eb2e8f9f7 | 323 | #define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) |
<> | 144:ef7eb2e8f9f7 | 324 | #define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) |
<> | 144:ef7eb2e8f9f7 | 325 | #define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) |
<> | 144:ef7eb2e8f9f7 | 326 | #define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) |
<> | 144:ef7eb2e8f9f7 | 327 | #define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) |
<> | 144:ef7eb2e8f9f7 | 328 | #define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) |
<> | 144:ef7eb2e8f9f7 | 329 | #define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) |
<> | 144:ef7eb2e8f9f7 | 330 | #define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) |
<> | 144:ef7eb2e8f9f7 | 331 | #define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) |
<> | 144:ef7eb2e8f9f7 | 332 | /** |
<> | 144:ef7eb2e8f9f7 | 333 | * @} |
<> | 144:ef7eb2e8f9f7 | 334 | */ |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | /** |
<> | 144:ef7eb2e8f9f7 | 337 | * @} |
<> | 144:ef7eb2e8f9f7 | 338 | */ |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /* Exported macros -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 341 | /** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros |
<> | 144:ef7eb2e8f9f7 | 342 | * @{ |
<> | 144:ef7eb2e8f9f7 | 343 | */ |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | /** @brief Reset SPDIFRX handle state |
<> | 144:ef7eb2e8f9f7 | 346 | * @param __HANDLE__: SPDIFRX handle. |
<> | 144:ef7eb2e8f9f7 | 347 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 348 | */ |
<> | 144:ef7eb2e8f9f7 | 349 | #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | /** @brief Disable the specified SPDIFRX peripheral (IDLE State). |
<> | 144:ef7eb2e8f9f7 | 352 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 353 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 354 | */ |
<> | 144:ef7eb2e8f9f7 | 355 | #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) |
<> | 144:ef7eb2e8f9f7 | 356 | |
<> | 144:ef7eb2e8f9f7 | 357 | /** @brief Enable the specified SPDIFRX peripheral (SYNC State). |
<> | 144:ef7eb2e8f9f7 | 358 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 359 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 360 | */ |
<> | 144:ef7eb2e8f9f7 | 361 | #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | |
<> | 144:ef7eb2e8f9f7 | 364 | /** @brief Enable the specified SPDIFRX peripheral (RCV State). |
<> | 144:ef7eb2e8f9f7 | 365 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 366 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 367 | */ |
<> | 144:ef7eb2e8f9f7 | 368 | #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | /** @brief Enable or disable the specified SPDIFRX interrupts. |
<> | 144:ef7eb2e8f9f7 | 372 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 373 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
<> | 144:ef7eb2e8f9f7 | 374 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 375 | * @arg SPDIFRX_IT_RXNE |
<> | 144:ef7eb2e8f9f7 | 376 | * @arg SPDIFRX_IT_CSRNE |
<> | 144:ef7eb2e8f9f7 | 377 | * @arg SPDIFRX_IT_PERRIE |
<> | 144:ef7eb2e8f9f7 | 378 | * @arg SPDIFRX_IT_OVRIE |
<> | 144:ef7eb2e8f9f7 | 379 | * @arg SPDIFRX_IT_SBLKIE |
<> | 144:ef7eb2e8f9f7 | 380 | * @arg SPDIFRX_IT_SYNCDIE |
<> | 144:ef7eb2e8f9f7 | 381 | * @arg SPDIFRX_IT_IFEIE |
<> | 144:ef7eb2e8f9f7 | 382 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 383 | */ |
<> | 144:ef7eb2e8f9f7 | 384 | #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) |
<> | 144:ef7eb2e8f9f7 | 385 | #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) |
<> | 144:ef7eb2e8f9f7 | 386 | |
<> | 144:ef7eb2e8f9f7 | 387 | /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. |
<> | 144:ef7eb2e8f9f7 | 388 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 389 | * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. |
<> | 144:ef7eb2e8f9f7 | 390 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 391 | * @arg SPDIFRX_IT_RXNE |
<> | 144:ef7eb2e8f9f7 | 392 | * @arg SPDIFRX_IT_CSRNE |
<> | 144:ef7eb2e8f9f7 | 393 | * @arg SPDIFRX_IT_PERRIE |
<> | 144:ef7eb2e8f9f7 | 394 | * @arg SPDIFRX_IT_OVRIE |
<> | 144:ef7eb2e8f9f7 | 395 | * @arg SPDIFRX_IT_SBLKIE |
<> | 144:ef7eb2e8f9f7 | 396 | * @arg SPDIFRX_IT_SYNCDIE |
<> | 144:ef7eb2e8f9f7 | 397 | * @arg SPDIFRX_IT_IFEIE |
<> | 144:ef7eb2e8f9f7 | 398 | * @retval The new state of __IT__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 399 | */ |
<> | 144:ef7eb2e8f9f7 | 400 | #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /** @brief Checks whether the specified SPDIFRX flag is set or not. |
<> | 144:ef7eb2e8f9f7 | 403 | * @param __HANDLE__: specifies the SPDIFRX Handle. |
<> | 144:ef7eb2e8f9f7 | 404 | * @param __FLAG__: specifies the flag to check. |
<> | 144:ef7eb2e8f9f7 | 405 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 406 | * @arg SPDIFRX_FLAG_RXNE |
<> | 144:ef7eb2e8f9f7 | 407 | * @arg SPDIFRX_FLAG_CSRNE |
<> | 144:ef7eb2e8f9f7 | 408 | * @arg SPDIFRX_FLAG_PERR |
<> | 144:ef7eb2e8f9f7 | 409 | * @arg SPDIFRX_FLAG_OVR |
<> | 144:ef7eb2e8f9f7 | 410 | * @arg SPDIFRX_FLAG_SBD |
<> | 144:ef7eb2e8f9f7 | 411 | * @arg SPDIFRX_FLAG_SYNCD |
<> | 144:ef7eb2e8f9f7 | 412 | * @arg SPDIFRX_FLAG_FERR |
<> | 144:ef7eb2e8f9f7 | 413 | * @arg SPDIFRX_FLAG_SERR |
<> | 144:ef7eb2e8f9f7 | 414 | * @arg SPDIFRX_FLAG_TERR |
<> | 144:ef7eb2e8f9f7 | 415 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
<> | 144:ef7eb2e8f9f7 | 416 | */ |
<> | 144:ef7eb2e8f9f7 | 417 | #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. |
<> | 144:ef7eb2e8f9f7 | 420 | * @param __HANDLE__: specifies the USART Handle. |
<> | 144:ef7eb2e8f9f7 | 421 | * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set |
<> | 144:ef7eb2e8f9f7 | 422 | * to clear the corresponding interrupt |
<> | 144:ef7eb2e8f9f7 | 423 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 424 | * @arg SPDIFRX_FLAG_PERR |
<> | 144:ef7eb2e8f9f7 | 425 | * @arg SPDIFRX_FLAG_OVR |
<> | 144:ef7eb2e8f9f7 | 426 | * @arg SPDIFRX_SR_SBD |
<> | 144:ef7eb2e8f9f7 | 427 | * @arg SPDIFRX_SR_SYNCD |
<> | 144:ef7eb2e8f9f7 | 428 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 429 | */ |
<> | 144:ef7eb2e8f9f7 | 430 | #define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) |
<> | 144:ef7eb2e8f9f7 | 431 | |
<> | 144:ef7eb2e8f9f7 | 432 | /** |
<> | 144:ef7eb2e8f9f7 | 433 | * @} |
<> | 144:ef7eb2e8f9f7 | 434 | */ |
<> | 144:ef7eb2e8f9f7 | 435 | |
<> | 144:ef7eb2e8f9f7 | 436 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 437 | /** @addtogroup SPDIFRX_Exported_Functions |
<> | 144:ef7eb2e8f9f7 | 438 | * @{ |
<> | 144:ef7eb2e8f9f7 | 439 | */ |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 144:ef7eb2e8f9f7 | 441 | /** @addtogroup SPDIFRX_Exported_Functions_Group1 |
<> | 144:ef7eb2e8f9f7 | 442 | * @{ |
<> | 144:ef7eb2e8f9f7 | 443 | */ |
<> | 144:ef7eb2e8f9f7 | 444 | /* Initialization/de-initialization functions **********************************/ |
<> | 144:ef7eb2e8f9f7 | 445 | HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 446 | HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 447 | void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 448 | void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 449 | HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); |
<> | 144:ef7eb2e8f9f7 | 450 | /** |
<> | 144:ef7eb2e8f9f7 | 451 | * @} |
<> | 144:ef7eb2e8f9f7 | 452 | */ |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | /** @addtogroup SPDIFRX_Exported_Functions_Group2 |
<> | 144:ef7eb2e8f9f7 | 455 | * @{ |
<> | 144:ef7eb2e8f9f7 | 456 | */ |
<> | 144:ef7eb2e8f9f7 | 457 | /* I/O operation functions ***************************************************/ |
<> | 144:ef7eb2e8f9f7 | 458 | /* Blocking mode: Polling */ |
<> | 144:ef7eb2e8f9f7 | 459 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 460 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); |
<> | 144:ef7eb2e8f9f7 | 461 | |
<> | 144:ef7eb2e8f9f7 | 462 | /* Non-Blocking mode: Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 463 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 464 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 465 | void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | /* Non-Blocking mode: DMA */ |
<> | 144:ef7eb2e8f9f7 | 468 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 469 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); |
<> | 144:ef7eb2e8f9f7 | 470 | |
<> | 144:ef7eb2e8f9f7 | 471 | HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 472 | |
<> | 144:ef7eb2e8f9f7 | 473 | /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ |
<> | 144:ef7eb2e8f9f7 | 474 | void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 475 | void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 476 | void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 477 | void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 478 | void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 479 | /** |
<> | 144:ef7eb2e8f9f7 | 480 | * @} |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /** @addtogroup SPDIFRX_Exported_Functions_Group3 |
<> | 144:ef7eb2e8f9f7 | 484 | * @{ |
<> | 144:ef7eb2e8f9f7 | 485 | */ |
<> | 144:ef7eb2e8f9f7 | 486 | /* Peripheral Control and State functions ************************************/ |
<> | 144:ef7eb2e8f9f7 | 487 | HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 488 | uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 489 | /** |
<> | 144:ef7eb2e8f9f7 | 490 | * @} |
<> | 144:ef7eb2e8f9f7 | 491 | */ |
<> | 144:ef7eb2e8f9f7 | 492 | |
<> | 144:ef7eb2e8f9f7 | 493 | /** |
<> | 144:ef7eb2e8f9f7 | 494 | * @} |
<> | 144:ef7eb2e8f9f7 | 495 | */ |
<> | 144:ef7eb2e8f9f7 | 496 | /* Private types -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 497 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 498 | /* Private constants ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 499 | /* Private macros ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 500 | /** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros |
<> | 144:ef7eb2e8f9f7 | 501 | * @{ |
<> | 144:ef7eb2e8f9f7 | 502 | */ |
<> | 144:ef7eb2e8f9f7 | 503 | #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ |
<> | 144:ef7eb2e8f9f7 | 504 | ((INPUT) == SPDIFRX_INPUT_IN2) || \ |
<> | 144:ef7eb2e8f9f7 | 505 | ((INPUT) == SPDIFRX_INPUT_IN3) || \ |
<> | 144:ef7eb2e8f9f7 | 506 | ((INPUT) == SPDIFRX_INPUT_IN0)) |
<> | 144:ef7eb2e8f9f7 | 507 | #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ |
<> | 144:ef7eb2e8f9f7 | 508 | ((RET) == SPDIFRX_MAXRETRIES_3) || \ |
<> | 144:ef7eb2e8f9f7 | 509 | ((RET) == SPDIFRX_MAXRETRIES_15) || \ |
<> | 144:ef7eb2e8f9f7 | 510 | ((RET) == SPDIFRX_MAXRETRIES_63)) |
<> | 144:ef7eb2e8f9f7 | 511 | #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ |
<> | 144:ef7eb2e8f9f7 | 512 | ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) |
<> | 144:ef7eb2e8f9f7 | 513 | #define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ |
<> | 144:ef7eb2e8f9f7 | 514 | ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) |
<> | 144:ef7eb2e8f9f7 | 515 | #define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ |
<> | 144:ef7eb2e8f9f7 | 516 | ((VAL) == SPDIFRX_VALIDITYMASK_ON)) |
<> | 144:ef7eb2e8f9f7 | 517 | #define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ |
<> | 144:ef7eb2e8f9f7 | 518 | ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) |
<> | 144:ef7eb2e8f9f7 | 519 | #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ |
<> | 144:ef7eb2e8f9f7 | 520 | ((CHANNEL) == SPDIFRX_CHANNEL_B)) |
<> | 144:ef7eb2e8f9f7 | 521 | #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ |
<> | 144:ef7eb2e8f9f7 | 522 | ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ |
<> | 144:ef7eb2e8f9f7 | 523 | ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) |
<> | 144:ef7eb2e8f9f7 | 524 | #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ |
<> | 144:ef7eb2e8f9f7 | 525 | ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) |
<> | 144:ef7eb2e8f9f7 | 526 | |
<> | 144:ef7eb2e8f9f7 | 527 | #define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ |
<> | 144:ef7eb2e8f9f7 | 528 | ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) |
<> | 144:ef7eb2e8f9f7 | 529 | /** |
<> | 144:ef7eb2e8f9f7 | 530 | * @} |
<> | 144:ef7eb2e8f9f7 | 531 | */ |
<> | 144:ef7eb2e8f9f7 | 532 | |
<> | 144:ef7eb2e8f9f7 | 533 | /* Private functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 534 | /** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions |
<> | 144:ef7eb2e8f9f7 | 535 | * @{ |
<> | 144:ef7eb2e8f9f7 | 536 | */ |
<> | 144:ef7eb2e8f9f7 | 537 | /** |
<> | 144:ef7eb2e8f9f7 | 538 | * @} |
<> | 144:ef7eb2e8f9f7 | 539 | */ |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /** |
<> | 144:ef7eb2e8f9f7 | 542 | * @} |
<> | 144:ef7eb2e8f9f7 | 543 | */ |
<> | 144:ef7eb2e8f9f7 | 544 | |
<> | 144:ef7eb2e8f9f7 | 545 | /** |
<> | 144:ef7eb2e8f9f7 | 546 | * @} |
<> | 144:ef7eb2e8f9f7 | 547 | */ |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 550 | } |
<> | 144:ef7eb2e8f9f7 | 551 | #endif |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | |
<> | 144:ef7eb2e8f9f7 | 554 | #endif /* __STM32F7xx_HAL_SPDIFRX_H */ |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |