added prescaler for 16 bit pwm in LPC1347 target
Fork of mbed-dev by
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spdifrx.c@147:ba84b7dc41a7, 2016-09-10 (annotated)
- Committer:
- JojoS
- Date:
- Sat Sep 10 15:32:04 2016 +0000
- Revision:
- 147:ba84b7dc41a7
- Parent:
- 144:ef7eb2e8f9f7
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f7xx_hal_spdifrx.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.1.0 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 22-April-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 8 | * functionalities of the SPDIFRX audio interface: |
<> | 144:ef7eb2e8f9f7 | 9 | * + Initialization and Configuration |
<> | 144:ef7eb2e8f9f7 | 10 | * + Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + DMA transfers management |
<> | 144:ef7eb2e8f9f7 | 12 | * + Interrupts and flags management |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 16 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | [..] |
<> | 144:ef7eb2e8f9f7 | 18 | The SPDIFRX HAL driver can be used as follow: |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | (#) Declare SPDIFRX_HandleTypeDef handle structure. |
<> | 144:ef7eb2e8f9f7 | 21 | (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API: |
<> | 144:ef7eb2e8f9f7 | 22 | (##) Enable the SPDIFRX interface clock. |
<> | 144:ef7eb2e8f9f7 | 23 | (##) SPDIFRX pins configuration: |
<> | 144:ef7eb2e8f9f7 | 24 | (+++) Enable the clock for the SPDIFRX GPIOs. |
<> | 144:ef7eb2e8f9f7 | 25 | (+++) Configure these SPDIFRX pins as alternate function pull-up. |
<> | 144:ef7eb2e8f9f7 | 26 | (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's). |
<> | 144:ef7eb2e8f9f7 | 27 | (+++) Configure the SPDIFRX interrupt priority. |
<> | 144:ef7eb2e8f9f7 | 28 | (+++) Enable the NVIC SPDIFRX IRQ handle. |
<> | 144:ef7eb2e8f9f7 | 29 | (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). |
<> | 144:ef7eb2e8f9f7 | 30 | (+++) Declare a DMA handle structure for the reception of the Data Flow channel. |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Declare a DMA handle structure for the reception of the Control Flow channel. |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) Enable the DMAx interface clock. |
<> | 144:ef7eb2e8f9f7 | 33 | (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters. |
<> | 144:ef7eb2e8f9f7 | 34 | (+++) Configure the DMA Channel. |
<> | 144:ef7eb2e8f9f7 | 35 | (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle. |
<> | 144:ef7eb2e8f9f7 | 36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the |
<> | 144:ef7eb2e8f9f7 | 37 | DMA CtrlRx/DataRx channel. |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits |
<> | 144:ef7eb2e8f9f7 | 40 | using HAL_SPDIFRX_Init() function. |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros |
<> | 144:ef7eb2e8f9f7 | 43 | __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. |
<> | 144:ef7eb2e8f9f7 | 44 | -@- Make sure that ck_spdif clock is configured. |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | (#) Three operation modes are available within this driver : |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | *** Polling mode for reception operation (for debug purpose) *** |
<> | 144:ef7eb2e8f9f7 | 49 | ================================================================ |
<> | 144:ef7eb2e8f9f7 | 50 | [..] |
<> | 144:ef7eb2e8f9f7 | 51 | (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow() |
<> | 144:ef7eb2e8f9f7 | 52 | (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow() |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | *** Interrupt mode for reception operation *** |
<> | 144:ef7eb2e8f9f7 | 55 | ========================================= |
<> | 144:ef7eb2e8f9f7 | 56 | [..] |
<> | 144:ef7eb2e8f9f7 | 57 | (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() |
<> | 144:ef7eb2e8f9f7 | 58 | (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() |
<> | 144:ef7eb2e8f9f7 | 59 | (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 60 | add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 61 | (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 62 | add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 63 | (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 64 | add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | *** DMA mode for reception operation *** |
<> | 144:ef7eb2e8f9f7 | 67 | ======================================== |
<> | 144:ef7eb2e8f9f7 | 68 | [..] |
<> | 144:ef7eb2e8f9f7 | 69 | (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() |
<> | 144:ef7eb2e8f9f7 | 70 | (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() |
<> | 144:ef7eb2e8f9f7 | 71 | (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 72 | add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 73 | (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can |
<> | 144:ef7eb2e8f9f7 | 74 | add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback |
<> | 144:ef7eb2e8f9f7 | 75 | (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 76 | add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback |
<> | 144:ef7eb2e8f9f7 | 77 | (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop() |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | *** SPDIFRX HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 80 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 81 | [..] |
<> | 144:ef7eb2e8f9f7 | 82 | Below the list of most used macros in USART HAL driver. |
<> | 144:ef7eb2e8f9f7 | 83 | (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State) |
<> | 144:ef7eb2e8f9f7 | 84 | (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) |
<> | 144:ef7eb2e8f9f7 | 85 | (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) |
<> | 144:ef7eb2e8f9f7 | 86 | (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts |
<> | 144:ef7eb2e8f9f7 | 87 | (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts |
<> | 144:ef7eb2e8f9f7 | 88 | (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not. |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | [..] |
<> | 144:ef7eb2e8f9f7 | 91 | (@) You can refer to the SPDIFRX HAL driver header file for more useful macros |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 94 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 95 | * @attention |
<> | 144:ef7eb2e8f9f7 | 96 | * |
<> | 144:ef7eb2e8f9f7 | 97 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 98 | * |
<> | 144:ef7eb2e8f9f7 | 99 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 100 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 101 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 102 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 103 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 104 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 105 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 106 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 107 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 108 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 109 | * |
<> | 144:ef7eb2e8f9f7 | 110 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 111 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 112 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 113 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 114 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 115 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 116 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 117 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 118 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 119 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 120 | * |
<> | 144:ef7eb2e8f9f7 | 121 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 122 | */ |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 125 | #include "stm32f7xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 126 | |
<> | 144:ef7eb2e8f9f7 | 127 | /** @addtogroup STM32F7xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 128 | * @{ |
<> | 144:ef7eb2e8f9f7 | 129 | */ |
<> | 144:ef7eb2e8f9f7 | 130 | /** @defgroup SPDIFRX SPDIFRX |
<> | 144:ef7eb2e8f9f7 | 131 | * @brief SPDIFRX HAL module driver |
<> | 144:ef7eb2e8f9f7 | 132 | * @{ |
<> | 144:ef7eb2e8f9f7 | 133 | */ |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | #ifdef HAL_SPDIFRX_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 138 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 139 | #define SPDIFRX_TIMEOUT_VALUE 0xFFFF |
<> | 144:ef7eb2e8f9f7 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 142 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 143 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 144 | /** @addtogroup SPDIFRX_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 145 | * @{ |
<> | 144:ef7eb2e8f9f7 | 146 | */ |
<> | 144:ef7eb2e8f9f7 | 147 | static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 148 | static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 149 | static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 150 | static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 151 | static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 152 | static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 153 | static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); |
<> | 144:ef7eb2e8f9f7 | 154 | static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); |
<> | 144:ef7eb2e8f9f7 | 155 | /** |
<> | 144:ef7eb2e8f9f7 | 156 | * @} |
<> | 144:ef7eb2e8f9f7 | 157 | */ |
<> | 144:ef7eb2e8f9f7 | 158 | /* Exported functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | /** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions |
<> | 144:ef7eb2e8f9f7 | 161 | * @{ |
<> | 144:ef7eb2e8f9f7 | 162 | */ |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | /** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 165 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 166 | * |
<> | 144:ef7eb2e8f9f7 | 167 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 168 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 169 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 170 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 171 | [..] This subsection provides a set of functions allowing to initialize and |
<> | 144:ef7eb2e8f9f7 | 172 | de-initialize the SPDIFRX peripheral: |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures |
<> | 144:ef7eb2e8f9f7 | 175 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
<> | 144:ef7eb2e8f9f7 | 176 | |
<> | 144:ef7eb2e8f9f7 | 177 | (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with |
<> | 144:ef7eb2e8f9f7 | 178 | the selected configuration: |
<> | 144:ef7eb2e8f9f7 | 179 | (++) Input Selection (IN0, IN1,...) |
<> | 144:ef7eb2e8f9f7 | 180 | (++) Maximum allowed re-tries during synchronization phase |
<> | 144:ef7eb2e8f9f7 | 181 | (++) Wait for activity on SPDIF selected input |
<> | 144:ef7eb2e8f9f7 | 182 | (++) Channel status selection (from channel A or B) |
<> | 144:ef7eb2e8f9f7 | 183 | (++) Data format (LSB, MSB, ...) |
<> | 144:ef7eb2e8f9f7 | 184 | (++) Stereo mode |
<> | 144:ef7eb2e8f9f7 | 185 | (++) User bits masking (PT,C,U,V,...) |
<> | 144:ef7eb2e8f9f7 | 186 | |
<> | 144:ef7eb2e8f9f7 | 187 | (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration |
<> | 144:ef7eb2e8f9f7 | 188 | of the selected SPDIFRXx peripheral. |
<> | 144:ef7eb2e8f9f7 | 189 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 190 | * @{ |
<> | 144:ef7eb2e8f9f7 | 191 | */ |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | /** |
<> | 144:ef7eb2e8f9f7 | 194 | * @brief Initializes the SPDIFRX according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 195 | * in the SPDIFRX_InitTypeDef and create the associated handle. |
<> | 144:ef7eb2e8f9f7 | 196 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 197 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 198 | */ |
<> | 144:ef7eb2e8f9f7 | 199 | HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 200 | { |
<> | 144:ef7eb2e8f9f7 | 201 | uint32_t tmpreg = 0; |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | /* Check the SPDIFRX handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 204 | if(hspdif == NULL) |
<> | 144:ef7eb2e8f9f7 | 205 | { |
<> | 144:ef7eb2e8f9f7 | 206 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 207 | } |
<> | 144:ef7eb2e8f9f7 | 208 | |
<> | 144:ef7eb2e8f9f7 | 209 | /* Check the SPDIFRX parameters */ |
<> | 144:ef7eb2e8f9f7 | 210 | assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode)); |
<> | 144:ef7eb2e8f9f7 | 211 | assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection)); |
<> | 144:ef7eb2e8f9f7 | 212 | assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries)); |
<> | 144:ef7eb2e8f9f7 | 213 | assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity)); |
<> | 144:ef7eb2e8f9f7 | 214 | assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection)); |
<> | 144:ef7eb2e8f9f7 | 215 | assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat)); |
<> | 144:ef7eb2e8f9f7 | 216 | assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask)); |
<> | 144:ef7eb2e8f9f7 | 217 | assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask)); |
<> | 144:ef7eb2e8f9f7 | 218 | assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask)); |
<> | 144:ef7eb2e8f9f7 | 219 | assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | if(hspdif->State == HAL_SPDIFRX_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 222 | { |
<> | 144:ef7eb2e8f9f7 | 223 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 224 | hspdif->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 225 | /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ |
<> | 144:ef7eb2e8f9f7 | 226 | HAL_SPDIFRX_MspInit(hspdif); |
<> | 144:ef7eb2e8f9f7 | 227 | } |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | /* SPDIFRX peripheral state is BUSY*/ |
<> | 144:ef7eb2e8f9f7 | 230 | hspdif->State = HAL_SPDIFRX_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /* Disable SPDIFRX interface (IDLE State) */ |
<> | 144:ef7eb2e8f9f7 | 233 | __HAL_SPDIFRX_IDLE(hspdif); |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | /* Reset the old SPDIFRX CR configuration */ |
<> | 144:ef7eb2e8f9f7 | 236 | tmpreg = hspdif->Instance->CR; |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | |
<> | 144:ef7eb2e8f9f7 | 239 | SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | |
<> | 144:ef7eb2e8f9f7 | 240 | SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL); |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | /* Sets the new configuration of the SPDIFRX peripheral */ |
<> | 144:ef7eb2e8f9f7 | 243 | tmpreg |= ((uint16_t) hspdif->Init.StereoMode | |
<> | 144:ef7eb2e8f9f7 | 244 | hspdif->Init.InputSelection | |
<> | 144:ef7eb2e8f9f7 | 245 | hspdif->Init.Retries | |
<> | 144:ef7eb2e8f9f7 | 246 | hspdif->Init.WaitForActivity | |
<> | 144:ef7eb2e8f9f7 | 247 | hspdif->Init.ChannelSelection | |
<> | 144:ef7eb2e8f9f7 | 248 | hspdif->Init.DataFormat | |
<> | 144:ef7eb2e8f9f7 | 249 | hspdif->Init.PreambleTypeMask | |
<> | 144:ef7eb2e8f9f7 | 250 | hspdif->Init.ChannelStatusMask | |
<> | 144:ef7eb2e8f9f7 | 251 | hspdif->Init.ValidityBitMask | |
<> | 144:ef7eb2e8f9f7 | 252 | hspdif->Init.ParityErrorMask); |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | hspdif->Instance->CR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /* SPDIFRX peripheral state is READY*/ |
<> | 144:ef7eb2e8f9f7 | 259 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 262 | } |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /** |
<> | 144:ef7eb2e8f9f7 | 265 | * @brief DeInitializes the SPDIFRX peripheral |
<> | 144:ef7eb2e8f9f7 | 266 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 267 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 268 | */ |
<> | 144:ef7eb2e8f9f7 | 269 | HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 270 | { |
<> | 144:ef7eb2e8f9f7 | 271 | /* Check the SPDIFRX handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 272 | if(hspdif == NULL) |
<> | 144:ef7eb2e8f9f7 | 273 | { |
<> | 144:ef7eb2e8f9f7 | 274 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 275 | } |
<> | 144:ef7eb2e8f9f7 | 276 | |
<> | 144:ef7eb2e8f9f7 | 277 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 278 | assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance)); |
<> | 144:ef7eb2e8f9f7 | 279 | |
<> | 144:ef7eb2e8f9f7 | 280 | hspdif->State = HAL_SPDIFRX_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | /* Disable SPDIFRX interface (IDLE state) */ |
<> | 144:ef7eb2e8f9f7 | 283 | __HAL_SPDIFRX_IDLE(hspdif); |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
<> | 144:ef7eb2e8f9f7 | 286 | HAL_SPDIFRX_MspDeInit(hspdif); |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 289 | |
<> | 144:ef7eb2e8f9f7 | 290 | /* SPDIFRX peripheral state is RESET*/ |
<> | 144:ef7eb2e8f9f7 | 291 | hspdif->State = HAL_SPDIFRX_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 294 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | /** |
<> | 144:ef7eb2e8f9f7 | 300 | * @brief SPDIFRX MSP Init |
<> | 144:ef7eb2e8f9f7 | 301 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 302 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 303 | */ |
<> | 144:ef7eb2e8f9f7 | 304 | __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 305 | { |
<> | 144:ef7eb2e8f9f7 | 306 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 307 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 310 | the HAL_SPDIFRX_MspInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 311 | */ |
<> | 144:ef7eb2e8f9f7 | 312 | } |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | /** |
<> | 144:ef7eb2e8f9f7 | 315 | * @brief SPDIFRX MSP DeInit |
<> | 144:ef7eb2e8f9f7 | 316 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 317 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 318 | */ |
<> | 144:ef7eb2e8f9f7 | 319 | __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 320 | { |
<> | 144:ef7eb2e8f9f7 | 321 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 322 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 325 | the HAL_SPDIFRX_MspDeInit could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 326 | */ |
<> | 144:ef7eb2e8f9f7 | 327 | } |
<> | 144:ef7eb2e8f9f7 | 328 | |
<> | 144:ef7eb2e8f9f7 | 329 | /** |
<> | 144:ef7eb2e8f9f7 | 330 | * @brief Sets the SPDIFRX dtat format according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 331 | * in the SPDIFRX_InitTypeDef. |
<> | 144:ef7eb2e8f9f7 | 332 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 333 | * @param sDataFormat: SPDIFRX data format |
<> | 144:ef7eb2e8f9f7 | 334 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 335 | */ |
<> | 144:ef7eb2e8f9f7 | 336 | HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) |
<> | 144:ef7eb2e8f9f7 | 337 | { |
<> | 144:ef7eb2e8f9f7 | 338 | uint32_t tmpreg = 0; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /* Check the SPDIFRX handle allocation */ |
<> | 144:ef7eb2e8f9f7 | 341 | if(hspdif == NULL) |
<> | 144:ef7eb2e8f9f7 | 342 | { |
<> | 144:ef7eb2e8f9f7 | 343 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 344 | } |
<> | 144:ef7eb2e8f9f7 | 345 | |
<> | 144:ef7eb2e8f9f7 | 346 | /* Check the SPDIFRX parameters */ |
<> | 144:ef7eb2e8f9f7 | 347 | assert_param(IS_STEREO_MODE(sDataFormat.StereoMode)); |
<> | 144:ef7eb2e8f9f7 | 348 | assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat)); |
<> | 144:ef7eb2e8f9f7 | 349 | assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask)); |
<> | 144:ef7eb2e8f9f7 | 350 | assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask)); |
<> | 144:ef7eb2e8f9f7 | 351 | assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask)); |
<> | 144:ef7eb2e8f9f7 | 352 | assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask)); |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /* Reset the old SPDIFRX CR configuration */ |
<> | 144:ef7eb2e8f9f7 | 355 | tmpreg = hspdif->Instance->CR; |
<> | 144:ef7eb2e8f9f7 | 356 | |
<> | 144:ef7eb2e8f9f7 | 357 | if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && |
<> | 144:ef7eb2e8f9f7 | 358 | (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || |
<> | 144:ef7eb2e8f9f7 | 359 | ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) |
<> | 144:ef7eb2e8f9f7 | 360 | { |
<> | 144:ef7eb2e8f9f7 | 361 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 362 | } |
<> | 144:ef7eb2e8f9f7 | 363 | |
<> | 144:ef7eb2e8f9f7 | 364 | tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | |
<> | 144:ef7eb2e8f9f7 | 365 | SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); |
<> | 144:ef7eb2e8f9f7 | 366 | |
<> | 144:ef7eb2e8f9f7 | 367 | /* Sets the new configuration of the SPDIFRX peripheral */ |
<> | 144:ef7eb2e8f9f7 | 368 | tmpreg |= ((uint16_t) sDataFormat.StereoMode | |
<> | 144:ef7eb2e8f9f7 | 369 | sDataFormat.DataFormat | |
<> | 144:ef7eb2e8f9f7 | 370 | sDataFormat.PreambleTypeMask | |
<> | 144:ef7eb2e8f9f7 | 371 | sDataFormat.ChannelStatusMask | |
<> | 144:ef7eb2e8f9f7 | 372 | sDataFormat.ValidityBitMask | |
<> | 144:ef7eb2e8f9f7 | 373 | sDataFormat.ParityErrorMask); |
<> | 144:ef7eb2e8f9f7 | 374 | |
<> | 144:ef7eb2e8f9f7 | 375 | hspdif->Instance->CR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 376 | |
<> | 144:ef7eb2e8f9f7 | 377 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 378 | } |
<> | 144:ef7eb2e8f9f7 | 379 | |
<> | 144:ef7eb2e8f9f7 | 380 | /** |
<> | 144:ef7eb2e8f9f7 | 381 | * @} |
<> | 144:ef7eb2e8f9f7 | 382 | */ |
<> | 144:ef7eb2e8f9f7 | 383 | |
<> | 144:ef7eb2e8f9f7 | 384 | /** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 385 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 386 | * |
<> | 144:ef7eb2e8f9f7 | 387 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 388 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 389 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 390 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 391 | [..] |
<> | 144:ef7eb2e8f9f7 | 392 | This subsection provides a set of functions allowing to manage the SPDIFRX data |
<> | 144:ef7eb2e8f9f7 | 393 | transfers. |
<> | 144:ef7eb2e8f9f7 | 394 | |
<> | 144:ef7eb2e8f9f7 | 395 | (#) There is two mode of transfer: |
<> | 144:ef7eb2e8f9f7 | 396 | (++) Blocking mode : The communication is performed in the polling mode. |
<> | 144:ef7eb2e8f9f7 | 397 | The status of all data processing is returned by the same function |
<> | 144:ef7eb2e8f9f7 | 398 | after finishing transfer. |
<> | 144:ef7eb2e8f9f7 | 399 | (++) No-Blocking mode : The communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 400 | or DMA. These functions return the status of the transfer start-up. |
<> | 144:ef7eb2e8f9f7 | 401 | The end of the data processing will be indicated through the |
<> | 144:ef7eb2e8f9f7 | 402 | dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 403 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 404 | |
<> | 144:ef7eb2e8f9f7 | 405 | (#) Blocking mode functions are : |
<> | 144:ef7eb2e8f9f7 | 406 | (++) HAL_SPDIFRX_ReceiveDataFlow() |
<> | 144:ef7eb2e8f9f7 | 407 | (++) HAL_SPDIFRX_ReceiveControlFlow() |
<> | 144:ef7eb2e8f9f7 | 408 | (+@) Do not use blocking mode to receive both control and data flow at the same time. |
<> | 144:ef7eb2e8f9f7 | 409 | |
<> | 144:ef7eb2e8f9f7 | 410 | (#) No-Blocking mode functions with Interrupt are : |
<> | 144:ef7eb2e8f9f7 | 411 | (++) HAL_SPDIFRX_ReceiveControlFlow_IT() |
<> | 144:ef7eb2e8f9f7 | 412 | (++) HAL_SPDIFRX_ReceiveDataFlow_IT() |
<> | 144:ef7eb2e8f9f7 | 413 | |
<> | 144:ef7eb2e8f9f7 | 414 | (#) No-Blocking mode functions with DMA are : |
<> | 144:ef7eb2e8f9f7 | 415 | (++) HAL_SPDIFRX_ReceiveControlFlow_DMA() |
<> | 144:ef7eb2e8f9f7 | 416 | (++) HAL_SPDIFRX_ReceiveDataFlow_DMA() |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
<> | 144:ef7eb2e8f9f7 | 419 | (++) HAL_SPDIFRX_RxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 420 | (++) HAL_SPDIFRX_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 421 | |
<> | 144:ef7eb2e8f9f7 | 422 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 423 | * @{ |
<> | 144:ef7eb2e8f9f7 | 424 | */ |
<> | 144:ef7eb2e8f9f7 | 425 | |
<> | 144:ef7eb2e8f9f7 | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | /** |
<> | 144:ef7eb2e8f9f7 | 428 | * @brief Receives an amount of data (Data Flow) in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 429 | * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 430 | * the configuration information for SPDIFRX module. |
<> | 144:ef7eb2e8f9f7 | 431 | * @param pData: Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 432 | * @param Size: Amount of data to be received |
<> | 144:ef7eb2e8f9f7 | 433 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 434 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 435 | */ |
<> | 144:ef7eb2e8f9f7 | 436 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 437 | { |
<> | 144:ef7eb2e8f9f7 | 438 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | if((pData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 441 | { |
<> | 144:ef7eb2e8f9f7 | 442 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 443 | } |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | if(hspdif->State == HAL_SPDIFRX_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 446 | { |
<> | 144:ef7eb2e8f9f7 | 447 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 448 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 449 | |
<> | 144:ef7eb2e8f9f7 | 450 | hspdif->State = HAL_SPDIFRX_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 451 | |
<> | 144:ef7eb2e8f9f7 | 452 | /* Start synchronisation */ |
<> | 144:ef7eb2e8f9f7 | 453 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 456 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 457 | |
<> | 144:ef7eb2e8f9f7 | 458 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 459 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 460 | { |
<> | 144:ef7eb2e8f9f7 | 461 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 462 | } |
<> | 144:ef7eb2e8f9f7 | 463 | |
<> | 144:ef7eb2e8f9f7 | 464 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 465 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | /* Receive data flow */ |
<> | 144:ef7eb2e8f9f7 | 468 | while(Size > 0U) |
<> | 144:ef7eb2e8f9f7 | 469 | { |
<> | 144:ef7eb2e8f9f7 | 470 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 471 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 472 | |
<> | 144:ef7eb2e8f9f7 | 473 | /* Wait until RXNE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 474 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 475 | { |
<> | 144:ef7eb2e8f9f7 | 476 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 477 | } |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | (*pData++) = hspdif->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 480 | Size--; |
<> | 144:ef7eb2e8f9f7 | 481 | } |
<> | 144:ef7eb2e8f9f7 | 482 | |
<> | 144:ef7eb2e8f9f7 | 483 | /* SPDIFRX ready */ |
<> | 144:ef7eb2e8f9f7 | 484 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 485 | |
<> | 144:ef7eb2e8f9f7 | 486 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 487 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 488 | |
<> | 144:ef7eb2e8f9f7 | 489 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 490 | } |
<> | 144:ef7eb2e8f9f7 | 491 | else |
<> | 144:ef7eb2e8f9f7 | 492 | { |
<> | 144:ef7eb2e8f9f7 | 493 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 494 | } |
<> | 144:ef7eb2e8f9f7 | 495 | } |
<> | 144:ef7eb2e8f9f7 | 496 | |
<> | 144:ef7eb2e8f9f7 | 497 | /** |
<> | 144:ef7eb2e8f9f7 | 498 | * @brief Receives an amount of data (Control Flow) in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 499 | * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 500 | * the configuration information for SPDIFRX module. |
<> | 144:ef7eb2e8f9f7 | 501 | * @param pData: Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 502 | * @param Size: Amount of data to be received |
<> | 144:ef7eb2e8f9f7 | 503 | * @param Timeout: Timeout duration |
<> | 144:ef7eb2e8f9f7 | 504 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 505 | */ |
<> | 144:ef7eb2e8f9f7 | 506 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 507 | { |
<> | 144:ef7eb2e8f9f7 | 508 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 509 | |
<> | 144:ef7eb2e8f9f7 | 510 | if((pData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 511 | { |
<> | 144:ef7eb2e8f9f7 | 512 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 513 | } |
<> | 144:ef7eb2e8f9f7 | 514 | |
<> | 144:ef7eb2e8f9f7 | 515 | if(hspdif->State == HAL_SPDIFRX_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 516 | { |
<> | 144:ef7eb2e8f9f7 | 517 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 518 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | hspdif->State = HAL_SPDIFRX_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 521 | |
<> | 144:ef7eb2e8f9f7 | 522 | /* Start synchronization */ |
<> | 144:ef7eb2e8f9f7 | 523 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 524 | |
<> | 144:ef7eb2e8f9f7 | 525 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 526 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 527 | |
<> | 144:ef7eb2e8f9f7 | 528 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 529 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 530 | { |
<> | 144:ef7eb2e8f9f7 | 531 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 532 | } |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 535 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | /* Receive control flow */ |
<> | 144:ef7eb2e8f9f7 | 538 | while(Size > 0U) |
<> | 144:ef7eb2e8f9f7 | 539 | { |
<> | 144:ef7eb2e8f9f7 | 540 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 541 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 542 | |
<> | 144:ef7eb2e8f9f7 | 543 | /* Wait until CSRNE flag is set */ |
<> | 144:ef7eb2e8f9f7 | 544 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 545 | { |
<> | 144:ef7eb2e8f9f7 | 546 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 547 | } |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | (*pData++) = hspdif->Instance->CSR; |
<> | 144:ef7eb2e8f9f7 | 550 | Size--; |
<> | 144:ef7eb2e8f9f7 | 551 | } |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | /* SPDIFRX ready */ |
<> | 144:ef7eb2e8f9f7 | 554 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 555 | |
<> | 144:ef7eb2e8f9f7 | 556 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 557 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 558 | |
<> | 144:ef7eb2e8f9f7 | 559 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 560 | } |
<> | 144:ef7eb2e8f9f7 | 561 | else |
<> | 144:ef7eb2e8f9f7 | 562 | { |
<> | 144:ef7eb2e8f9f7 | 563 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 564 | } |
<> | 144:ef7eb2e8f9f7 | 565 | } |
<> | 144:ef7eb2e8f9f7 | 566 | |
<> | 144:ef7eb2e8f9f7 | 567 | /** |
<> | 144:ef7eb2e8f9f7 | 568 | * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 569 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 570 | * @param pData: a 32-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 571 | * @param Size: number of data sample to be received . |
<> | 144:ef7eb2e8f9f7 | 572 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 573 | */ |
<> | 144:ef7eb2e8f9f7 | 574 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 575 | { |
<> | 144:ef7eb2e8f9f7 | 576 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) |
<> | 144:ef7eb2e8f9f7 | 579 | { |
<> | 144:ef7eb2e8f9f7 | 580 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 581 | { |
<> | 144:ef7eb2e8f9f7 | 582 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 583 | } |
<> | 144:ef7eb2e8f9f7 | 584 | |
<> | 144:ef7eb2e8f9f7 | 585 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 586 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 587 | |
<> | 144:ef7eb2e8f9f7 | 588 | hspdif->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 589 | hspdif->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 590 | hspdif->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | /* Check if a receive process is ongoing or not */ |
<> | 144:ef7eb2e8f9f7 | 595 | hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 596 | |
<> | 144:ef7eb2e8f9f7 | 597 | |
<> | 144:ef7eb2e8f9f7 | 598 | /* Enable the SPDIFRX PE Error Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 599 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); |
<> | 144:ef7eb2e8f9f7 | 600 | |
<> | 144:ef7eb2e8f9f7 | 601 | /* Enable the SPDIFRX OVR Error Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 602 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); |
<> | 144:ef7eb2e8f9f7 | 603 | |
<> | 144:ef7eb2e8f9f7 | 604 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 605 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 606 | |
<> | 144:ef7eb2e8f9f7 | 607 | /* Enable the SPDIFRX RXNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 608 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 609 | |
<> | 144:ef7eb2e8f9f7 | 610 | if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) |
<> | 144:ef7eb2e8f9f7 | 611 | { |
<> | 144:ef7eb2e8f9f7 | 612 | /* Start synchronization */ |
<> | 144:ef7eb2e8f9f7 | 613 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 614 | |
<> | 144:ef7eb2e8f9f7 | 615 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 616 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 617 | |
<> | 144:ef7eb2e8f9f7 | 618 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 619 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 620 | { |
<> | 144:ef7eb2e8f9f7 | 621 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 622 | } |
<> | 144:ef7eb2e8f9f7 | 623 | |
<> | 144:ef7eb2e8f9f7 | 624 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 625 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 626 | } |
<> | 144:ef7eb2e8f9f7 | 627 | |
<> | 144:ef7eb2e8f9f7 | 628 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 629 | } |
<> | 144:ef7eb2e8f9f7 | 630 | else |
<> | 144:ef7eb2e8f9f7 | 631 | { |
<> | 144:ef7eb2e8f9f7 | 632 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 633 | } |
<> | 144:ef7eb2e8f9f7 | 634 | } |
<> | 144:ef7eb2e8f9f7 | 635 | |
<> | 144:ef7eb2e8f9f7 | 636 | /** |
<> | 144:ef7eb2e8f9f7 | 637 | * @brief Receive an amount of data (Control Flow) with Interrupt |
<> | 144:ef7eb2e8f9f7 | 638 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 639 | * @param pData: a 32-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 640 | * @param Size: number of data sample (Control Flow) to be received : |
<> | 144:ef7eb2e8f9f7 | 641 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 642 | */ |
<> | 144:ef7eb2e8f9f7 | 643 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 644 | { |
<> | 144:ef7eb2e8f9f7 | 645 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 646 | |
<> | 144:ef7eb2e8f9f7 | 647 | if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) |
<> | 144:ef7eb2e8f9f7 | 648 | { |
<> | 144:ef7eb2e8f9f7 | 649 | if((pData == NULL ) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 650 | { |
<> | 144:ef7eb2e8f9f7 | 651 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 652 | } |
<> | 144:ef7eb2e8f9f7 | 653 | |
<> | 144:ef7eb2e8f9f7 | 654 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 655 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 656 | |
<> | 144:ef7eb2e8f9f7 | 657 | hspdif->pCsBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 658 | hspdif->CsXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 659 | hspdif->CsXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | /* Check if a receive process is ongoing or not */ |
<> | 144:ef7eb2e8f9f7 | 664 | hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; |
<> | 144:ef7eb2e8f9f7 | 665 | |
<> | 144:ef7eb2e8f9f7 | 666 | |
<> | 144:ef7eb2e8f9f7 | 667 | /* Enable the SPDIFRX PE Error Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 668 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | /* Enable the SPDIFRX OVR Error Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 671 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); |
<> | 144:ef7eb2e8f9f7 | 672 | |
<> | 144:ef7eb2e8f9f7 | 673 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 674 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | /* Enable the SPDIFRX CSRNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 677 | __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); |
<> | 144:ef7eb2e8f9f7 | 678 | |
<> | 144:ef7eb2e8f9f7 | 679 | if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) |
<> | 144:ef7eb2e8f9f7 | 680 | { |
<> | 144:ef7eb2e8f9f7 | 681 | /* Start synchronization */ |
<> | 144:ef7eb2e8f9f7 | 682 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 683 | |
<> | 144:ef7eb2e8f9f7 | 684 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 685 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 686 | |
<> | 144:ef7eb2e8f9f7 | 687 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 688 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 689 | { |
<> | 144:ef7eb2e8f9f7 | 690 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 691 | } |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 694 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 695 | } |
<> | 144:ef7eb2e8f9f7 | 696 | |
<> | 144:ef7eb2e8f9f7 | 697 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 698 | } |
<> | 144:ef7eb2e8f9f7 | 699 | else |
<> | 144:ef7eb2e8f9f7 | 700 | { |
<> | 144:ef7eb2e8f9f7 | 701 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 702 | } |
<> | 144:ef7eb2e8f9f7 | 703 | } |
<> | 144:ef7eb2e8f9f7 | 704 | |
<> | 144:ef7eb2e8f9f7 | 705 | /** |
<> | 144:ef7eb2e8f9f7 | 706 | * @brief Receive an amount of data (Data Flow) mode with DMA |
<> | 144:ef7eb2e8f9f7 | 707 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 708 | * @param pData: a 32-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 709 | * @param Size: number of data sample to be received : |
<> | 144:ef7eb2e8f9f7 | 710 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 711 | */ |
<> | 144:ef7eb2e8f9f7 | 712 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 713 | { |
<> | 144:ef7eb2e8f9f7 | 714 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 715 | |
<> | 144:ef7eb2e8f9f7 | 716 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 717 | { |
<> | 144:ef7eb2e8f9f7 | 718 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 719 | } |
<> | 144:ef7eb2e8f9f7 | 720 | |
<> | 144:ef7eb2e8f9f7 | 721 | if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_CX)) |
<> | 144:ef7eb2e8f9f7 | 722 | { |
<> | 144:ef7eb2e8f9f7 | 723 | hspdif->pRxBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 724 | hspdif->RxXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 725 | hspdif->RxXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 726 | |
<> | 144:ef7eb2e8f9f7 | 727 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 728 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 729 | |
<> | 144:ef7eb2e8f9f7 | 730 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 731 | hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 732 | |
<> | 144:ef7eb2e8f9f7 | 733 | /* Set the SPDIFRX Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 734 | hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | /* Set the SPDIFRX Rx DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 737 | hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt; |
<> | 144:ef7eb2e8f9f7 | 738 | |
<> | 144:ef7eb2e8f9f7 | 739 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 740 | hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; |
<> | 144:ef7eb2e8f9f7 | 741 | |
<> | 144:ef7eb2e8f9f7 | 742 | /* Enable the DMA request */ |
<> | 144:ef7eb2e8f9f7 | 743 | HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size); |
<> | 144:ef7eb2e8f9f7 | 744 | |
<> | 144:ef7eb2e8f9f7 | 745 | /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ |
<> | 144:ef7eb2e8f9f7 | 746 | hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 747 | |
<> | 144:ef7eb2e8f9f7 | 748 | if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) |
<> | 144:ef7eb2e8f9f7 | 749 | { |
<> | 144:ef7eb2e8f9f7 | 750 | /* Start synchronization */ |
<> | 144:ef7eb2e8f9f7 | 751 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 754 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 757 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 758 | { |
<> | 144:ef7eb2e8f9f7 | 759 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 760 | } |
<> | 144:ef7eb2e8f9f7 | 761 | |
<> | 144:ef7eb2e8f9f7 | 762 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 763 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 764 | } |
<> | 144:ef7eb2e8f9f7 | 765 | |
<> | 144:ef7eb2e8f9f7 | 766 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 767 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 768 | |
<> | 144:ef7eb2e8f9f7 | 769 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 770 | } |
<> | 144:ef7eb2e8f9f7 | 771 | else |
<> | 144:ef7eb2e8f9f7 | 772 | { |
<> | 144:ef7eb2e8f9f7 | 773 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 774 | } |
<> | 144:ef7eb2e8f9f7 | 775 | } |
<> | 144:ef7eb2e8f9f7 | 776 | |
<> | 144:ef7eb2e8f9f7 | 777 | /** |
<> | 144:ef7eb2e8f9f7 | 778 | * @brief Receive an amount of data (Control Flow) with DMA |
<> | 144:ef7eb2e8f9f7 | 779 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 780 | * @param pData: a 32-bit pointer to the Receive data buffer. |
<> | 144:ef7eb2e8f9f7 | 781 | * @param Size: number of data (Control Flow) sample to be received : |
<> | 144:ef7eb2e8f9f7 | 782 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 783 | */ |
<> | 144:ef7eb2e8f9f7 | 784 | HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 785 | { |
<> | 144:ef7eb2e8f9f7 | 786 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 787 | |
<> | 144:ef7eb2e8f9f7 | 788 | if((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 789 | { |
<> | 144:ef7eb2e8f9f7 | 790 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 791 | } |
<> | 144:ef7eb2e8f9f7 | 792 | |
<> | 144:ef7eb2e8f9f7 | 793 | if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) |
<> | 144:ef7eb2e8f9f7 | 794 | { |
<> | 144:ef7eb2e8f9f7 | 795 | hspdif->pCsBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 796 | hspdif->CsXferSize = Size; |
<> | 144:ef7eb2e8f9f7 | 797 | hspdif->CsXferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 798 | |
<> | 144:ef7eb2e8f9f7 | 799 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 800 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 801 | |
<> | 144:ef7eb2e8f9f7 | 802 | hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 803 | hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; |
<> | 144:ef7eb2e8f9f7 | 804 | |
<> | 144:ef7eb2e8f9f7 | 805 | /* Set the SPDIFRX Rx DMA Half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 806 | hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; |
<> | 144:ef7eb2e8f9f7 | 807 | |
<> | 144:ef7eb2e8f9f7 | 808 | /* Set the SPDIFRX Rx DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 809 | hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; |
<> | 144:ef7eb2e8f9f7 | 810 | |
<> | 144:ef7eb2e8f9f7 | 811 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 812 | hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; |
<> | 144:ef7eb2e8f9f7 | 813 | |
<> | 144:ef7eb2e8f9f7 | 814 | /* Enable the DMA request */ |
<> | 144:ef7eb2e8f9f7 | 815 | HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size); |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ |
<> | 144:ef7eb2e8f9f7 | 818 | hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) |
<> | 144:ef7eb2e8f9f7 | 821 | { |
<> | 144:ef7eb2e8f9f7 | 822 | /* Start synchronization */ |
<> | 144:ef7eb2e8f9f7 | 823 | __HAL_SPDIFRX_SYNC(hspdif); |
<> | 144:ef7eb2e8f9f7 | 824 | |
<> | 144:ef7eb2e8f9f7 | 825 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 826 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | /* Wait until SYNCD flag is set */ |
<> | 144:ef7eb2e8f9f7 | 829 | if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 830 | { |
<> | 144:ef7eb2e8f9f7 | 831 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 832 | } |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | /* Start reception */ |
<> | 144:ef7eb2e8f9f7 | 835 | __HAL_SPDIFRX_RCV(hspdif); |
<> | 144:ef7eb2e8f9f7 | 836 | } |
<> | 144:ef7eb2e8f9f7 | 837 | |
<> | 144:ef7eb2e8f9f7 | 838 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 839 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 840 | |
<> | 144:ef7eb2e8f9f7 | 841 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 842 | } |
<> | 144:ef7eb2e8f9f7 | 843 | else |
<> | 144:ef7eb2e8f9f7 | 844 | { |
<> | 144:ef7eb2e8f9f7 | 845 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 846 | } |
<> | 144:ef7eb2e8f9f7 | 847 | } |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | /** |
<> | 144:ef7eb2e8f9f7 | 850 | * @brief stop the audio stream receive from the Media. |
<> | 144:ef7eb2e8f9f7 | 851 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 852 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 853 | */ |
<> | 144:ef7eb2e8f9f7 | 854 | HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 855 | { |
<> | 144:ef7eb2e8f9f7 | 856 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 857 | __HAL_LOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 858 | |
<> | 144:ef7eb2e8f9f7 | 859 | /* Disable the SPDIFRX DMA requests */ |
<> | 144:ef7eb2e8f9f7 | 860 | hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 861 | hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); |
<> | 144:ef7eb2e8f9f7 | 862 | |
<> | 144:ef7eb2e8f9f7 | 863 | /* Disable the SPDIFRX DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 864 | __HAL_DMA_DISABLE(hspdif->hdmaDrRx); |
<> | 144:ef7eb2e8f9f7 | 865 | __HAL_DMA_DISABLE(hspdif->hdmaCsRx); |
<> | 144:ef7eb2e8f9f7 | 866 | |
<> | 144:ef7eb2e8f9f7 | 867 | /* Disable SPDIFRX peripheral */ |
<> | 144:ef7eb2e8f9f7 | 868 | __HAL_SPDIFRX_IDLE(hspdif); |
<> | 144:ef7eb2e8f9f7 | 869 | |
<> | 144:ef7eb2e8f9f7 | 870 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 871 | |
<> | 144:ef7eb2e8f9f7 | 872 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 873 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 874 | |
<> | 144:ef7eb2e8f9f7 | 875 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 876 | } |
<> | 144:ef7eb2e8f9f7 | 877 | |
<> | 144:ef7eb2e8f9f7 | 878 | /** |
<> | 144:ef7eb2e8f9f7 | 879 | * @brief This function handles SPDIFRX interrupt request. |
<> | 144:ef7eb2e8f9f7 | 880 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 881 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 882 | */ |
<> | 144:ef7eb2e8f9f7 | 883 | void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 884 | { |
<> | 144:ef7eb2e8f9f7 | 885 | /* SPDIFRX in mode Data Flow Reception ------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 886 | if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_RXNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 887 | { |
<> | 144:ef7eb2e8f9f7 | 888 | __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 889 | SPDIFRX_ReceiveDataFlow_IT(hspdif); |
<> | 144:ef7eb2e8f9f7 | 890 | } |
<> | 144:ef7eb2e8f9f7 | 891 | |
<> | 144:ef7eb2e8f9f7 | 892 | /* SPDIFRX in mode Control Flow Reception ------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 893 | if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_CSRNE) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_CSRNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 894 | { |
<> | 144:ef7eb2e8f9f7 | 895 | __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); |
<> | 144:ef7eb2e8f9f7 | 896 | SPDIFRX_ReceiveControlFlow_IT(hspdif); |
<> | 144:ef7eb2e8f9f7 | 897 | } |
<> | 144:ef7eb2e8f9f7 | 898 | |
<> | 144:ef7eb2e8f9f7 | 899 | /* SPDIFRX Overrun error interrupt occurred ---------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 900 | if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_OVR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_OVRIE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 901 | { |
<> | 144:ef7eb2e8f9f7 | 902 | __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 903 | |
<> | 144:ef7eb2e8f9f7 | 904 | /* Change the SPDIFRX error code */ |
<> | 144:ef7eb2e8f9f7 | 905 | hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR; |
<> | 144:ef7eb2e8f9f7 | 906 | |
<> | 144:ef7eb2e8f9f7 | 907 | /* the transfer is not stopped */ |
<> | 144:ef7eb2e8f9f7 | 908 | HAL_SPDIFRX_ErrorCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 909 | } |
<> | 144:ef7eb2e8f9f7 | 910 | |
<> | 144:ef7eb2e8f9f7 | 911 | /* SPDIFRX Parity error interrupt occurred ---------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 912 | if((__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_PERR) != RESET) && (__HAL_SPDIFRX_GET_IT_SOURCE(hspdif, SPDIFRX_IT_PERRIE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 913 | { |
<> | 144:ef7eb2e8f9f7 | 914 | __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_FLAG_PERR); |
<> | 144:ef7eb2e8f9f7 | 915 | |
<> | 144:ef7eb2e8f9f7 | 916 | /* Change the SPDIFRX error code */ |
<> | 144:ef7eb2e8f9f7 | 917 | hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE; |
<> | 144:ef7eb2e8f9f7 | 918 | |
<> | 144:ef7eb2e8f9f7 | 919 | /* the transfer is not stopped */ |
<> | 144:ef7eb2e8f9f7 | 920 | HAL_SPDIFRX_ErrorCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 921 | } |
<> | 144:ef7eb2e8f9f7 | 922 | } |
<> | 144:ef7eb2e8f9f7 | 923 | |
<> | 144:ef7eb2e8f9f7 | 924 | /** |
<> | 144:ef7eb2e8f9f7 | 925 | * @brief Rx Transfer (Data flow) half completed callbacks |
<> | 144:ef7eb2e8f9f7 | 926 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 927 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 928 | */ |
<> | 144:ef7eb2e8f9f7 | 929 | __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 930 | { |
<> | 144:ef7eb2e8f9f7 | 931 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 932 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 933 | |
<> | 144:ef7eb2e8f9f7 | 934 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 935 | the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 936 | */ |
<> | 144:ef7eb2e8f9f7 | 937 | } |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | /** |
<> | 144:ef7eb2e8f9f7 | 940 | * @brief Rx Transfer (Data flow) completed callbacks |
<> | 144:ef7eb2e8f9f7 | 941 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 942 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 943 | */ |
<> | 144:ef7eb2e8f9f7 | 944 | __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 945 | { |
<> | 144:ef7eb2e8f9f7 | 946 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 947 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 948 | |
<> | 144:ef7eb2e8f9f7 | 949 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 950 | the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 951 | */ |
<> | 144:ef7eb2e8f9f7 | 952 | } |
<> | 144:ef7eb2e8f9f7 | 953 | |
<> | 144:ef7eb2e8f9f7 | 954 | /** |
<> | 144:ef7eb2e8f9f7 | 955 | * @brief Rx (Control flow) Transfer half completed callbacks |
<> | 144:ef7eb2e8f9f7 | 956 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 957 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 958 | */ |
<> | 144:ef7eb2e8f9f7 | 959 | __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 960 | { |
<> | 144:ef7eb2e8f9f7 | 961 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 962 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 965 | the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 966 | */ |
<> | 144:ef7eb2e8f9f7 | 967 | } |
<> | 144:ef7eb2e8f9f7 | 968 | |
<> | 144:ef7eb2e8f9f7 | 969 | /** |
<> | 144:ef7eb2e8f9f7 | 970 | * @brief Rx Transfer (Control flow) completed callbacks |
<> | 144:ef7eb2e8f9f7 | 971 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 972 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 973 | */ |
<> | 144:ef7eb2e8f9f7 | 974 | __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 975 | { |
<> | 144:ef7eb2e8f9f7 | 976 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 977 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 978 | |
<> | 144:ef7eb2e8f9f7 | 979 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 980 | the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 981 | */ |
<> | 144:ef7eb2e8f9f7 | 982 | } |
<> | 144:ef7eb2e8f9f7 | 983 | |
<> | 144:ef7eb2e8f9f7 | 984 | /** |
<> | 144:ef7eb2e8f9f7 | 985 | * @brief SPDIFRX error callbacks |
<> | 144:ef7eb2e8f9f7 | 986 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 987 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 988 | */ |
<> | 144:ef7eb2e8f9f7 | 989 | __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 990 | { |
<> | 144:ef7eb2e8f9f7 | 991 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 992 | UNUSED(hspdif); |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 995 | the HAL_SPDIFRX_ErrorCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 996 | */ |
<> | 144:ef7eb2e8f9f7 | 997 | } |
<> | 144:ef7eb2e8f9f7 | 998 | |
<> | 144:ef7eb2e8f9f7 | 999 | /** |
<> | 144:ef7eb2e8f9f7 | 1000 | * @} |
<> | 144:ef7eb2e8f9f7 | 1001 | */ |
<> | 144:ef7eb2e8f9f7 | 1002 | |
<> | 144:ef7eb2e8f9f7 | 1003 | /** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions |
<> | 144:ef7eb2e8f9f7 | 1004 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1005 | * |
<> | 144:ef7eb2e8f9f7 | 1006 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1007 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1008 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1009 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1010 | [..] |
<> | 144:ef7eb2e8f9f7 | 1011 | This subsection permit to get in run-time the status of the peripheral |
<> | 144:ef7eb2e8f9f7 | 1012 | and the data flow. |
<> | 144:ef7eb2e8f9f7 | 1013 | |
<> | 144:ef7eb2e8f9f7 | 1014 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1015 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1016 | */ |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | /** |
<> | 144:ef7eb2e8f9f7 | 1019 | * @brief Return the SPDIFRX state |
<> | 144:ef7eb2e8f9f7 | 1020 | * @param hspdif : SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 1021 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1022 | */ |
<> | 144:ef7eb2e8f9f7 | 1023 | HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 1024 | { |
<> | 144:ef7eb2e8f9f7 | 1025 | return hspdif->State; |
<> | 144:ef7eb2e8f9f7 | 1026 | } |
<> | 144:ef7eb2e8f9f7 | 1027 | |
<> | 144:ef7eb2e8f9f7 | 1028 | /** |
<> | 144:ef7eb2e8f9f7 | 1029 | * @brief Return the SPDIFRX error code |
<> | 144:ef7eb2e8f9f7 | 1030 | * @param hspdif : SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 1031 | * @retval SPDIFRX Error Code |
<> | 144:ef7eb2e8f9f7 | 1032 | */ |
<> | 144:ef7eb2e8f9f7 | 1033 | uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 1034 | { |
<> | 144:ef7eb2e8f9f7 | 1035 | return hspdif->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1036 | } |
<> | 144:ef7eb2e8f9f7 | 1037 | |
<> | 144:ef7eb2e8f9f7 | 1038 | /** |
<> | 144:ef7eb2e8f9f7 | 1039 | * @} |
<> | 144:ef7eb2e8f9f7 | 1040 | */ |
<> | 144:ef7eb2e8f9f7 | 1041 | |
<> | 144:ef7eb2e8f9f7 | 1042 | /** |
<> | 144:ef7eb2e8f9f7 | 1043 | * @brief DMA SPDIFRX receive process (Data flow) complete callback |
<> | 144:ef7eb2e8f9f7 | 1044 | * @param hdma : DMA handle |
<> | 144:ef7eb2e8f9f7 | 1045 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1046 | */ |
<> | 144:ef7eb2e8f9f7 | 1047 | static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1048 | { |
<> | 144:ef7eb2e8f9f7 | 1049 | SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1050 | |
<> | 144:ef7eb2e8f9f7 | 1051 | /* Disable Rx DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1052 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
<> | 144:ef7eb2e8f9f7 | 1053 | { |
<> | 144:ef7eb2e8f9f7 | 1054 | hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1055 | hspdif->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1056 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1057 | } |
<> | 144:ef7eb2e8f9f7 | 1058 | HAL_SPDIFRX_RxCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1059 | } |
<> | 144:ef7eb2e8f9f7 | 1060 | |
<> | 144:ef7eb2e8f9f7 | 1061 | /** |
<> | 144:ef7eb2e8f9f7 | 1062 | * @brief DMA SPDIFRX receive process (Data flow) half complete callback |
<> | 144:ef7eb2e8f9f7 | 1063 | * @param hdma : DMA handle |
<> | 144:ef7eb2e8f9f7 | 1064 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1065 | */ |
<> | 144:ef7eb2e8f9f7 | 1066 | static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1067 | { |
<> | 144:ef7eb2e8f9f7 | 1068 | SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1069 | |
<> | 144:ef7eb2e8f9f7 | 1070 | HAL_SPDIFRX_RxHalfCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1071 | } |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | |
<> | 144:ef7eb2e8f9f7 | 1074 | /** |
<> | 144:ef7eb2e8f9f7 | 1075 | * @brief DMA SPDIFRX receive process (Control flow) complete callback |
<> | 144:ef7eb2e8f9f7 | 1076 | * @param hdma : DMA handle |
<> | 144:ef7eb2e8f9f7 | 1077 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1078 | */ |
<> | 144:ef7eb2e8f9f7 | 1079 | static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1080 | { |
<> | 144:ef7eb2e8f9f7 | 1081 | SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1082 | |
<> | 144:ef7eb2e8f9f7 | 1083 | /* Disable Cb DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1084 | hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); |
<> | 144:ef7eb2e8f9f7 | 1085 | hspdif->CsXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1086 | |
<> | 144:ef7eb2e8f9f7 | 1087 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1088 | HAL_SPDIFRX_CxCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1089 | } |
<> | 144:ef7eb2e8f9f7 | 1090 | |
<> | 144:ef7eb2e8f9f7 | 1091 | /** |
<> | 144:ef7eb2e8f9f7 | 1092 | * @brief DMA SPDIFRX receive process (Control flow) half complete callback |
<> | 144:ef7eb2e8f9f7 | 1093 | * @param hdma : DMA handle |
<> | 144:ef7eb2e8f9f7 | 1094 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1095 | */ |
<> | 144:ef7eb2e8f9f7 | 1096 | static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1097 | { |
<> | 144:ef7eb2e8f9f7 | 1098 | SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1099 | |
<> | 144:ef7eb2e8f9f7 | 1100 | HAL_SPDIFRX_CxHalfCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1101 | } |
<> | 144:ef7eb2e8f9f7 | 1102 | |
<> | 144:ef7eb2e8f9f7 | 1103 | /** |
<> | 144:ef7eb2e8f9f7 | 1104 | * @brief DMA SPDIFRX communication error callback |
<> | 144:ef7eb2e8f9f7 | 1105 | * @param hdma : DMA handle |
<> | 144:ef7eb2e8f9f7 | 1106 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1107 | */ |
<> | 144:ef7eb2e8f9f7 | 1108 | static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 1109 | { |
<> | 144:ef7eb2e8f9f7 | 1110 | SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 1111 | |
<> | 144:ef7eb2e8f9f7 | 1112 | /* Disable Rx and Cb DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1113 | hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); |
<> | 144:ef7eb2e8f9f7 | 1114 | hspdif->RxXferCount = 0; |
<> | 144:ef7eb2e8f9f7 | 1115 | |
<> | 144:ef7eb2e8f9f7 | 1116 | hspdif->State= HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1117 | |
<> | 144:ef7eb2e8f9f7 | 1118 | /* Set the error code and execute error callback*/ |
<> | 144:ef7eb2e8f9f7 | 1119 | hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1120 | HAL_SPDIFRX_ErrorCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1121 | } |
<> | 144:ef7eb2e8f9f7 | 1122 | |
<> | 144:ef7eb2e8f9f7 | 1123 | /** |
<> | 144:ef7eb2e8f9f7 | 1124 | * @brief Receive an amount of data (Data Flow) with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1125 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 1126 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1127 | */ |
<> | 144:ef7eb2e8f9f7 | 1128 | static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 1129 | { |
<> | 144:ef7eb2e8f9f7 | 1130 | /* Receive data */ |
<> | 144:ef7eb2e8f9f7 | 1131 | (*hspdif->pRxBuffPtr++) = hspdif->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1132 | hspdif->RxXferCount--; |
<> | 144:ef7eb2e8f9f7 | 1133 | |
<> | 144:ef7eb2e8f9f7 | 1134 | if(hspdif->RxXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 1135 | { |
<> | 144:ef7eb2e8f9f7 | 1136 | /* Disable RXNE/PE and OVR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1137 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 1138 | |
<> | 144:ef7eb2e8f9f7 | 1139 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1140 | |
<> | 144:ef7eb2e8f9f7 | 1141 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1142 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1143 | |
<> | 144:ef7eb2e8f9f7 | 1144 | HAL_SPDIFRX_RxCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1145 | } |
<> | 144:ef7eb2e8f9f7 | 1146 | } |
<> | 144:ef7eb2e8f9f7 | 1147 | |
<> | 144:ef7eb2e8f9f7 | 1148 | /** |
<> | 144:ef7eb2e8f9f7 | 1149 | * @brief Receive an amount of data (Control Flow) with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1150 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 1151 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1152 | */ |
<> | 144:ef7eb2e8f9f7 | 1153 | static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) |
<> | 144:ef7eb2e8f9f7 | 1154 | { |
<> | 144:ef7eb2e8f9f7 | 1155 | /* Receive data */ |
<> | 144:ef7eb2e8f9f7 | 1156 | (*hspdif->pCsBuffPtr++) = hspdif->Instance->CSR; |
<> | 144:ef7eb2e8f9f7 | 1157 | hspdif->CsXferCount--; |
<> | 144:ef7eb2e8f9f7 | 1158 | |
<> | 144:ef7eb2e8f9f7 | 1159 | if(hspdif->CsXferCount == 0) |
<> | 144:ef7eb2e8f9f7 | 1160 | { |
<> | 144:ef7eb2e8f9f7 | 1161 | /* Disable CSRNE interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1162 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); |
<> | 144:ef7eb2e8f9f7 | 1163 | |
<> | 144:ef7eb2e8f9f7 | 1164 | hspdif->State = HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1165 | |
<> | 144:ef7eb2e8f9f7 | 1166 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1167 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1168 | |
<> | 144:ef7eb2e8f9f7 | 1169 | HAL_SPDIFRX_CxCpltCallback(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1170 | } |
<> | 144:ef7eb2e8f9f7 | 1171 | } |
<> | 144:ef7eb2e8f9f7 | 1172 | |
<> | 144:ef7eb2e8f9f7 | 1173 | /** |
<> | 144:ef7eb2e8f9f7 | 1174 | * @brief This function handles SPDIFRX Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 1175 | * @param hspdif: SPDIFRX handle |
<> | 144:ef7eb2e8f9f7 | 1176 | * @param Flag: Flag checked |
<> | 144:ef7eb2e8f9f7 | 1177 | * @param Status: Value of the flag expected |
<> | 144:ef7eb2e8f9f7 | 1178 | * @param Timeout: Duration of the timeout |
<> | 144:ef7eb2e8f9f7 | 1179 | * @param tickstart: Tick start value |
<> | 144:ef7eb2e8f9f7 | 1180 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1181 | */ |
<> | 144:ef7eb2e8f9f7 | 1182 | static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) |
<> | 144:ef7eb2e8f9f7 | 1183 | { |
<> | 144:ef7eb2e8f9f7 | 1184 | /* Wait until flag is set */ |
<> | 144:ef7eb2e8f9f7 | 1185 | if(Status == RESET) |
<> | 144:ef7eb2e8f9f7 | 1186 | { |
<> | 144:ef7eb2e8f9f7 | 1187 | while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1188 | { |
<> | 144:ef7eb2e8f9f7 | 1189 | /* Check for the Timeout */ |
<> | 144:ef7eb2e8f9f7 | 1190 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1191 | { |
<> | 144:ef7eb2e8f9f7 | 1192 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1193 | { |
<> | 144:ef7eb2e8f9f7 | 1194 | /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ |
<> | 144:ef7eb2e8f9f7 | 1195 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 1196 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); |
<> | 144:ef7eb2e8f9f7 | 1197 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); |
<> | 144:ef7eb2e8f9f7 | 1198 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); |
<> | 144:ef7eb2e8f9f7 | 1199 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); |
<> | 144:ef7eb2e8f9f7 | 1200 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); |
<> | 144:ef7eb2e8f9f7 | 1201 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); |
<> | 144:ef7eb2e8f9f7 | 1202 | |
<> | 144:ef7eb2e8f9f7 | 1203 | hspdif->State= HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1204 | |
<> | 144:ef7eb2e8f9f7 | 1205 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1206 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1207 | |
<> | 144:ef7eb2e8f9f7 | 1208 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1209 | } |
<> | 144:ef7eb2e8f9f7 | 1210 | } |
<> | 144:ef7eb2e8f9f7 | 1211 | } |
<> | 144:ef7eb2e8f9f7 | 1212 | } |
<> | 144:ef7eb2e8f9f7 | 1213 | else |
<> | 144:ef7eb2e8f9f7 | 1214 | { |
<> | 144:ef7eb2e8f9f7 | 1215 | while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1216 | { |
<> | 144:ef7eb2e8f9f7 | 1217 | /* Check for the Timeout */ |
<> | 144:ef7eb2e8f9f7 | 1218 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1219 | { |
<> | 144:ef7eb2e8f9f7 | 1220 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1221 | { |
<> | 144:ef7eb2e8f9f7 | 1222 | /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ |
<> | 144:ef7eb2e8f9f7 | 1223 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); |
<> | 144:ef7eb2e8f9f7 | 1224 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); |
<> | 144:ef7eb2e8f9f7 | 1225 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); |
<> | 144:ef7eb2e8f9f7 | 1226 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); |
<> | 144:ef7eb2e8f9f7 | 1227 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); |
<> | 144:ef7eb2e8f9f7 | 1228 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); |
<> | 144:ef7eb2e8f9f7 | 1229 | __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); |
<> | 144:ef7eb2e8f9f7 | 1230 | |
<> | 144:ef7eb2e8f9f7 | 1231 | hspdif->State= HAL_SPDIFRX_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 1232 | |
<> | 144:ef7eb2e8f9f7 | 1233 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1234 | __HAL_UNLOCK(hspdif); |
<> | 144:ef7eb2e8f9f7 | 1235 | |
<> | 144:ef7eb2e8f9f7 | 1236 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1237 | } |
<> | 144:ef7eb2e8f9f7 | 1238 | } |
<> | 144:ef7eb2e8f9f7 | 1239 | } |
<> | 144:ef7eb2e8f9f7 | 1240 | } |
<> | 144:ef7eb2e8f9f7 | 1241 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1242 | } |
<> | 144:ef7eb2e8f9f7 | 1243 | |
<> | 144:ef7eb2e8f9f7 | 1244 | /** |
<> | 144:ef7eb2e8f9f7 | 1245 | * @} |
<> | 144:ef7eb2e8f9f7 | 1246 | */ |
<> | 144:ef7eb2e8f9f7 | 1247 | |
<> | 144:ef7eb2e8f9f7 | 1248 | #endif /* HAL_SPDIFRX_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1249 | /** |
<> | 144:ef7eb2e8f9f7 | 1250 | * @} |
<> | 144:ef7eb2e8f9f7 | 1251 | */ |
<> | 144:ef7eb2e8f9f7 | 1252 | |
<> | 144:ef7eb2e8f9f7 | 1253 | /** |
<> | 144:ef7eb2e8f9f7 | 1254 | * @} |
<> | 144:ef7eb2e8f9f7 | 1255 | */ |
<> | 144:ef7eb2e8f9f7 | 1256 | |
<> | 144:ef7eb2e8f9f7 | 1257 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |