Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_nand.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief NAND HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a generic firmware to drive NAND memories mounted
<> 144:ef7eb2e8f9f7 9 * as external device.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 18 with NAND devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
<> 144:ef7eb2e8f9f7 21 with control and timing parameters for both common and attribute spaces.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (+) Read NAND flash memory maker and device IDs using the function
<> 144:ef7eb2e8f9f7 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
<> 144:ef7eb2e8f9f7 25 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (+) Access NAND flash memory by read/write operations using the functions
<> 144:ef7eb2e8f9f7 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
<> 144:ef7eb2e8f9f7 29 to read/write page(s)/spare area(s). These functions use specific device
<> 144:ef7eb2e8f9f7 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
<> 144:ef7eb2e8f9f7 31 structure. The read/write address information is contained by the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 32 structure passed as parameter.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
<> 144:ef7eb2e8f9f7 37 The erase block address information is contained in the Nand_Address_Typedef
<> 144:ef7eb2e8f9f7 38 structure passed as parameter.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
<> 144:ef7eb2e8f9f7 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
<> 144:ef7eb2e8f9f7 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (+) You can monitor the NAND device HAL state by calling the function
<> 144:ef7eb2e8f9f7 47 HAL_NAND_GetState()
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 [..]
<> 144:ef7eb2e8f9f7 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
<> 144:ef7eb2e8f9f7 51 If a NAND flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 52 it should be implemented separately.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 @endverbatim
<> 144:ef7eb2e8f9f7 55 ******************************************************************************
<> 144:ef7eb2e8f9f7 56 * @attention
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 61 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 62 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 65 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 66 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 68 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 69 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 81 *
<> 144:ef7eb2e8f9f7 82 ******************************************************************************
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 #ifdef HAL_NAND_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @defgroup NAND NAND
<> 144:ef7eb2e8f9f7 96 * @brief NAND HAL module driver
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /* Private Constants ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 102 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 104 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 105 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup NAND_Exported_Functions NAND Exported Functions
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 112 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 @verbatim
<> 144:ef7eb2e8f9f7 115 ==============================================================================
<> 144:ef7eb2e8f9f7 116 ##### NAND Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 117 ==============================================================================
<> 144:ef7eb2e8f9f7 118 [..]
<> 144:ef7eb2e8f9f7 119 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 120 the NAND memory
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 @endverbatim
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @brief Perform NAND memory Initialization sequence
<> 144:ef7eb2e8f9f7 128 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 129 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 130 * @param ComSpace_Timing: pointer to Common space timing structure
<> 144:ef7eb2e8f9f7 131 * @param AttSpace_Timing: pointer to Attribute space timing structure
<> 144:ef7eb2e8f9f7 132 * @retval HAL status
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 /* Check the NAND handle state */
<> 144:ef7eb2e8f9f7 137 if(hnand == NULL)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 140 }
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if(hnand->State == HAL_NAND_STATE_RESET)
<> 144:ef7eb2e8f9f7 143 {
<> 144:ef7eb2e8f9f7 144 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 145 hnand->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 146 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 147 HAL_NAND_MspInit(hnand);
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Initialize NAND control Interface */
<> 144:ef7eb2e8f9f7 151 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Initialize NAND common space timing Interface */
<> 144:ef7eb2e8f9f7 154 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Initialize NAND attribute space timing Interface */
<> 144:ef7eb2e8f9f7 157 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Enable the NAND device */
<> 144:ef7eb2e8f9f7 160 __FMC_NAND_ENABLE(hnand->Instance);
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 163 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 return HAL_OK;
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Perform NAND memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 170 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 171 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 172 * @retval HAL status
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 177 HAL_NAND_MspDeInit(hnand);
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Configure the NAND registers with their reset values */
<> 144:ef7eb2e8f9f7 180 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Reset the NAND controller state */
<> 144:ef7eb2e8f9f7 183 hnand->State = HAL_NAND_STATE_RESET;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Release Lock */
<> 144:ef7eb2e8f9f7 186 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 return HAL_OK;
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief NAND MSP Init
<> 144:ef7eb2e8f9f7 193 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 194 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 195 * @retval None
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 200 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 203 the HAL_NAND_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief NAND MSP DeInit
<> 144:ef7eb2e8f9f7 209 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 210 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 211 * @retval None
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 216 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 219 the HAL_NAND_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @brief This function handles NAND device interrupt request.
<> 144:ef7eb2e8f9f7 226 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 227 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 228 * @retval HAL status
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Check NAND interrupt Rising edge flag */
<> 144:ef7eb2e8f9f7 233 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 236 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Clear NAND interrupt Rising edge pending bit */
<> 144:ef7eb2e8f9f7 239 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Check NAND interrupt Level flag */
<> 144:ef7eb2e8f9f7 243 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 246 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Clear NAND interrupt Level pending bit */
<> 144:ef7eb2e8f9f7 249 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Check NAND interrupt Falling edge flag */
<> 144:ef7eb2e8f9f7 253 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 256 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Clear NAND interrupt Falling edge pending bit */
<> 144:ef7eb2e8f9f7 259 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Check NAND interrupt FIFO empty flag */
<> 144:ef7eb2e8f9f7 263 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* NAND interrupt callback*/
<> 144:ef7eb2e8f9f7 266 HAL_NAND_ITCallback(hnand);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Clear NAND interrupt FIFO empty pending bit */
<> 144:ef7eb2e8f9f7 269 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief NAND interrupt feature callback
<> 144:ef7eb2e8f9f7 276 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 277 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 278 * @retval None
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 283 UNUSED(hnand);
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 286 the HAL_NAND_ITCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @}
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 295 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 296 *
<> 144:ef7eb2e8f9f7 297 @verbatim
<> 144:ef7eb2e8f9f7 298 ==============================================================================
<> 144:ef7eb2e8f9f7 299 ##### NAND Input and Output functions #####
<> 144:ef7eb2e8f9f7 300 ==============================================================================
<> 144:ef7eb2e8f9f7 301 [..]
<> 144:ef7eb2e8f9f7 302 This section provides functions allowing to use and control the NAND
<> 144:ef7eb2e8f9f7 303 memory
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 @endverbatim
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @brief Read the NAND memory electronic signature
<> 144:ef7eb2e8f9f7 311 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 312 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 313 * @param pNAND_ID: NAND ID structure
<> 144:ef7eb2e8f9f7 314 * @retval HAL status
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 __IO uint32_t data = 0;
<> 144:ef7eb2e8f9f7 319 __IO uint32_t data1 = 0;
<> 144:ef7eb2e8f9f7 320 uint32_t deviceAddress = 0;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Process Locked */
<> 144:ef7eb2e8f9f7 323 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 326 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Identify the device address */
<> 144:ef7eb2e8f9f7 332 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 335 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* Send Read ID command sequence */
<> 144:ef7eb2e8f9f7 338 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
<> 144:ef7eb2e8f9f7 339 __DSB();
<> 144:ef7eb2e8f9f7 340 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 341 __DSB();
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Read the electronic signature from NAND flash */
<> 144:ef7eb2e8f9f7 344 if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 data = *(__IO uint32_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Return the data read */
<> 144:ef7eb2e8f9f7 349 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
<> 144:ef7eb2e8f9f7 350 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
<> 144:ef7eb2e8f9f7 351 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
<> 144:ef7eb2e8f9f7 352 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 else
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 data = *(__IO uint32_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 357 data1 = *((__IO uint32_t *)deviceAddress + 4);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Return the data read */
<> 144:ef7eb2e8f9f7 360 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
<> 144:ef7eb2e8f9f7 361 pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
<> 144:ef7eb2e8f9f7 362 pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
<> 144:ef7eb2e8f9f7 363 pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 368 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Process unlocked */
<> 144:ef7eb2e8f9f7 371 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 return HAL_OK;
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @brief NAND memory reset
<> 144:ef7eb2e8f9f7 378 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 379 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 380 * @retval HAL status
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 uint32_t deviceAddress = 0;
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /* Process Locked */
<> 144:ef7eb2e8f9f7 387 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 390 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Identify the device address */
<> 144:ef7eb2e8f9f7 396 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 399 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Send NAND reset command */
<> 144:ef7eb2e8f9f7 402 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 406 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Process unlocked */
<> 144:ef7eb2e8f9f7 409 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 return HAL_OK;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @brief Read Page(s) from NAND memory block (8-bits addressing)
<> 144:ef7eb2e8f9f7 417 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 418 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 419 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 420 * @param pBuffer : pointer to destination read buffer
<> 144:ef7eb2e8f9f7 421 * @param NumPageToRead : number of pages to read from block
<> 144:ef7eb2e8f9f7 422 * @retval HAL status
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 427 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Process Locked */
<> 144:ef7eb2e8f9f7 430 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 433 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Identify the device address */
<> 144:ef7eb2e8f9f7 439 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 442 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 445 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Page(s) read loop */
<> 144:ef7eb2e8f9f7 448 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* update the buffer size */
<> 144:ef7eb2e8f9f7 451 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Send read page command sequence */
<> 144:ef7eb2e8f9f7 454 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 455 __DSB();
<> 144:ef7eb2e8f9f7 456 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 457 __DSB();
<> 144:ef7eb2e8f9f7 458 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 459 __DSB();
<> 144:ef7eb2e8f9f7 460 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 461 __DSB();
<> 144:ef7eb2e8f9f7 462 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 463 __DSB();
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 466 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 469 __DSB();
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 473 __DSB();
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 478 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483 else
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 486 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 489 }
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Increment read pages number */
<> 144:ef7eb2e8f9f7 493 numPagesRead++;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Decrement pages to read */
<> 144:ef7eb2e8f9f7 496 NumPageToRead--;
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 499 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 503 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Process unlocked */
<> 144:ef7eb2e8f9f7 506 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 return HAL_OK;
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief Read Page(s) from NAND memory block (16-bits addressing)
<> 144:ef7eb2e8f9f7 514 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 515 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 516 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 517 * @param pBuffer : pointer to destination read buffer
<> 144:ef7eb2e8f9f7 518 * @param NumPageToRead : number of pages to read from block
<> 144:ef7eb2e8f9f7 519 * @retval HAL status
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 524 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Process Locked */
<> 144:ef7eb2e8f9f7 527 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 530 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Identify the device address */
<> 144:ef7eb2e8f9f7 536 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 539 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 542 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Page(s) read loop */
<> 144:ef7eb2e8f9f7 545 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 /* update the buffer size */
<> 144:ef7eb2e8f9f7 548 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /* Send read page command sequence */
<> 144:ef7eb2e8f9f7 551 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 552 __DSB();
<> 144:ef7eb2e8f9f7 553 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 554 __DSB();
<> 144:ef7eb2e8f9f7 555 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 556 __DSB();
<> 144:ef7eb2e8f9f7 557 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 558 __DSB();
<> 144:ef7eb2e8f9f7 559 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 560 __DSB();
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 563 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 566 __DSB();
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 570 __DSB();
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 573 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Increment read pages number */
<> 144:ef7eb2e8f9f7 579 numPagesRead++;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Decrement pages to read */
<> 144:ef7eb2e8f9f7 582 NumPageToRead--;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 585 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 589 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Process unlocked */
<> 144:ef7eb2e8f9f7 592 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 return HAL_OK;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @brief Write Page(s) to NAND memory block (8-bits addressing)
<> 144:ef7eb2e8f9f7 599 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 600 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 601 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 602 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 603 * @param NumPageToWrite : number of pages to write to block
<> 144:ef7eb2e8f9f7 604 * @retval HAL status
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 609 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 610 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Process Locked */
<> 144:ef7eb2e8f9f7 613 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 616 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Identify the device address */
<> 144:ef7eb2e8f9f7 622 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 625 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 628 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Page(s) write loop */
<> 144:ef7eb2e8f9f7 631 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* update the buffer size */
<> 144:ef7eb2e8f9f7 634 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Send write page command sequence */
<> 144:ef7eb2e8f9f7 637 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 638 __DSB();
<> 144:ef7eb2e8f9f7 639 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 640 __DSB();
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 643 __DSB();
<> 144:ef7eb2e8f9f7 644 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 645 __DSB();
<> 144:ef7eb2e8f9f7 646 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 647 __DSB();
<> 144:ef7eb2e8f9f7 648 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 649 __DSB();
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 652 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 655 __DSB();
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 /* Write data to memory */
<> 144:ef7eb2e8f9f7 661 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 664 __DSB();
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 else
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 /* Write data to memory */
<> 144:ef7eb2e8f9f7 670 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 673 __DSB();
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 678 __DSB();
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 681 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 /* Get tick */
<> 144:ef7eb2e8f9f7 684 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Increment written pages number */
<> 144:ef7eb2e8f9f7 693 numPagesWritten++;
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Decrement pages to write */
<> 144:ef7eb2e8f9f7 696 NumPageToWrite--;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 699 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
<> 144:ef7eb2e8f9f7 700 }
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 703 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Process unlocked */
<> 144:ef7eb2e8f9f7 706 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 return HAL_OK;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /**
<> 144:ef7eb2e8f9f7 712 * @brief Write Page(s) to NAND memory block (16-bits addressing)
<> 144:ef7eb2e8f9f7 713 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 714 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 715 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 716 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 717 * @param NumPageToWrite : number of pages to write to block
<> 144:ef7eb2e8f9f7 718 * @retval HAL status
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 723 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 724 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Process Locked */
<> 144:ef7eb2e8f9f7 727 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 730 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Identify the device address */
<> 144:ef7eb2e8f9f7 736 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 739 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 742 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /* Page(s) write loop */
<> 144:ef7eb2e8f9f7 745 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /* update the buffer size */
<> 144:ef7eb2e8f9f7 748 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Send write page command sequence */
<> 144:ef7eb2e8f9f7 751 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
<> 144:ef7eb2e8f9f7 752 __DSB();
<> 144:ef7eb2e8f9f7 753 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 754 __DSB();
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 757 __DSB();
<> 144:ef7eb2e8f9f7 758 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 759 __DSB();
<> 144:ef7eb2e8f9f7 760 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 761 __DSB();
<> 144:ef7eb2e8f9f7 762 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 763 __DSB();
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 766 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 769 __DSB();
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Write data to memory */
<> 144:ef7eb2e8f9f7 773 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 776 __DSB();
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 780 __DSB();
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 783 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 /* Get tick */
<> 144:ef7eb2e8f9f7 786 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Increment written pages number */
<> 144:ef7eb2e8f9f7 795 numPagesWritten++;
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Decrement pages to write */
<> 144:ef7eb2e8f9f7 798 NumPageToWrite--;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 801 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 805 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Process unlocked */
<> 144:ef7eb2e8f9f7 808 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 return HAL_OK;
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @brief Read Spare area(s) from NAND memory (8-bits addressing)
<> 144:ef7eb2e8f9f7 815 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 816 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 817 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 818 * @param pBuffer: pointer to source buffer to write
<> 144:ef7eb2e8f9f7 819 * @param NumSpareAreaToRead: Number of spare area to read
<> 144:ef7eb2e8f9f7 820 * @retval HAL status
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 825 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Process Locked */
<> 144:ef7eb2e8f9f7 828 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 831 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 832 {
<> 144:ef7eb2e8f9f7 833 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /* Identify the device address */
<> 144:ef7eb2e8f9f7 837 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 840 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 843 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Spare area(s) read loop */
<> 144:ef7eb2e8f9f7 846 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 /* update the buffer size */
<> 144:ef7eb2e8f9f7 849 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Send read spare area command sequence */
<> 144:ef7eb2e8f9f7 852 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 853 __DSB();
<> 144:ef7eb2e8f9f7 854 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 855 __DSB();
<> 144:ef7eb2e8f9f7 856 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 857 __DSB();
<> 144:ef7eb2e8f9f7 858 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 859 __DSB();
<> 144:ef7eb2e8f9f7 860 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 861 __DSB();
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 864 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 867 __DSB();
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 871 __DSB();
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 874 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Increment read spare areas number */
<> 144:ef7eb2e8f9f7 880 numSpareAreaRead++;
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Decrement spare areas to read */
<> 144:ef7eb2e8f9f7 883 NumSpareAreaToRead--;
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 886 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 890 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Process unlocked */
<> 144:ef7eb2e8f9f7 893 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 return HAL_OK;
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /**
<> 144:ef7eb2e8f9f7 899 * @brief Read Spare area(s) from NAND memory (16-bits addressing)
<> 144:ef7eb2e8f9f7 900 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 901 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 902 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 903 * @param pBuffer: pointer to source buffer to write
<> 144:ef7eb2e8f9f7 904 * @param NumSpareAreaToRead: Number of spare area to read
<> 144:ef7eb2e8f9f7 905 * @retval HAL status
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 910 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Process Locked */
<> 144:ef7eb2e8f9f7 913 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 916 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Identify the device address */
<> 144:ef7eb2e8f9f7 922 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 925 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 928 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Spare area(s) read loop */
<> 144:ef7eb2e8f9f7 931 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 932 {
<> 144:ef7eb2e8f9f7 933 /* update the buffer size */
<> 144:ef7eb2e8f9f7 934 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Send read spare area command sequence */
<> 144:ef7eb2e8f9f7 937 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 938 __DSB();
<> 144:ef7eb2e8f9f7 939 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 940 __DSB();
<> 144:ef7eb2e8f9f7 941 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 942 __DSB();
<> 144:ef7eb2e8f9f7 943 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 944 __DSB();
<> 144:ef7eb2e8f9f7 945 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 946 __DSB();
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 949 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 950 {
<> 144:ef7eb2e8f9f7 951 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 952 __DSB();
<> 144:ef7eb2e8f9f7 953 }
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<> 144:ef7eb2e8f9f7 956 __DSB();
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Get Data into Buffer */
<> 144:ef7eb2e8f9f7 959 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /* Increment read spare areas number */
<> 144:ef7eb2e8f9f7 965 numSpareAreaRead++;
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Decrement spare areas to read */
<> 144:ef7eb2e8f9f7 968 NumSpareAreaToRead--;
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 971 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
<> 144:ef7eb2e8f9f7 972 }
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 975 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /* Process unlocked */
<> 144:ef7eb2e8f9f7 978 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 return HAL_OK;
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /**
<> 144:ef7eb2e8f9f7 984 * @brief Write Spare area(s) to NAND memory (8-bits addressing)
<> 144:ef7eb2e8f9f7 985 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 986 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 987 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 988 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 989 * @param NumSpareAreaTowrite : number of spare areas to write to block
<> 144:ef7eb2e8f9f7 990 * @retval HAL status
<> 144:ef7eb2e8f9f7 991 */
<> 144:ef7eb2e8f9f7 992 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 995 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 996 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /* Process Locked */
<> 144:ef7eb2e8f9f7 999 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1002 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Identify the device address */
<> 144:ef7eb2e8f9f7 1008 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /* Update the FMC_NAND controller state */
<> 144:ef7eb2e8f9f7 1011 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 1014 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Spare area(s) write loop */
<> 144:ef7eb2e8f9f7 1017 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 /* update the buffer size */
<> 144:ef7eb2e8f9f7 1020 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* Send write Spare area command sequence */
<> 144:ef7eb2e8f9f7 1023 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 1024 __DSB();
<> 144:ef7eb2e8f9f7 1025 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 1026 __DSB();
<> 144:ef7eb2e8f9f7 1027 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 1028 __DSB();
<> 144:ef7eb2e8f9f7 1029 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1030 __DSB();
<> 144:ef7eb2e8f9f7 1031 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1032 __DSB();
<> 144:ef7eb2e8f9f7 1033 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1034 __DSB();
<> 144:ef7eb2e8f9f7 1035 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 1036 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 1037 {
<> 144:ef7eb2e8f9f7 1038 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1039 __DSB();
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /* Write data to memory */
<> 144:ef7eb2e8f9f7 1043 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 1046 __DSB();
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 1050 __DSB();
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 1053 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 /* Get tick */
<> 144:ef7eb2e8f9f7 1056 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062 }
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 /* Increment written spare areas number */
<> 144:ef7eb2e8f9f7 1065 numSpareAreaWritten++;
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Decrement spare areas to write */
<> 144:ef7eb2e8f9f7 1068 NumSpareAreaTowrite--;
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 1071 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 1075 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1078 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 return HAL_OK;
<> 144:ef7eb2e8f9f7 1081 }
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /**
<> 144:ef7eb2e8f9f7 1084 * @brief Write Spare area(s) to NAND memory (16-bits addressing)
<> 144:ef7eb2e8f9f7 1085 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1086 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1087 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 1088 * @param pBuffer : pointer to source buffer to write
<> 144:ef7eb2e8f9f7 1089 * @param NumSpareAreaTowrite : number of spare areas to write to block
<> 144:ef7eb2e8f9f7 1090 * @retval HAL status
<> 144:ef7eb2e8f9f7 1091 */
<> 144:ef7eb2e8f9f7 1092 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 __IO uint32_t index = 0;
<> 144:ef7eb2e8f9f7 1095 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1096 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Process Locked */
<> 144:ef7eb2e8f9f7 1099 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1102 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Identify the device address */
<> 144:ef7eb2e8f9f7 1108 deviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Update the FMC_NAND controller state */
<> 144:ef7eb2e8f9f7 1111 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* NAND raw address calculation */
<> 144:ef7eb2e8f9f7 1114 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Spare area(s) write loop */
<> 144:ef7eb2e8f9f7 1117 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 /* update the buffer size */
<> 144:ef7eb2e8f9f7 1120 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /* Send write Spare area command sequence */
<> 144:ef7eb2e8f9f7 1123 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
<> 144:ef7eb2e8f9f7 1124 __DSB();
<> 144:ef7eb2e8f9f7 1125 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
<> 144:ef7eb2e8f9f7 1126 __DSB();
<> 144:ef7eb2e8f9f7 1127 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
<> 144:ef7eb2e8f9f7 1128 __DSB();
<> 144:ef7eb2e8f9f7 1129 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1130 __DSB();
<> 144:ef7eb2e8f9f7 1131 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1132 __DSB();
<> 144:ef7eb2e8f9f7 1133 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1134 __DSB();
<> 144:ef7eb2e8f9f7 1135 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 1136 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 1137 {
<> 144:ef7eb2e8f9f7 1138 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
<> 144:ef7eb2e8f9f7 1139 __DSB();
<> 144:ef7eb2e8f9f7 1140 }
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Write data to memory */
<> 144:ef7eb2e8f9f7 1143 for(; index < size; index++)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 *(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
<> 144:ef7eb2e8f9f7 1146 __DSB();
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<> 144:ef7eb2e8f9f7 1150 __DSB();
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Read status until NAND is ready */
<> 144:ef7eb2e8f9f7 1153 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<> 144:ef7eb2e8f9f7 1154 {
<> 144:ef7eb2e8f9f7 1155 /* Get tick */
<> 144:ef7eb2e8f9f7 1156 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162 }
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Increment written spare areas number */
<> 144:ef7eb2e8f9f7 1165 numSpareAreaWritten++;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Decrement spare areas to write */
<> 144:ef7eb2e8f9f7 1168 NumSpareAreaTowrite--;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Increment the NAND address */
<> 144:ef7eb2e8f9f7 1171 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 1175 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1178 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 return HAL_OK;
<> 144:ef7eb2e8f9f7 1181 }
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /**
<> 144:ef7eb2e8f9f7 1184 * @brief NAND memory Block erase
<> 144:ef7eb2e8f9f7 1185 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1186 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1187 * @param pAddress : pointer to NAND address structure
<> 144:ef7eb2e8f9f7 1188 * @retval HAL status
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 1191 {
<> 144:ef7eb2e8f9f7 1192 uint32_t DeviceAddress = 0;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /* Process Locked */
<> 144:ef7eb2e8f9f7 1195 __HAL_LOCK(hnand);
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1198 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1199 {
<> 144:ef7eb2e8f9f7 1200 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Identify the device address */
<> 144:ef7eb2e8f9f7 1204 DeviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 1207 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Send Erase block command sequence */
<> 144:ef7eb2e8f9f7 1210 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
<> 144:ef7eb2e8f9f7 1211 __DSB();
<> 144:ef7eb2e8f9f7 1212 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 1213 __DSB();
<> 144:ef7eb2e8f9f7 1214 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 1215 __DSB();
<> 144:ef7eb2e8f9f7 1216 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 1217 __DSB();
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* for 512 and 1 GB devices, 4th cycle is required */
<> 144:ef7eb2e8f9f7 1220 if(hnand->Info.BlockNbr >= 1024)
<> 144:ef7eb2e8f9f7 1221 {
<> 144:ef7eb2e8f9f7 1222 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<> 144:ef7eb2e8f9f7 1223 __DSB();
<> 144:ef7eb2e8f9f7 1224 }
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
<> 144:ef7eb2e8f9f7 1227 __DSB();
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 /* Update the NAND controller state */
<> 144:ef7eb2e8f9f7 1230 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1233 __HAL_UNLOCK(hnand);
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 return HAL_OK;
<> 144:ef7eb2e8f9f7 1236 }
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /**
<> 144:ef7eb2e8f9f7 1239 * @brief NAND memory read status
<> 144:ef7eb2e8f9f7 1240 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1241 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1242 * @retval NAND status
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 uint32_t data = 0;
<> 144:ef7eb2e8f9f7 1247 uint32_t DeviceAddress = 0;
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Identify the device address */
<> 144:ef7eb2e8f9f7 1250 DeviceAddress = NAND_DEVICE;
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Send Read status operation command */
<> 144:ef7eb2e8f9f7 1253 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Read status register data */
<> 144:ef7eb2e8f9f7 1256 data = *(__IO uint8_t *)DeviceAddress;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 /* Return the status */
<> 144:ef7eb2e8f9f7 1259 if((data & NAND_ERROR) == NAND_ERROR)
<> 144:ef7eb2e8f9f7 1260 {
<> 144:ef7eb2e8f9f7 1261 return NAND_ERROR;
<> 144:ef7eb2e8f9f7 1262 }
<> 144:ef7eb2e8f9f7 1263 else if((data & NAND_READY) == NAND_READY)
<> 144:ef7eb2e8f9f7 1264 {
<> 144:ef7eb2e8f9f7 1265 return NAND_READY;
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 return NAND_BUSY;
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270
<> 144:ef7eb2e8f9f7 1271 /**
<> 144:ef7eb2e8f9f7 1272 * @brief Increment the NAND memory address
<> 144:ef7eb2e8f9f7 1273 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1274 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1275 * @param pAddress: pointer to NAND address structure
<> 144:ef7eb2e8f9f7 1276 * @retval The new status of the increment address operation. It can be:
<> 144:ef7eb2e8f9f7 1277 * - NAND_VALID_ADDRESS: When the new address is valid address
<> 144:ef7eb2e8f9f7 1278 * - NAND_INVALID_ADDRESS: When the new address is invalid address
<> 144:ef7eb2e8f9f7 1279 */
<> 144:ef7eb2e8f9f7 1280 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
<> 144:ef7eb2e8f9f7 1281 {
<> 144:ef7eb2e8f9f7 1282 uint32_t status = NAND_VALID_ADDRESS;
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Increment page address */
<> 144:ef7eb2e8f9f7 1285 pAddress->Page++;
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Check NAND address is valid */
<> 144:ef7eb2e8f9f7 1288 if(pAddress->Page == hnand->Info.BlockSize)
<> 144:ef7eb2e8f9f7 1289 {
<> 144:ef7eb2e8f9f7 1290 pAddress->Page = 0;
<> 144:ef7eb2e8f9f7 1291 pAddress->Block++;
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 if(pAddress->Block == hnand->Info.ZoneSize)
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 pAddress->Block = 0;
<> 144:ef7eb2e8f9f7 1296 pAddress->Zone++;
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 status = NAND_INVALID_ADDRESS;
<> 144:ef7eb2e8f9f7 1301 }
<> 144:ef7eb2e8f9f7 1302 }
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 return (status);
<> 144:ef7eb2e8f9f7 1306 }
<> 144:ef7eb2e8f9f7 1307 /**
<> 144:ef7eb2e8f9f7 1308 * @}
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1312 * @brief management functions
<> 144:ef7eb2e8f9f7 1313 *
<> 144:ef7eb2e8f9f7 1314 @verbatim
<> 144:ef7eb2e8f9f7 1315 ==============================================================================
<> 144:ef7eb2e8f9f7 1316 ##### NAND Control functions #####
<> 144:ef7eb2e8f9f7 1317 ==============================================================================
<> 144:ef7eb2e8f9f7 1318 [..]
<> 144:ef7eb2e8f9f7 1319 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 1320 the NAND interface.
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 @endverbatim
<> 144:ef7eb2e8f9f7 1323 * @{
<> 144:ef7eb2e8f9f7 1324 */
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /**
<> 144:ef7eb2e8f9f7 1328 * @brief Enables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 1329 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1330 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1331 * @retval HAL status
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1336 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1337 {
<> 144:ef7eb2e8f9f7 1338 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1339 }
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1342 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 1345 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1348 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 return HAL_OK;
<> 144:ef7eb2e8f9f7 1351 }
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /**
<> 144:ef7eb2e8f9f7 1354 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 1355 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1356 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1357 * @retval HAL status
<> 144:ef7eb2e8f9f7 1358 */
<> 144:ef7eb2e8f9f7 1359 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1362 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1363 {
<> 144:ef7eb2e8f9f7 1364 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1365 }
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1368 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 1371 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1374 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 return HAL_OK;
<> 144:ef7eb2e8f9f7 1377 }
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /**
<> 144:ef7eb2e8f9f7 1380 * @brief Disables dynamically NAND ECC feature.
<> 144:ef7eb2e8f9f7 1381 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1382 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1383 * @param ECCval: pointer to ECC value
<> 144:ef7eb2e8f9f7 1384 * @param Timeout: maximum timeout to wait
<> 144:ef7eb2e8f9f7 1385 * @retval HAL status
<> 144:ef7eb2e8f9f7 1386 */
<> 144:ef7eb2e8f9f7 1387 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1388 {
<> 144:ef7eb2e8f9f7 1389 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* Check the NAND controller state */
<> 144:ef7eb2e8f9f7 1392 if(hnand->State == HAL_NAND_STATE_BUSY)
<> 144:ef7eb2e8f9f7 1393 {
<> 144:ef7eb2e8f9f7 1394 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1395 }
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1398 hnand->State = HAL_NAND_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Get NAND ECC value */
<> 144:ef7eb2e8f9f7 1401 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Update the NAND state */
<> 144:ef7eb2e8f9f7 1404 hnand->State = HAL_NAND_STATE_READY;
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 return status;
<> 144:ef7eb2e8f9f7 1407 }
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /**
<> 144:ef7eb2e8f9f7 1410 * @}
<> 144:ef7eb2e8f9f7 1411 */
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 1415 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1416 *
<> 144:ef7eb2e8f9f7 1417 @verbatim
<> 144:ef7eb2e8f9f7 1418 ==============================================================================
<> 144:ef7eb2e8f9f7 1419 ##### NAND State functions #####
<> 144:ef7eb2e8f9f7 1420 ==============================================================================
<> 144:ef7eb2e8f9f7 1421 [..]
<> 144:ef7eb2e8f9f7 1422 This subsection permits to get in run-time the status of the NAND controller
<> 144:ef7eb2e8f9f7 1423 and the data flow.
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 @endverbatim
<> 144:ef7eb2e8f9f7 1426 * @{
<> 144:ef7eb2e8f9f7 1427 */
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 /**
<> 144:ef7eb2e8f9f7 1430 * @brief return the NAND state
<> 144:ef7eb2e8f9f7 1431 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1432 * the configuration information for NAND module.
<> 144:ef7eb2e8f9f7 1433 * @retval HAL state
<> 144:ef7eb2e8f9f7 1434 */
<> 144:ef7eb2e8f9f7 1435 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 return hnand->State;
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /**
<> 144:ef7eb2e8f9f7 1441 * @}
<> 144:ef7eb2e8f9f7 1442 */
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /**
<> 144:ef7eb2e8f9f7 1445 * @}
<> 144:ef7eb2e8f9f7 1446 */
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 #endif /* HAL_NAND_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /**
<> 144:ef7eb2e8f9f7 1451 * @}
<> 144:ef7eb2e8f9f7 1452 */
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 /**
<> 144:ef7eb2e8f9f7 1455 * @}
<> 144:ef7eb2e8f9f7 1456 */
<> 144:ef7eb2e8f9f7 1457
<> 144:ef7eb2e8f9f7 1458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/