Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_irda.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of IRDA HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_IRDA_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup IRDA
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup IRDA_Exported_Types IRDA Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief IRDA Init Structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
<> 144:ef7eb2e8f9f7 67 The baud rate register is computed using the following formula:
<> 144:ef7eb2e8f9f7 68 Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref IRDAEx_Word_Length */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref IRDA_Parity
<> 144:ef7eb2e8f9f7 75 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 76 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 77 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 78 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<> 144:ef7eb2e8f9f7 81 This parameter can be a value of @ref IRDA_Transfer_Mode */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
<> 144:ef7eb2e8f9f7 84 to achieve low-power frequency.
<> 144:ef7eb2e8f9f7 85 @note Prescaler value 0 is forbidden */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint16_t PowerMode; /*!< Specifies the IRDA power mode.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref IRDA_Low_Power */
<> 144:ef7eb2e8f9f7 89 }IRDA_InitTypeDef;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @brief HAL IRDA State structures definition
<> 144:ef7eb2e8f9f7 93 * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
<> 144:ef7eb2e8f9f7 94 * - gState contains IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 95 * and also information related to Tx operations.
<> 144:ef7eb2e8f9f7 96 * gState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 97 * b7-b6 Error information
<> 144:ef7eb2e8f9f7 98 * 00 : No Error
<> 144:ef7eb2e8f9f7 99 * 01 : (Not Used)
<> 144:ef7eb2e8f9f7 100 * 10 : Timeout
<> 144:ef7eb2e8f9f7 101 * 11 : Error
<> 144:ef7eb2e8f9f7 102 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 103 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 104 * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
<> 144:ef7eb2e8f9f7 105 * b4-b3 (not used)
<> 144:ef7eb2e8f9f7 106 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 107 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 108 * 0 : Ready
<> 144:ef7eb2e8f9f7 109 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 110 * b1 (not used)
<> 144:ef7eb2e8f9f7 111 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 112 * b0 Tx state
<> 144:ef7eb2e8f9f7 113 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 114 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 115 * - RxState contains information related to Rx operations.
<> 144:ef7eb2e8f9f7 116 * RxState value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 117 * b7-b6 (not used)
<> 144:ef7eb2e8f9f7 118 * xx : Should be set to 00
<> 144:ef7eb2e8f9f7 119 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 120 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 121 * 1 : Init done (IP not initialized)
<> 144:ef7eb2e8f9f7 122 * b4-b2 (not used)
<> 144:ef7eb2e8f9f7 123 * xxx : Should be set to 000
<> 144:ef7eb2e8f9f7 124 * b1 Rx state
<> 144:ef7eb2e8f9f7 125 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 126 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 127 * b0 (not used)
<> 144:ef7eb2e8f9f7 128 * x : Should be set to 0.
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 typedef enum
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
<> 144:ef7eb2e8f9f7 133 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 134 HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<> 144:ef7eb2e8f9f7 135 Value is allowed for gState and RxState */
<> 144:ef7eb2e8f9f7 136 HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
<> 144:ef7eb2e8f9f7 137 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 138 HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<> 144:ef7eb2e8f9f7 139 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 140 HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<> 144:ef7eb2e8f9f7 141 Value is allowed for RxState only */
<> 144:ef7eb2e8f9f7 142 HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<> 144:ef7eb2e8f9f7 143 Not to be used for neither gState nor RxState.
<> 144:ef7eb2e8f9f7 144 Value is result of combination (Or) between gState and RxState values */
<> 144:ef7eb2e8f9f7 145 HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<> 144:ef7eb2e8f9f7 146 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 147 HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
<> 144:ef7eb2e8f9f7 148 Value is allowed for gState only */
<> 144:ef7eb2e8f9f7 149 }HAL_IRDA_StateTypeDef;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief IRDA clock sources definition
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 typedef enum
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
<> 144:ef7eb2e8f9f7 157 IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
<> 144:ef7eb2e8f9f7 158 IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
<> 144:ef7eb2e8f9f7 159 IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
<> 144:ef7eb2e8f9f7 160 IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */
<> 144:ef7eb2e8f9f7 161 }IRDA_ClockSourceTypeDef;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief IRDA handle Structure definition
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 typedef struct
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 USART_TypeDef *Instance; /* IRDA registers base address */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 IRDA_InitTypeDef Init; /* IRDA communication parameters */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint8_t *pTxBuffPtr; /* Pointer to IRDA Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 uint16_t TxXferSize; /* IRDA Tx Transfer size */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 uint16_t RxXferSize; /* IRDA Rx Transfer size */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 uint16_t Mask; /* IRDA RX RDR register mask */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 DMA_HandleTypeDef *hdmatx; /* IRDA Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 DMA_HandleTypeDef *hdmarx; /* IRDA Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 HAL_LockTypeDef Lock; /* Locking object */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 __IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
<> 144:ef7eb2e8f9f7 193 and also related to Tx operations.
<> 144:ef7eb2e8f9f7 194 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 __IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
<> 144:ef7eb2e8f9f7 197 This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 __IO uint32_t ErrorCode; /* IRDA Error code */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 }IRDA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /**
<> 144:ef7eb2e8f9f7 204 * @}
<> 144:ef7eb2e8f9f7 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief IRDA Configuration enumeration values definition
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 212 /** @defgroup IRDA_Exported_Constants IRDA Exported constants
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 /** @defgroup IRDA_Error_Code IRDA Error Code
<> 144:ef7eb2e8f9f7 216 * @brief IRDA Error Code
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 144:ef7eb2e8f9f7 221 #define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
<> 144:ef7eb2e8f9f7 222 #define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
<> 144:ef7eb2e8f9f7 223 #define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
<> 144:ef7eb2e8f9f7 224 #define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 225 #define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup IRDA_Parity IRDA Parity
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define IRDA_PARITY_NONE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 234 #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
<> 144:ef7eb2e8f9f7 235 #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
<> 144:ef7eb2e8f9f7 245 #define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
<> 144:ef7eb2e8f9f7 246 #define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup IRDA_Low_Power IRDA Low Power
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 255 #define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** @defgroup IRDA_State IRDA State
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 #define IRDA_STATE_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 264 #define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @}
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /** @defgroup IRDA_Mode IRDA Mode
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define IRDA_MODE_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 273 #define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /** @defgroup IRDA_One_Bit IRDA One Bit
<> 144:ef7eb2e8f9f7 279 * @{
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 #define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 282 #define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /** @defgroup IRDA_DMA_Tx IRDA DMA Tx
<> 144:ef7eb2e8f9f7 288 * @{
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 #define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 291 #define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @}
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /** @defgroup IRDA_DMA_Rx IRDA DMA Rx
<> 144:ef7eb2e8f9f7 297 * @{
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 300 #define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @defgroup IRDA_Flags IRDA Flags
<> 144:ef7eb2e8f9f7 306 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 307 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define IRDA_FLAG_REACK ((uint32_t)0x00400000U)
<> 144:ef7eb2e8f9f7 311 #define IRDA_FLAG_TEACK ((uint32_t)0x00200000U)
<> 144:ef7eb2e8f9f7 312 #define IRDA_FLAG_BUSY ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 313 #define IRDA_FLAG_ABRF ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 314 #define IRDA_FLAG_ABRE ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 315 #define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 316 #define IRDA_FLAG_TC ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 317 #define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 318 #define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 319 #define IRDA_FLAG_NE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 320 #define IRDA_FLAG_FE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 321 #define IRDA_FLAG_PE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition
<> 144:ef7eb2e8f9f7 327 * Elements values convention: 0000ZZZZ0XXYYYYYb
<> 144:ef7eb2e8f9f7 328 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 329 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 330 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 331 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 332 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 333 * - ZZZZ : Flag position in the ISR register(4bits)
<> 144:ef7eb2e8f9f7 334 * @{
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 #define IRDA_IT_PE ((uint16_t)0x0028U)
<> 144:ef7eb2e8f9f7 337 #define IRDA_IT_TXE ((uint16_t)0x0727U)
<> 144:ef7eb2e8f9f7 338 #define IRDA_IT_TC ((uint16_t)0x0626U)
<> 144:ef7eb2e8f9f7 339 #define IRDA_IT_RXNE ((uint16_t)0x0525U)
<> 144:ef7eb2e8f9f7 340 #define IRDA_IT_IDLE ((uint16_t)0x0424U)
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /** Elements values convention: 000000000XXYYYYYb
<> 144:ef7eb2e8f9f7 345 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 346 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 347 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 348 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 349 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351 #define IRDA_IT_ERR ((uint16_t)0x0060U)
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /** Elements values convention: 0000ZZZZ00000000b
<> 144:ef7eb2e8f9f7 354 * - ZZZZ : Flag position in the ISR register(4bits)
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define IRDA_IT_ORE ((uint16_t)0x0300U)
<> 144:ef7eb2e8f9f7 357 #define IRDA_IT_NE ((uint16_t)0x0200U)
<> 144:ef7eb2e8f9f7 358 #define IRDA_IT_FE ((uint16_t)0x0100U)
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup IRDA_IT_CLEAR_Flags IRDA IT CLEAR Flags
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366 #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
<> 144:ef7eb2e8f9f7 367 #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
<> 144:ef7eb2e8f9f7 368 #define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
<> 144:ef7eb2e8f9f7 369 #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
<> 144:ef7eb2e8f9f7 370 #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 371 /**
<> 144:ef7eb2e8f9f7 372 * @}
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup IRDA_Request_Parameters IRDA Request Parameters
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
<> 144:ef7eb2e8f9f7 381 #define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 382 #define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @}
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 393 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
<> 144:ef7eb2e8f9f7 394 * @{
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @brief Reset IRDA handle state
<> 144:ef7eb2e8f9f7 398 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 399 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 400 * @retval None
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /** @brief Check whether the specified IRDA flag is set or not.
<> 144:ef7eb2e8f9f7 405 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 406 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 407 * UART peripheral
<> 144:ef7eb2e8f9f7 408 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 409 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 410 * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
<> 144:ef7eb2e8f9f7 411 * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
<> 144:ef7eb2e8f9f7 412 * @arg IRDA_FLAG_BUSY: Busy flag
<> 144:ef7eb2e8f9f7 413 * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
<> 144:ef7eb2e8f9f7 414 * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
<> 144:ef7eb2e8f9f7 415 * @arg IRDA_FLAG_TXE: Transmit data register empty flag
<> 144:ef7eb2e8f9f7 416 * @arg IRDA_FLAG_TC: Transmission Complete flag
<> 144:ef7eb2e8f9f7 417 * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
<> 144:ef7eb2e8f9f7 418 * @arg IRDA_FLAG_IDLE: Idle Line detection flag
<> 144:ef7eb2e8f9f7 419 * @arg IRDA_FLAG_ORE: OverRun Error flag
<> 144:ef7eb2e8f9f7 420 * @arg IRDA_FLAG_NE: Noise Error flag
<> 144:ef7eb2e8f9f7 421 * @arg IRDA_FLAG_FE: Framing Error flag
<> 144:ef7eb2e8f9f7 422 * @arg IRDA_FLAG_PE: Parity Error flag
<> 144:ef7eb2e8f9f7 423 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /** @brief Enable the specified IRDA interrupt.
<> 144:ef7eb2e8f9f7 428 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 429 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 430 * UART peripheral
<> 144:ef7eb2e8f9f7 431 * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
<> 144:ef7eb2e8f9f7 432 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 433 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 434 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 435 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 436 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 437 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 438 * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 439 * @retval None
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 442 ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 443 ((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /** @brief Disable the specified IRDA interrupt.
<> 144:ef7eb2e8f9f7 446 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 447 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 448 * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
<> 144:ef7eb2e8f9f7 449 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 450 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 451 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 452 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 453 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 454 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 455 * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 456 * @retval None
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 459 ((((uint8_t)(__INTERRUPT__)) >> 5) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))): \
<> 144:ef7eb2e8f9f7 460 ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @brief Check whether the specified IRDA interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 463 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 464 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 465 * @param __IT__: specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 466 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 467 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 468 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 469 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 470 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 471 * @arg IRDA_IT_ORE: OverRun Error interrupt
<> 144:ef7eb2e8f9f7 472 * @arg IRDA_IT_NE: Noise Error interrupt
<> 144:ef7eb2e8f9f7 473 * @arg IRDA_IT_FE: Framing Error interrupt
<> 144:ef7eb2e8f9f7 474 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 475 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /** @brief Check whether the specified IRDA interrupt source is enabled.
<> 144:ef7eb2e8f9f7 480 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 481 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 482 * @param __IT__: specifies the IRDA interrupt source to check.
<> 144:ef7eb2e8f9f7 483 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 484 * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
<> 144:ef7eb2e8f9f7 485 * @arg IRDA_IT_TC: Transmission complete interrupt
<> 144:ef7eb2e8f9f7 486 * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
<> 144:ef7eb2e8f9f7 487 * @arg IRDA_IT_IDLE: Idle line detection interrupt
<> 144:ef7eb2e8f9f7 488 * @arg IRDA_IT_ORE: OverRun Error interrupt
<> 144:ef7eb2e8f9f7 489 * @arg IRDA_IT_NE: Noise Error interrupt
<> 144:ef7eb2e8f9f7 490 * @arg IRDA_IT_FE: Framing Error interrupt
<> 144:ef7eb2e8f9f7 491 * @arg IRDA_IT_PE: Parity Error interrupt
<> 144:ef7eb2e8f9f7 492 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
<> 144:ef7eb2e8f9f7 495 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
<> 144:ef7eb2e8f9f7 498 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 499 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 500 * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
<> 144:ef7eb2e8f9f7 501 * to clear the corresponding interrupt
<> 144:ef7eb2e8f9f7 502 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 503 * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
<> 144:ef7eb2e8f9f7 504 * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
<> 144:ef7eb2e8f9f7 505 * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
<> 144:ef7eb2e8f9f7 506 * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
<> 144:ef7eb2e8f9f7 507 * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
<> 144:ef7eb2e8f9f7 508 * @retval None
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510 #define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /** @brief Set a specific IRDA request flag.
<> 144:ef7eb2e8f9f7 513 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 514 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 515 * @param __REQ__: specifies the request flag to set
<> 144:ef7eb2e8f9f7 516 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 517 * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
<> 144:ef7eb2e8f9f7 518 * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
<> 144:ef7eb2e8f9f7 519 * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
<> 144:ef7eb2e8f9f7 520 *
<> 144:ef7eb2e8f9f7 521 * @retval None
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /** @brief Enable UART/USART associated to IRDA Handle
<> 144:ef7eb2e8f9f7 526 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 527 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 528 * @retval None
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /** @brief Disable UART/USART associated to IRDA Handle
<> 144:ef7eb2e8f9f7 533 * @param __HANDLE__: specifies the IRDA Handle.
<> 144:ef7eb2e8f9f7 534 * The Handle Instance which can be USART1 or USART2.
<> 144:ef7eb2e8f9f7 535 * @retval None
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @}
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Include IRDA HAL Extension module */
<> 144:ef7eb2e8f9f7 544 #include "stm32f7xx_hal_irda_ex.h"
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 547 /** @addtogroup IRDA_Exported_Functions IrDA Exported Functions
<> 144:ef7eb2e8f9f7 548 * @{
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 552 * @{
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 556 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 557 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 558 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 559 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * @}
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 565 * @{
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 573 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 574 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 575 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 576 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 577 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 578 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 579 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 580 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 581 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 582 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 583 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @}
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 589 * @{
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 /* Peripheral State methods **************************************************/
<> 144:ef7eb2e8f9f7 592 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 593 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
<> 144:ef7eb2e8f9f7 594 /**
<> 144:ef7eb2e8f9f7 595 * @}
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @}
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 603 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 604 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 605 /** @defgroup IRDA_Private_Constants IRDA Private Constants
<> 144:ef7eb2e8f9f7 606 * @{
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask
<> 144:ef7eb2e8f9f7 610 * @{
<> 144:ef7eb2e8f9f7 611 */
<> 144:ef7eb2e8f9f7 612 #define IRDA_IT_MASK ((uint16_t)0x001FU)
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @}
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @}
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 621 /** @defgroup IRDA_Private_Macros IRDA Private Macros
<> 144:ef7eb2e8f9f7 622 * @{
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /** @brief Ensure that IRDA Baud rate is less or equal to maximum value
<> 144:ef7eb2e8f9f7 626 * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
<> 144:ef7eb2e8f9f7 627 * @retval True or False
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /** @brief Ensure that IRDA prescaler value is strictly larger than 0
<> 144:ef7eb2e8f9f7 632 * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
<> 144:ef7eb2e8f9f7 633 * @retval True or False
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 638 ((__PARITY__) == IRDA_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 639 ((__PARITY__) == IRDA_PARITY_ODD))
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
<> 144:ef7eb2e8f9f7 644 ((__MODE__) == IRDA_POWERMODE_NORMAL))
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 647 ((__STATE__) == IRDA_STATE_ENABLE))
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 #define IS_IRDA_MODE(__STATE__) (((__STATE__) == IRDA_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 650 ((__STATE__) == IRDA_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
<> 144:ef7eb2e8f9f7 653 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
<> 144:ef7eb2e8f9f7 656 ((__DMATX__) == IRDA_DMA_TX_ENABLE))
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
<> 144:ef7eb2e8f9f7 659 ((__DMARX__) == IRDA_DMA_RX_ENABLE))
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \
<> 144:ef7eb2e8f9f7 662 ((PARAM) == IRDA_SENDBREAK_REQUEST) || \
<> 144:ef7eb2e8f9f7 663 ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \
<> 144:ef7eb2e8f9f7 664 ((PARAM) == IRDA_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 665 ((PARAM) == IRDA_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @}
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 671 /** @defgroup IRDA_Private_Functions IRDA Private Functions
<> 144:ef7eb2e8f9f7 672 * @{
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /**
<> 144:ef7eb2e8f9f7 676 * @}
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @}
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @}
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689 #endif
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 #endif /* __STM32F7xx_HAL_IRDA_H */
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/