Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_i2c.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2C HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The I2C HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (#) Declare a I2C_HandleTypeDef handle structure, for example:
<> 144:ef7eb2e8f9f7 22 I2C_HandleTypeDef hi2c;
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
<> 144:ef7eb2e8f9f7 25 (##) Enable the I2Cx interface clock
<> 144:ef7eb2e8f9f7 26 (##) I2C pins configuration
<> 144:ef7eb2e8f9f7 27 (+++) Enable the clock for the I2C GPIOs
<> 144:ef7eb2e8f9f7 28 (+++) Configure I2C pins as alternate function open-drain
<> 144:ef7eb2e8f9f7 29 (##) NVIC configuration if you need to use interrupt process
<> 144:ef7eb2e8f9f7 30 (+++) Configure the I2Cx interrupt priority
<> 144:ef7eb2e8f9f7 31 (+++) Enable the NVIC I2C IRQ Channel
<> 144:ef7eb2e8f9f7 32 (##) DMA Configuration if you need to use DMA process
<> 144:ef7eb2e8f9f7 33 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
<> 144:ef7eb2e8f9f7 34 (+++) Enable the DMAx interface clock using
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA handle parameters
<> 144:ef7eb2e8f9f7 36 (+++) Configure the DMA Tx or Rx stream
<> 144:ef7eb2e8f9f7 37 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<> 144:ef7eb2e8f9f7 38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<> 144:ef7eb2e8f9f7 39 the DMA Tx or Rx stream
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
<> 144:ef7eb2e8f9f7 42 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<> 144:ef7eb2e8f9f7 45 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 52 =================================
<> 144:ef7eb2e8f9f7 53 [..]
<> 144:ef7eb2e8f9f7 54 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<> 144:ef7eb2e8f9f7 55 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<> 144:ef7eb2e8f9f7 56 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 *** Polling mode IO MEM operation ***
<> 144:ef7eb2e8f9f7 60 =====================================
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<> 144:ef7eb2e8f9f7 63 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 67 ===================================
<> 144:ef7eb2e8f9f7 68 [..]
<> 144:ef7eb2e8f9f7 69 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 70 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 72 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 73 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 74 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 75 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 76 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 77 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 78 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 79 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 81 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 83 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 84 (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 86 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<> 144:ef7eb2e8f9f7 87 This action will inform Master to generate a Stop condition to discard the communication.
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 *** Interrupt mode IO sequential operation ***
<> 144:ef7eb2e8f9f7 91 ===================================
<> 144:ef7eb2e8f9f7 92 [..]
<> 144:ef7eb2e8f9f7 93 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
<> 144:ef7eb2e8f9f7 94 when a direction change during transfer
<> 144:ef7eb2e8f9f7 95 [..]
<> 144:ef7eb2e8f9f7 96 (+) A specific option field manage the different steps of a sequential transfer
<> 144:ef7eb2e8f9f7 97 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
<> 144:ef7eb2e8f9f7 98 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
<> 144:ef7eb2e8f9f7 99 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
<> 144:ef7eb2e8f9f7 100 and data to transfer without a final stop condition
<> 144:ef7eb2e8f9f7 101 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
<> 144:ef7eb2e8f9f7 102 and with new data to transfer if the direction change or manage only the new data to transfer
<> 144:ef7eb2e8f9f7 103 if no direction change and without a final stop condition in both cases
<> 144:ef7eb2e8f9f7 104 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
<> 144:ef7eb2e8f9f7 105 and with new data to transfer if the direction change or manage only the new data to transfer
<> 144:ef7eb2e8f9f7 106 if no direction change and with a final stop condition in both cases
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 (+) Differents sequential I2C interfaces are listed below:
<> 144:ef7eb2e8f9f7 109 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
<> 144:ef7eb2e8f9f7 110 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 111 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 112 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
<> 144:ef7eb2e8f9f7 113 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 114 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 115 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 116 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 117 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<> 144:ef7eb2e8f9f7 118 (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
<> 144:ef7eb2e8f9f7 119 (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
<> 144:ef7eb2e8f9f7 120 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
<> 144:ef7eb2e8f9f7 121 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<> 144:ef7eb2e8f9f7 122 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
<> 144:ef7eb2e8f9f7 123 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 124 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
<> 144:ef7eb2e8f9f7 125 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
<> 144:ef7eb2e8f9f7 126 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 127 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 128 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
<> 144:ef7eb2e8f9f7 129 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 130 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 131 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 132 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 133 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 134 (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 135 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<> 144:ef7eb2e8f9f7 136 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<> 144:ef7eb2e8f9f7 137 This action will inform Master to generate a Stop condition to discard the communication.
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 *** Interrupt mode IO MEM operation ***
<> 144:ef7eb2e8f9f7 140 =======================================
<> 144:ef7eb2e8f9f7 141 [..]
<> 144:ef7eb2e8f9f7 142 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
<> 144:ef7eb2e8f9f7 143 HAL_I2C_Mem_Write_IT()
<> 144:ef7eb2e8f9f7 144 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 145 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
<> 144:ef7eb2e8f9f7 146 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
<> 144:ef7eb2e8f9f7 147 HAL_I2C_Mem_Read_IT()
<> 144:ef7eb2e8f9f7 148 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 149 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
<> 144:ef7eb2e8f9f7 150 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 151 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 154 ==============================
<> 144:ef7eb2e8f9f7 155 [..]
<> 144:ef7eb2e8f9f7 156 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
<> 144:ef7eb2e8f9f7 157 HAL_I2C_Master_Transmit_DMA()
<> 144:ef7eb2e8f9f7 158 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 159 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 160 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
<> 144:ef7eb2e8f9f7 161 HAL_I2C_Master_Receive_DMA()
<> 144:ef7eb2e8f9f7 162 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 163 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 164 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
<> 144:ef7eb2e8f9f7 165 HAL_I2C_Slave_Transmit_DMA()
<> 144:ef7eb2e8f9f7 166 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 167 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 168 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
<> 144:ef7eb2e8f9f7 169 HAL_I2C_Slave_Receive_DMA()
<> 144:ef7eb2e8f9f7 170 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 171 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 173 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 174 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<> 144:ef7eb2e8f9f7 175 (+) End of abort process, HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 176 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() or HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 177 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
<> 144:ef7eb2e8f9f7 178 This action will inform Master to generate a Stop condition to discard the communication.
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 *** DMA mode IO MEM operation ***
<> 144:ef7eb2e8f9f7 181 =================================
<> 144:ef7eb2e8f9f7 182 [..]
<> 144:ef7eb2e8f9f7 183 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
<> 144:ef7eb2e8f9f7 184 HAL_I2C_Mem_Write_DMA()
<> 144:ef7eb2e8f9f7 185 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 186 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
<> 144:ef7eb2e8f9f7 187 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
<> 144:ef7eb2e8f9f7 188 HAL_I2C_Mem_Read_DMA()
<> 144:ef7eb2e8f9f7 189 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
<> 144:ef7eb2e8f9f7 190 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
<> 144:ef7eb2e8f9f7 191 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 192 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 *** I2C HAL driver macros list ***
<> 144:ef7eb2e8f9f7 196 ==================================
<> 144:ef7eb2e8f9f7 197 [..]
<> 144:ef7eb2e8f9f7 198 Below the list of most used macros in I2C HAL driver.
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<> 144:ef7eb2e8f9f7 201 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<> 144:ef7eb2e8f9f7 202 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
<> 144:ef7eb2e8f9f7 203 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
<> 144:ef7eb2e8f9f7 204 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
<> 144:ef7eb2e8f9f7 205 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<> 144:ef7eb2e8f9f7 206 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 [..]
<> 144:ef7eb2e8f9f7 209 (@) You can refer to the I2C HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 @endverbatim
<> 144:ef7eb2e8f9f7 212 ******************************************************************************
<> 144:ef7eb2e8f9f7 213 * @attention
<> 144:ef7eb2e8f9f7 214 *
<> 144:ef7eb2e8f9f7 215 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 216 *
<> 144:ef7eb2e8f9f7 217 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 218 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 219 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 220 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 221 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 222 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 223 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 224 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 225 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 226 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 227 *
<> 144:ef7eb2e8f9f7 228 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 229 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 230 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 231 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 232 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 233 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 234 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 235 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 236 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 237 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 238 *
<> 144:ef7eb2e8f9f7 239 ******************************************************************************
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 243 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** @defgroup I2C I2C
<> 144:ef7eb2e8f9f7 250 * @brief I2C HAL module driver
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #ifdef HAL_I2C_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 257 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup I2C_Private_Define I2C Private Define
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
<> 144:ef7eb2e8f9f7 263 #define I2C_TIMEOUT_ADDR ((uint32_t)10000U) /*!< 10 s */
<> 144:ef7eb2e8f9f7 264 #define I2C_TIMEOUT_BUSY ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 265 #define I2C_TIMEOUT_DIR ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 266 #define I2C_TIMEOUT_RXNE ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 267 #define I2C_TIMEOUT_STOPF ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 268 #define I2C_TIMEOUT_TC ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 269 #define I2C_TIMEOUT_TCR ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 270 #define I2C_TIMEOUT_TXIS ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 271 #define I2C_TIMEOUT_FLAG ((uint32_t)25U) /*!< 25 ms */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 #define MAX_NBYTE_SIZE 255U
<> 144:ef7eb2e8f9f7 274 #define SlaveAddr_SHIFT 7U
<> 144:ef7eb2e8f9f7 275 #define SlaveAddr_MSK 0x06U
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Private define for @ref PreviousState usage */
<> 144:ef7eb2e8f9f7 278 #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
<> 144:ef7eb2e8f9f7 279 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
<> 144:ef7eb2e8f9f7 280 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 281 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 282 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 283 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 284 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 285 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Private define to centralize the enable/disable of Interrupts */
<> 144:ef7eb2e8f9f7 289 #define I2C_XFER_TX_IT ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 290 #define I2C_XFER_RX_IT ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 291 #define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 #define I2C_XFER_ERROR_IT ((uint32_t)0x00000011)
<> 144:ef7eb2e8f9f7 294 #define I2C_XFER_CPLT_IT ((uint32_t)0x00000012)
<> 144:ef7eb2e8f9f7 295 #define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012)
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 301 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
<> 144:ef7eb2e8f9f7 302 ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
<> 144:ef7eb2e8f9f7 303 ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 306 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 /* Private functions to handle DMA transfer */
<> 144:ef7eb2e8f9f7 312 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 313 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 314 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 315 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 316 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 317 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Private functions to handle IT transfer */
<> 144:ef7eb2e8f9f7 320 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<> 144:ef7eb2e8f9f7 321 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 322 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 323 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<> 144:ef7eb2e8f9f7 324 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<> 144:ef7eb2e8f9f7 325 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
<> 144:ef7eb2e8f9f7 326 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Private functions to handle IT transfer */
<> 144:ef7eb2e8f9f7 329 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 330 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Private functions for I2C transfer IRQ handler */
<> 144:ef7eb2e8f9f7 333 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<> 144:ef7eb2e8f9f7 334 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<> 144:ef7eb2e8f9f7 335 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<> 144:ef7eb2e8f9f7 336 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Private functions to handle flags during polling transfer */
<> 144:ef7eb2e8f9f7 339 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 340 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 341 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 342 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 343 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Private functions to centralize the enable/disable of Interrupts */
<> 144:ef7eb2e8f9f7 346 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 347 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Private functions to flush TXDR register */
<> 144:ef7eb2e8f9f7 350 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Private functions to handle start, restart or stop a transfer */
<> 144:ef7eb2e8f9f7 353 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @}
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /** @defgroup I2C_Exported_Functions I2C Exported Functions
<> 144:ef7eb2e8f9f7 361 * @{
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 365 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 366 *
<> 144:ef7eb2e8f9f7 367 @verbatim
<> 144:ef7eb2e8f9f7 368 ===============================================================================
<> 144:ef7eb2e8f9f7 369 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 370 ===============================================================================
<> 144:ef7eb2e8f9f7 371 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 372 deinitialize the I2Cx peripheral:
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 (+) User must Implement HAL_I2C_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 375 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 (+) Call the function HAL_I2C_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 378 the selected configuration:
<> 144:ef7eb2e8f9f7 379 (++) Clock Timing
<> 144:ef7eb2e8f9f7 380 (++) Own Address 1
<> 144:ef7eb2e8f9f7 381 (++) Addressing mode (Master, Slave)
<> 144:ef7eb2e8f9f7 382 (++) Dual Addressing mode
<> 144:ef7eb2e8f9f7 383 (++) Own Address 2
<> 144:ef7eb2e8f9f7 384 (++) Own Address 2 Mask
<> 144:ef7eb2e8f9f7 385 (++) General call mode
<> 144:ef7eb2e8f9f7 386 (++) Nostretch mode
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 389 of the selected I2Cx peripheral.
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 @endverbatim
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief Initializes the I2C according to the specified parameters
<> 144:ef7eb2e8f9f7 397 * in the I2C_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 398 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 399 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 400 * @retval HAL status
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 403 {
<> 144:ef7eb2e8f9f7 404 /* Check the I2C handle allocation */
<> 144:ef7eb2e8f9f7 405 if(hi2c == NULL)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Check the parameters */
<> 144:ef7eb2e8f9f7 411 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<> 144:ef7eb2e8f9f7 412 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<> 144:ef7eb2e8f9f7 413 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<> 144:ef7eb2e8f9f7 414 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<> 144:ef7eb2e8f9f7 415 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<> 144:ef7eb2e8f9f7 416 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
<> 144:ef7eb2e8f9f7 417 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<> 144:ef7eb2e8f9f7 418 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 if(hi2c->State == HAL_I2C_STATE_RESET)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 423 hi2c->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 426 HAL_I2C_MspInit(hi2c);
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 hi2c->State = HAL_I2C_STATE_BUSY;
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Disable the selected I2C peripheral */
<> 144:ef7eb2e8f9f7 432 __HAL_I2C_DISABLE(hi2c);
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
<> 144:ef7eb2e8f9f7 435 /* Configure I2Cx: Frequency range */
<> 144:ef7eb2e8f9f7 436 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 439 /* Configure I2Cx: Own Address1 and ack own address1 mode */
<> 144:ef7eb2e8f9f7 440 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
<> 144:ef7eb2e8f9f7 441 if(hi2c->Init.OwnAddress1 != 0)
<> 144:ef7eb2e8f9f7 442 {
<> 144:ef7eb2e8f9f7 443 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 else /* I2C_ADDRESSINGMODE_10BIT */
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 454 /* Configure I2Cx: Addressing Master mode */
<> 144:ef7eb2e8f9f7 455 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
<> 144:ef7eb2e8f9f7 460 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
<> 144:ef7eb2e8f9f7 463 /* Configure I2Cx: Dual mode and Own Address2 */
<> 144:ef7eb2e8f9f7 464 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
<> 144:ef7eb2e8f9f7 467 /* Configure I2Cx: Generalcall and NoStretch mode */
<> 144:ef7eb2e8f9f7 468 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Enable the selected I2C peripheral */
<> 144:ef7eb2e8f9f7 471 __HAL_I2C_ENABLE(hi2c);
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 474 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 475 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 476 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 return HAL_OK;
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /**
<> 144:ef7eb2e8f9f7 482 * @brief DeInitialize the I2C peripheral.
<> 144:ef7eb2e8f9f7 483 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 484 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 485 * @retval HAL status
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 /* Check the I2C handle allocation */
<> 144:ef7eb2e8f9f7 490 if(hi2c == NULL)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Check the parameters */
<> 144:ef7eb2e8f9f7 496 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 hi2c->State = HAL_I2C_STATE_BUSY;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Disable the I2C Peripheral Clock */
<> 144:ef7eb2e8f9f7 501 __HAL_I2C_DISABLE(hi2c);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 504 HAL_I2C_MspDeInit(hi2c);
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 507 hi2c->State = HAL_I2C_STATE_RESET;
<> 144:ef7eb2e8f9f7 508 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 509 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Release Lock */
<> 144:ef7eb2e8f9f7 512 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 return HAL_OK;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief Initialize the I2C MSP.
<> 144:ef7eb2e8f9f7 519 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 520 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 521 * @retval None
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 526 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 529 the HAL_I2C_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /**
<> 144:ef7eb2e8f9f7 534 * @brief DeInitialize the I2C MSP.
<> 144:ef7eb2e8f9f7 535 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 536 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 537 * @retval None
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 542 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 545 the HAL_I2C_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @}
<> 144:ef7eb2e8f9f7 551 */
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 554 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 555 *
<> 144:ef7eb2e8f9f7 556 @verbatim
<> 144:ef7eb2e8f9f7 557 ===============================================================================
<> 144:ef7eb2e8f9f7 558 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 559 ===============================================================================
<> 144:ef7eb2e8f9f7 560 [..]
<> 144:ef7eb2e8f9f7 561 This subsection provides a set of functions allowing to manage the I2C data
<> 144:ef7eb2e8f9f7 562 transfers.
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 565 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 566 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 567 after finishing transfer.
<> 144:ef7eb2e8f9f7 568 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 569 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 570 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 571 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 572 using DMA mode.
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 575 (++) HAL_I2C_Master_Transmit()
<> 144:ef7eb2e8f9f7 576 (++) HAL_I2C_Master_Receive()
<> 144:ef7eb2e8f9f7 577 (++) HAL_I2C_Slave_Transmit()
<> 144:ef7eb2e8f9f7 578 (++) HAL_I2C_Slave_Receive()
<> 144:ef7eb2e8f9f7 579 (++) HAL_I2C_Mem_Write()
<> 144:ef7eb2e8f9f7 580 (++) HAL_I2C_Mem_Read()
<> 144:ef7eb2e8f9f7 581 (++) HAL_I2C_IsDeviceReady()
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 584 (++) HAL_I2C_Master_Transmit_IT()
<> 144:ef7eb2e8f9f7 585 (++) HAL_I2C_Master_Receive_IT()
<> 144:ef7eb2e8f9f7 586 (++) HAL_I2C_Slave_Transmit_IT()
<> 144:ef7eb2e8f9f7 587 (++) HAL_I2C_Slave_Receive_IT()
<> 144:ef7eb2e8f9f7 588 (++) HAL_I2C_Mem_Write_IT()
<> 144:ef7eb2e8f9f7 589 (++) HAL_I2C_Mem_Read_IT()
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 592 (++) HAL_I2C_Master_Transmit_DMA()
<> 144:ef7eb2e8f9f7 593 (++) HAL_I2C_Master_Receive_DMA()
<> 144:ef7eb2e8f9f7 594 (++) HAL_I2C_Slave_Transmit_DMA()
<> 144:ef7eb2e8f9f7 595 (++) HAL_I2C_Slave_Receive_DMA()
<> 144:ef7eb2e8f9f7 596 (++) HAL_I2C_Mem_Write_DMA()
<> 144:ef7eb2e8f9f7 597 (++) HAL_I2C_Mem_Read_DMA()
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 600 (++) HAL_I2C_MemTxCpltCallback()
<> 144:ef7eb2e8f9f7 601 (++) HAL_I2C_MemRxCpltCallback()
<> 144:ef7eb2e8f9f7 602 (++) HAL_I2C_MasterTxCpltCallback()
<> 144:ef7eb2e8f9f7 603 (++) HAL_I2C_MasterRxCpltCallback()
<> 144:ef7eb2e8f9f7 604 (++) HAL_I2C_SlaveTxCpltCallback()
<> 144:ef7eb2e8f9f7 605 (++) HAL_I2C_SlaveRxCpltCallback()
<> 144:ef7eb2e8f9f7 606 (++) HAL_I2C_ErrorCallback()
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 @endverbatim
<> 144:ef7eb2e8f9f7 609 * @{
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @brief Transmits in master mode an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 614 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 615 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 616 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 617 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 618 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 619 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 620 * @retval HAL status
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 /* Process Locked */
<> 144:ef7eb2e8f9f7 629 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 632 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 640 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 641 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 644 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 645 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 646 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 649 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 650 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 653 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 else
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 658 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 659 }
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 while(hi2c->XferSize > 0)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 664 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670 else
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 676 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<> 144:ef7eb2e8f9f7 677 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 678 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 /* Wait until TCR flag is set */
<> 144:ef7eb2e8f9f7 683 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 691 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 else
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 696 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 702 /* Wait until STOPF flag is set */
<> 144:ef7eb2e8f9f7 703 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 706 {
<> 144:ef7eb2e8f9f7 707 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 else
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 }
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 716 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 719 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 722 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 725 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 return HAL_OK;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 else
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /**
<> 144:ef7eb2e8f9f7 736 * @brief Receives in master mode an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 737 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 738 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 739 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 740 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 741 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 742 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 743 * @retval HAL status
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 /* Process Locked */
<> 144:ef7eb2e8f9f7 752 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 755 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 763 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 764 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 767 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 768 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 769 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 772 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 773 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 776 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 else
<> 144:ef7eb2e8f9f7 779 {
<> 144:ef7eb2e8f9f7 780 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 781 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 while(hi2c->XferSize > 0)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 787 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793 else
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 796 }
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 800 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 801 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 802 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* Wait until TCR flag is set */
<> 144:ef7eb2e8f9f7 807 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 815 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 else
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 820 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 821 }
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 826 /* Wait until STOPF flag is set */
<> 144:ef7eb2e8f9f7 827 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 828 {
<> 144:ef7eb2e8f9f7 829 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833 else
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 840 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 843 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 846 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 849 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 return HAL_OK;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 else
<> 144:ef7eb2e8f9f7 854 {
<> 144:ef7eb2e8f9f7 855 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857 }
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /**
<> 144:ef7eb2e8f9f7 860 * @brief Transmits in slave mode an amount of data in blocking mode.
<> 144:ef7eb2e8f9f7 861 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 862 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 863 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 864 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 865 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 866 * @retval HAL status
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878 /* Process Locked */
<> 144:ef7eb2e8f9f7 879 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 882 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 885 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 886 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 889 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 890 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 891 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 894 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /* Wait until ADDR flag is set */
<> 144:ef7eb2e8f9f7 897 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 900 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 901 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 905 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* If 10bit addressing mode is selected */
<> 144:ef7eb2e8f9f7 908 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* Wait until ADDR flag is set */
<> 144:ef7eb2e8f9f7 911 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 914 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 915 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 916 }
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 919 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Wait until DIR flag is set Transmitter mode */
<> 144:ef7eb2e8f9f7 923 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 926 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 927 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 while(hi2c->XferCount > 0)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 933 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 936 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 939 {
<> 144:ef7eb2e8f9f7 940 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 else
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 949 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<> 144:ef7eb2e8f9f7 950 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Wait until STOP flag is set */
<> 144:ef7eb2e8f9f7 954 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 957 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 /* Normal use case for Transmitter mode */
<> 144:ef7eb2e8f9f7 962 /* A NACK is generated to confirm the end of transfer */
<> 144:ef7eb2e8f9f7 963 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965 else
<> 144:ef7eb2e8f9f7 966 {
<> 144:ef7eb2e8f9f7 967 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /* Clear STOP flag */
<> 144:ef7eb2e8f9f7 972 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /* Wait until BUSY flag is reset */
<> 144:ef7eb2e8f9f7 975 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 978 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 979 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 980 }
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 983 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 986 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 989 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 return HAL_OK;
<> 144:ef7eb2e8f9f7 992 }
<> 144:ef7eb2e8f9f7 993 else
<> 144:ef7eb2e8f9f7 994 {
<> 144:ef7eb2e8f9f7 995 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /**
<> 144:ef7eb2e8f9f7 1000 * @brief Receive in slave mode an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 1001 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1002 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1003 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1004 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1005 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1006 * @retval HAL status
<> 144:ef7eb2e8f9f7 1007 */
<> 144:ef7eb2e8f9f7 1008 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1009 {
<> 144:ef7eb2e8f9f7 1010 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 /* Process Locked */
<> 144:ef7eb2e8f9f7 1019 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 1022 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1025 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 1026 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1029 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1030 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1031 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1034 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* Wait until ADDR flag is set */
<> 144:ef7eb2e8f9f7 1037 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1040 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1041 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1042 }
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 1045 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Wait until DIR flag is reset Receiver mode */
<> 144:ef7eb2e8f9f7 1048 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1051 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1052 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 while(hi2c->XferCount > 0)
<> 144:ef7eb2e8f9f7 1056 {
<> 144:ef7eb2e8f9f7 1057 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 1058 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1061 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Store Last receive data if any */
<> 144:ef7eb2e8f9f7 1064 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<> 144:ef7eb2e8f9f7 1065 {
<> 144:ef7eb2e8f9f7 1066 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1067 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1068 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075 else
<> 144:ef7eb2e8f9f7 1076 {
<> 144:ef7eb2e8f9f7 1077 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1082 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1083 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Wait until STOP flag is set */
<> 144:ef7eb2e8f9f7 1087 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1090 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1095 }
<> 144:ef7eb2e8f9f7 1096 else
<> 144:ef7eb2e8f9f7 1097 {
<> 144:ef7eb2e8f9f7 1098 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /* Clear STOP flag */
<> 144:ef7eb2e8f9f7 1103 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1104
<> 144:ef7eb2e8f9f7 1105 /* Wait until BUSY flag is reset */
<> 144:ef7eb2e8f9f7 1106 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1109 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1110 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1114 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 1117 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1120 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 return HAL_OK;
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124 else
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /**
<> 144:ef7eb2e8f9f7 1131 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1132 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1133 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1134 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1135 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1136 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1137 * @retval HAL status
<> 144:ef7eb2e8f9f7 1138 */
<> 144:ef7eb2e8f9f7 1139 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /* Process Locked */
<> 144:ef7eb2e8f9f7 1151 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1154 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 1155 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1158 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1159 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1160 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1161 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1166 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168 else
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1171 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 1175 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<> 144:ef7eb2e8f9f7 1176 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1179 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1182 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1183 process unlock */
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1186 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 1187 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 1188 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 return HAL_OK;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 else
<> 144:ef7eb2e8f9f7 1193 {
<> 144:ef7eb2e8f9f7 1194 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1195 }
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /**
<> 144:ef7eb2e8f9f7 1199 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1200 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1201 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1202 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1203 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1204 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1205 * @retval HAL status
<> 144:ef7eb2e8f9f7 1206 */
<> 144:ef7eb2e8f9f7 1207 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1208 {
<> 144:ef7eb2e8f9f7 1209 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1212 {
<> 144:ef7eb2e8f9f7 1213 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1216 }
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Process Locked */
<> 144:ef7eb2e8f9f7 1219 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1222 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 1223 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1226 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1227 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1228 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1229 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1234 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 1235 }
<> 144:ef7eb2e8f9f7 1236 else
<> 144:ef7eb2e8f9f7 1237 {
<> 144:ef7eb2e8f9f7 1238 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1239 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 1240 }
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 1243 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<> 144:ef7eb2e8f9f7 1244 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1247 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1248
<> 144:ef7eb2e8f9f7 1249 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1250 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1251 process unlock */
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1254 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 1255 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 1256 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 return HAL_OK;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 else
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1268 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1269 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1270 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1271 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1272 * @retval HAL status
<> 144:ef7eb2e8f9f7 1273 */
<> 144:ef7eb2e8f9f7 1274 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1277 {
<> 144:ef7eb2e8f9f7 1278 /* Process Locked */
<> 144:ef7eb2e8f9f7 1279 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1282 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 1283 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1286 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1289 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1290 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1291 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1292 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1293 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1296 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1299 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1300 process unlock */
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 1303 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 1304 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 1305 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 return HAL_OK;
<> 144:ef7eb2e8f9f7 1308 }
<> 144:ef7eb2e8f9f7 1309 else
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313 }
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /**
<> 144:ef7eb2e8f9f7 1316 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1317 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1318 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1319 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1320 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1321 * @retval HAL status
<> 144:ef7eb2e8f9f7 1322 */
<> 144:ef7eb2e8f9f7 1323 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1324 {
<> 144:ef7eb2e8f9f7 1325 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1326 {
<> 144:ef7eb2e8f9f7 1327 /* Process Locked */
<> 144:ef7eb2e8f9f7 1328 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1331 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 1332 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1335 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1338 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1339 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1340 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1341 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1342 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1345 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1348 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1349 process unlock */
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 1352 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 1353 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 1354 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 return HAL_OK;
<> 144:ef7eb2e8f9f7 1357 }
<> 144:ef7eb2e8f9f7 1358 else
<> 144:ef7eb2e8f9f7 1359 {
<> 144:ef7eb2e8f9f7 1360 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1361 }
<> 144:ef7eb2e8f9f7 1362 }
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 /**
<> 144:ef7eb2e8f9f7 1365 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1366 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1367 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1368 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1369 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1370 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1371 * @retval HAL status
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1378 {
<> 144:ef7eb2e8f9f7 1379 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 1380 {
<> 144:ef7eb2e8f9f7 1381 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1382 }
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Process Locked */
<> 144:ef7eb2e8f9f7 1385 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1388 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 1389 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1390
<> 144:ef7eb2e8f9f7 1391 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1392 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1393 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1394 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1395 hi2c->XferISR = I2C_Master_ISR_DMA;
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1400 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 1401 }
<> 144:ef7eb2e8f9f7 1402 else
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1405 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1409 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1412 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 1415 hi2c->hdmatx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1416 hi2c->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1419 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 1422 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 1423 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 /* Update XferCount value */
<> 144:ef7eb2e8f9f7 1426 hi2c->XferCount -= hi2c->XferSize;
<> 144:ef7eb2e8f9f7 1427
<> 144:ef7eb2e8f9f7 1428 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1429 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1432 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1433 process unlock */
<> 144:ef7eb2e8f9f7 1434 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 1435 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 1438 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 return HAL_OK;
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442 else
<> 144:ef7eb2e8f9f7 1443 {
<> 144:ef7eb2e8f9f7 1444 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1445 }
<> 144:ef7eb2e8f9f7 1446 }
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /**
<> 144:ef7eb2e8f9f7 1449 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1450 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1451 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1452 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1453 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1454 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1455 * @retval HAL status
<> 144:ef7eb2e8f9f7 1456 */
<> 144:ef7eb2e8f9f7 1457 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1458 {
<> 144:ef7eb2e8f9f7 1459 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1462 {
<> 144:ef7eb2e8f9f7 1463 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 1464 {
<> 144:ef7eb2e8f9f7 1465 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1466 }
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 /* Process Locked */
<> 144:ef7eb2e8f9f7 1469 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1472 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 1473 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1476 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1477 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1478 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1479 hi2c->XferISR = I2C_Master_ISR_DMA;
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1482 {
<> 144:ef7eb2e8f9f7 1483 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1484 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 1485 }
<> 144:ef7eb2e8f9f7 1486 else
<> 144:ef7eb2e8f9f7 1487 {
<> 144:ef7eb2e8f9f7 1488 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1489 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 1490 }
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 if(hi2c->XferSize > 0)
<> 144:ef7eb2e8f9f7 1493 {
<> 144:ef7eb2e8f9f7 1494 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1495 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1498 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 1501 hi2c->hdmarx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1502 hi2c->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1505 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 1508 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 1509 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 1510
<> 144:ef7eb2e8f9f7 1511 /* Update XferCount value */
<> 144:ef7eb2e8f9f7 1512 hi2c->XferCount -= hi2c->XferSize;
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1515 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1518 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1519 process unlock */
<> 144:ef7eb2e8f9f7 1520 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 1521 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 1524 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526 else
<> 144:ef7eb2e8f9f7 1527 {
<> 144:ef7eb2e8f9f7 1528 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 1529 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1532 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1533 }
<> 144:ef7eb2e8f9f7 1534 return HAL_OK;
<> 144:ef7eb2e8f9f7 1535 }
<> 144:ef7eb2e8f9f7 1536 else
<> 144:ef7eb2e8f9f7 1537 {
<> 144:ef7eb2e8f9f7 1538 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1539 }
<> 144:ef7eb2e8f9f7 1540 }
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /**
<> 144:ef7eb2e8f9f7 1543 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1544 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1545 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1546 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1547 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1548 * @retval HAL status
<> 144:ef7eb2e8f9f7 1549 */
<> 144:ef7eb2e8f9f7 1550 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1553 {
<> 144:ef7eb2e8f9f7 1554 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1555 {
<> 144:ef7eb2e8f9f7 1556 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1557 }
<> 144:ef7eb2e8f9f7 1558 /* Process Locked */
<> 144:ef7eb2e8f9f7 1559 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1562 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 1563 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1566 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1567 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1568 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1569 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1570 hi2c->XferISR = I2C_Slave_ISR_DMA;
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1573 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1576 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 1579 hi2c->hdmatx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1580 hi2c->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1583 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1586 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1589 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1592 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1593 process unlock */
<> 144:ef7eb2e8f9f7 1594 /* Enable ERR, STOP, NACK, ADDR interrupts */
<> 144:ef7eb2e8f9f7 1595 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 1598 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 return HAL_OK;
<> 144:ef7eb2e8f9f7 1601 }
<> 144:ef7eb2e8f9f7 1602 else
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1605 }
<> 144:ef7eb2e8f9f7 1606 }
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 /**
<> 144:ef7eb2e8f9f7 1609 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 1610 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1611 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1612 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1613 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1614 * @retval HAL status
<> 144:ef7eb2e8f9f7 1615 */
<> 144:ef7eb2e8f9f7 1616 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1617 {
<> 144:ef7eb2e8f9f7 1618 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1619 {
<> 144:ef7eb2e8f9f7 1620 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1621 {
<> 144:ef7eb2e8f9f7 1622 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1623 }
<> 144:ef7eb2e8f9f7 1624 /* Process Locked */
<> 144:ef7eb2e8f9f7 1625 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1628 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 1629 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1632 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1633 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1634 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1635 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 1636 hi2c->XferISR = I2C_Slave_ISR_DMA;
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1639 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
<> 144:ef7eb2e8f9f7 1640
<> 144:ef7eb2e8f9f7 1641 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1642 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 1645 hi2c->hdmarx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1646 hi2c->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1649 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 1652 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1655 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 1658 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 1659 process unlock */
<> 144:ef7eb2e8f9f7 1660 /* Enable ERR, STOP, NACK, ADDR interrupts */
<> 144:ef7eb2e8f9f7 1661 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 1664 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 return HAL_OK;
<> 144:ef7eb2e8f9f7 1667 }
<> 144:ef7eb2e8f9f7 1668 else
<> 144:ef7eb2e8f9f7 1669 {
<> 144:ef7eb2e8f9f7 1670 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1671 }
<> 144:ef7eb2e8f9f7 1672 }
<> 144:ef7eb2e8f9f7 1673 /**
<> 144:ef7eb2e8f9f7 1674 * @brief Write an amount of data in blocking mode to a specific memory address
<> 144:ef7eb2e8f9f7 1675 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1676 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1677 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1678 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 1679 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 1680 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1681 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1682 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1683 * @retval HAL status
<> 144:ef7eb2e8f9f7 1684 */
<> 144:ef7eb2e8f9f7 1685 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1686 {
<> 144:ef7eb2e8f9f7 1687 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1690 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 1691
<> 144:ef7eb2e8f9f7 1692 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1693 {
<> 144:ef7eb2e8f9f7 1694 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1695 {
<> 144:ef7eb2e8f9f7 1696 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1697 }
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 /* Process Locked */
<> 144:ef7eb2e8f9f7 1700 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 1703 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1706 {
<> 144:ef7eb2e8f9f7 1707 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1708 }
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 1711 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 1712 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1715 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1716 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1717 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 1720 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1721 {
<> 144:ef7eb2e8f9f7 1722 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1723 {
<> 144:ef7eb2e8f9f7 1724 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1725 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1726 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1727 }
<> 144:ef7eb2e8f9f7 1728 else
<> 144:ef7eb2e8f9f7 1729 {
<> 144:ef7eb2e8f9f7 1730 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1731 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1732 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1733 }
<> 144:ef7eb2e8f9f7 1734 }
<> 144:ef7eb2e8f9f7 1735
<> 144:ef7eb2e8f9f7 1736 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
<> 144:ef7eb2e8f9f7 1737 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1738 {
<> 144:ef7eb2e8f9f7 1739 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1740 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1741 }
<> 144:ef7eb2e8f9f7 1742 else
<> 144:ef7eb2e8f9f7 1743 {
<> 144:ef7eb2e8f9f7 1744 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1745 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1746 }
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 do
<> 144:ef7eb2e8f9f7 1749 {
<> 144:ef7eb2e8f9f7 1750 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 1751 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1752 {
<> 144:ef7eb2e8f9f7 1753 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1754 {
<> 144:ef7eb2e8f9f7 1755 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1756 }
<> 144:ef7eb2e8f9f7 1757 else
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1760 }
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762
<> 144:ef7eb2e8f9f7 1763 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 1764 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<> 144:ef7eb2e8f9f7 1765 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 1766 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 1767
<> 144:ef7eb2e8f9f7 1768 if((hi2c->XferSize == 0) && (hi2c->XferCount!=0))
<> 144:ef7eb2e8f9f7 1769 {
<> 144:ef7eb2e8f9f7 1770 /* Wait until TCR flag is set */
<> 144:ef7eb2e8f9f7 1771 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1772 {
<> 144:ef7eb2e8f9f7 1773 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1774 }
<> 144:ef7eb2e8f9f7 1775
<> 144:ef7eb2e8f9f7 1776 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1777 {
<> 144:ef7eb2e8f9f7 1778 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1779 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1780 }
<> 144:ef7eb2e8f9f7 1781 else
<> 144:ef7eb2e8f9f7 1782 {
<> 144:ef7eb2e8f9f7 1783 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1784 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1785 }
<> 144:ef7eb2e8f9f7 1786 }
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 }while(hi2c->XferCount > 0);
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 1791 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 1792 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1793 {
<> 144:ef7eb2e8f9f7 1794 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1795 {
<> 144:ef7eb2e8f9f7 1796 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1797 }
<> 144:ef7eb2e8f9f7 1798 else
<> 144:ef7eb2e8f9f7 1799 {
<> 144:ef7eb2e8f9f7 1800 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1801 }
<> 144:ef7eb2e8f9f7 1802 }
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1805 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1808 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 1809
<> 144:ef7eb2e8f9f7 1810 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 1811 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1814 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 return HAL_OK;
<> 144:ef7eb2e8f9f7 1817 }
<> 144:ef7eb2e8f9f7 1818 else
<> 144:ef7eb2e8f9f7 1819 {
<> 144:ef7eb2e8f9f7 1820 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1821 }
<> 144:ef7eb2e8f9f7 1822 }
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /**
<> 144:ef7eb2e8f9f7 1825 * @brief Read an amount of data in blocking mode from a specific memory address
<> 144:ef7eb2e8f9f7 1826 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1827 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1828 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1829 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 1830 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 1831 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1832 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1833 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1834 * @retval HAL status
<> 144:ef7eb2e8f9f7 1835 */
<> 144:ef7eb2e8f9f7 1836 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1837 {
<> 144:ef7eb2e8f9f7 1838 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1839
<> 144:ef7eb2e8f9f7 1840 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1841 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1844 {
<> 144:ef7eb2e8f9f7 1845 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1846 {
<> 144:ef7eb2e8f9f7 1847 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1848 }
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 /* Process Locked */
<> 144:ef7eb2e8f9f7 1851 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 1854 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1857 {
<> 144:ef7eb2e8f9f7 1858 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 1862 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 1863 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 1866 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 1867 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 1868 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 1871 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1872 {
<> 144:ef7eb2e8f9f7 1873 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1874 {
<> 144:ef7eb2e8f9f7 1875 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1876 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1877 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1878 }
<> 144:ef7eb2e8f9f7 1879 else
<> 144:ef7eb2e8f9f7 1880 {
<> 144:ef7eb2e8f9f7 1881 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1882 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1883 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1884 }
<> 144:ef7eb2e8f9f7 1885 }
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 1888 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 1889 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1890 {
<> 144:ef7eb2e8f9f7 1891 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1892 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 1893 }
<> 144:ef7eb2e8f9f7 1894 else
<> 144:ef7eb2e8f9f7 1895 {
<> 144:ef7eb2e8f9f7 1896 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1897 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 1898 }
<> 144:ef7eb2e8f9f7 1899
<> 144:ef7eb2e8f9f7 1900 do
<> 144:ef7eb2e8f9f7 1901 {
<> 144:ef7eb2e8f9f7 1902 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 1903 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1904 {
<> 144:ef7eb2e8f9f7 1905 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1906 }
<> 144:ef7eb2e8f9f7 1907
<> 144:ef7eb2e8f9f7 1908 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 1909 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 1910 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 1911 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 1912
<> 144:ef7eb2e8f9f7 1913 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
<> 144:ef7eb2e8f9f7 1914 {
<> 144:ef7eb2e8f9f7 1915 /* Wait until TCR flag is set */
<> 144:ef7eb2e8f9f7 1916 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1917 {
<> 144:ef7eb2e8f9f7 1918 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1919 }
<> 144:ef7eb2e8f9f7 1920
<> 144:ef7eb2e8f9f7 1921 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 1924 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1925 }
<> 144:ef7eb2e8f9f7 1926 else
<> 144:ef7eb2e8f9f7 1927 {
<> 144:ef7eb2e8f9f7 1928 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 1929 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 1930 }
<> 144:ef7eb2e8f9f7 1931 }
<> 144:ef7eb2e8f9f7 1932 }while(hi2c->XferCount > 0);
<> 144:ef7eb2e8f9f7 1933
<> 144:ef7eb2e8f9f7 1934 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 1935 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 1936 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 1937 {
<> 144:ef7eb2e8f9f7 1938 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 1939 {
<> 144:ef7eb2e8f9f7 1940 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1941 }
<> 144:ef7eb2e8f9f7 1942 else
<> 144:ef7eb2e8f9f7 1943 {
<> 144:ef7eb2e8f9f7 1944 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1945 }
<> 144:ef7eb2e8f9f7 1946 }
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 1949 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 1950
<> 144:ef7eb2e8f9f7 1951 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 1952 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 1955 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 1956
<> 144:ef7eb2e8f9f7 1957 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1958 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 return HAL_OK;
<> 144:ef7eb2e8f9f7 1961 }
<> 144:ef7eb2e8f9f7 1962 else
<> 144:ef7eb2e8f9f7 1963 {
<> 144:ef7eb2e8f9f7 1964 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1965 }
<> 144:ef7eb2e8f9f7 1966 }
<> 144:ef7eb2e8f9f7 1967 /**
<> 144:ef7eb2e8f9f7 1968 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
<> 144:ef7eb2e8f9f7 1969 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1970 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 1971 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 1972 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 1973 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 1974 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 1975 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 1976 * @retval HAL status
<> 144:ef7eb2e8f9f7 1977 */
<> 144:ef7eb2e8f9f7 1978 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 1979 {
<> 144:ef7eb2e8f9f7 1980 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1981 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 1982
<> 144:ef7eb2e8f9f7 1983 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1984 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 1985
<> 144:ef7eb2e8f9f7 1986 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 1987 {
<> 144:ef7eb2e8f9f7 1988 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 1989 {
<> 144:ef7eb2e8f9f7 1990 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1991 }
<> 144:ef7eb2e8f9f7 1992
<> 144:ef7eb2e8f9f7 1993 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 1994 {
<> 144:ef7eb2e8f9f7 1995 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1996 }
<> 144:ef7eb2e8f9f7 1997
<> 144:ef7eb2e8f9f7 1998 /* Process Locked */
<> 144:ef7eb2e8f9f7 1999 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 2002 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2003
<> 144:ef7eb2e8f9f7 2004 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 2005 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 2006 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2007
<> 144:ef7eb2e8f9f7 2008 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2009 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2010 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2011 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 2012 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2015 {
<> 144:ef7eb2e8f9f7 2016 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2017 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2018 }
<> 144:ef7eb2e8f9f7 2019 else
<> 144:ef7eb2e8f9f7 2020 {
<> 144:ef7eb2e8f9f7 2021 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2022 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 2023 }
<> 144:ef7eb2e8f9f7 2024
<> 144:ef7eb2e8f9f7 2025 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 2026 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2027 {
<> 144:ef7eb2e8f9f7 2028 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 2029 {
<> 144:ef7eb2e8f9f7 2030 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2031 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2032 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2033 }
<> 144:ef7eb2e8f9f7 2034 else
<> 144:ef7eb2e8f9f7 2035 {
<> 144:ef7eb2e8f9f7 2036 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2037 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2038 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2039 }
<> 144:ef7eb2e8f9f7 2040 }
<> 144:ef7eb2e8f9f7 2041
<> 144:ef7eb2e8f9f7 2042 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 2043 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2046 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2047
<> 144:ef7eb2e8f9f7 2048 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2049 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2050 process unlock */
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
<> 144:ef7eb2e8f9f7 2053 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 2054 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 2055 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 return HAL_OK;
<> 144:ef7eb2e8f9f7 2058 }
<> 144:ef7eb2e8f9f7 2059 else
<> 144:ef7eb2e8f9f7 2060 {
<> 144:ef7eb2e8f9f7 2061 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2062 }
<> 144:ef7eb2e8f9f7 2063 }
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 /**
<> 144:ef7eb2e8f9f7 2066 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
<> 144:ef7eb2e8f9f7 2067 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2068 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2069 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2070 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 2071 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 2072 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2073 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2074 * @retval HAL status
<> 144:ef7eb2e8f9f7 2075 */
<> 144:ef7eb2e8f9f7 2076 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 2077 {
<> 144:ef7eb2e8f9f7 2078 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2079 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 2080
<> 144:ef7eb2e8f9f7 2081 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2082 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 2083
<> 144:ef7eb2e8f9f7 2084 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2085 {
<> 144:ef7eb2e8f9f7 2086 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 2087 {
<> 144:ef7eb2e8f9f7 2088 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2089 }
<> 144:ef7eb2e8f9f7 2090
<> 144:ef7eb2e8f9f7 2091 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 2092 {
<> 144:ef7eb2e8f9f7 2093 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2094 }
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /* Process Locked */
<> 144:ef7eb2e8f9f7 2097 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 2100 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 2103 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 2104 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2107 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2108 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2109 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 2110 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 2111
<> 144:ef7eb2e8f9f7 2112 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2113 {
<> 144:ef7eb2e8f9f7 2114 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2115 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2116 }
<> 144:ef7eb2e8f9f7 2117 else
<> 144:ef7eb2e8f9f7 2118 {
<> 144:ef7eb2e8f9f7 2119 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2120 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 2121 }
<> 144:ef7eb2e8f9f7 2122
<> 144:ef7eb2e8f9f7 2123 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 2124 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2125 {
<> 144:ef7eb2e8f9f7 2126 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 2127 {
<> 144:ef7eb2e8f9f7 2128 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2129 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2130 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2131 }
<> 144:ef7eb2e8f9f7 2132 else
<> 144:ef7eb2e8f9f7 2133 {
<> 144:ef7eb2e8f9f7 2134 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2135 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2136 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2137 }
<> 144:ef7eb2e8f9f7 2138 }
<> 144:ef7eb2e8f9f7 2139
<> 144:ef7eb2e8f9f7 2140 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 2141 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 2142
<> 144:ef7eb2e8f9f7 2143 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2144 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2145
<> 144:ef7eb2e8f9f7 2146 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2147 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2148 process unlock */
<> 144:ef7eb2e8f9f7 2149
<> 144:ef7eb2e8f9f7 2150 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
<> 144:ef7eb2e8f9f7 2151 /* possible to enable all of these */
<> 144:ef7eb2e8f9f7 2152 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
<> 144:ef7eb2e8f9f7 2153 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 2154
<> 144:ef7eb2e8f9f7 2155 return HAL_OK;
<> 144:ef7eb2e8f9f7 2156 }
<> 144:ef7eb2e8f9f7 2157 else
<> 144:ef7eb2e8f9f7 2158 {
<> 144:ef7eb2e8f9f7 2159 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2160 }
<> 144:ef7eb2e8f9f7 2161 }
<> 144:ef7eb2e8f9f7 2162 /**
<> 144:ef7eb2e8f9f7 2163 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
<> 144:ef7eb2e8f9f7 2164 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2165 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2166 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2167 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 2168 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 2169 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2170 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2171 * @retval HAL status
<> 144:ef7eb2e8f9f7 2172 */
<> 144:ef7eb2e8f9f7 2173 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 2174 {
<> 144:ef7eb2e8f9f7 2175 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2176 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2179 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 2180
<> 144:ef7eb2e8f9f7 2181 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2182 {
<> 144:ef7eb2e8f9f7 2183 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 2184 {
<> 144:ef7eb2e8f9f7 2185 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2186 }
<> 144:ef7eb2e8f9f7 2187
<> 144:ef7eb2e8f9f7 2188 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 2189 {
<> 144:ef7eb2e8f9f7 2190 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2191 }
<> 144:ef7eb2e8f9f7 2192
<> 144:ef7eb2e8f9f7 2193 /* Process Locked */
<> 144:ef7eb2e8f9f7 2194 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2195
<> 144:ef7eb2e8f9f7 2196 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 2197 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 2200 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 2201 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2204 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2205 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2206 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 2207 hi2c->XferISR = I2C_Master_ISR_DMA;
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2210 {
<> 144:ef7eb2e8f9f7 2211 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2212 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2213 }
<> 144:ef7eb2e8f9f7 2214 else
<> 144:ef7eb2e8f9f7 2215 {
<> 144:ef7eb2e8f9f7 2216 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2217 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 2218 }
<> 144:ef7eb2e8f9f7 2219
<> 144:ef7eb2e8f9f7 2220 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 2221 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2222 {
<> 144:ef7eb2e8f9f7 2223 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 2224 {
<> 144:ef7eb2e8f9f7 2225 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2226 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2227 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2228 }
<> 144:ef7eb2e8f9f7 2229 else
<> 144:ef7eb2e8f9f7 2230 {
<> 144:ef7eb2e8f9f7 2231 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2232 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2233 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2234 }
<> 144:ef7eb2e8f9f7 2235 }
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2238 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
<> 144:ef7eb2e8f9f7 2239
<> 144:ef7eb2e8f9f7 2240 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2241 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 2242
<> 144:ef7eb2e8f9f7 2243 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 2244 hi2c->hdmatx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 2245 hi2c->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2248 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 2249
<> 144:ef7eb2e8f9f7 2250 /* Send Slave Address */
<> 144:ef7eb2e8f9f7 2251 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 2252 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 2253
<> 144:ef7eb2e8f9f7 2254 /* Update XferCount value */
<> 144:ef7eb2e8f9f7 2255 hi2c->XferCount -= hi2c->XferSize;
<> 144:ef7eb2e8f9f7 2256
<> 144:ef7eb2e8f9f7 2257 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2258 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2261 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2262 process unlock */
<> 144:ef7eb2e8f9f7 2263 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 2264 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<> 144:ef7eb2e8f9f7 2265
<> 144:ef7eb2e8f9f7 2266 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 2267 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 2268
<> 144:ef7eb2e8f9f7 2269 return HAL_OK;
<> 144:ef7eb2e8f9f7 2270 }
<> 144:ef7eb2e8f9f7 2271 else
<> 144:ef7eb2e8f9f7 2272 {
<> 144:ef7eb2e8f9f7 2273 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2274 }
<> 144:ef7eb2e8f9f7 2275 }
<> 144:ef7eb2e8f9f7 2276
<> 144:ef7eb2e8f9f7 2277 /**
<> 144:ef7eb2e8f9f7 2278 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
<> 144:ef7eb2e8f9f7 2279 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2280 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2281 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2282 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 2283 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 2284 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2285 * @param Size: Amount of data to be read
<> 144:ef7eb2e8f9f7 2286 * @retval HAL status
<> 144:ef7eb2e8f9f7 2287 */
<> 144:ef7eb2e8f9f7 2288 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 2289 {
<> 144:ef7eb2e8f9f7 2290 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2291 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 2292
<> 144:ef7eb2e8f9f7 2293 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2294 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2297 {
<> 144:ef7eb2e8f9f7 2298 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 2299 {
<> 144:ef7eb2e8f9f7 2300 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2301 }
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 2304 {
<> 144:ef7eb2e8f9f7 2305 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2306 }
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 /* Process Locked */
<> 144:ef7eb2e8f9f7 2309 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2310
<> 144:ef7eb2e8f9f7 2311 /* Init tickstart for timeout management*/
<> 144:ef7eb2e8f9f7 2312 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 2315 hi2c->Mode = HAL_I2C_MODE_MEM;
<> 144:ef7eb2e8f9f7 2316 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2317
<> 144:ef7eb2e8f9f7 2318 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2319 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2320 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2321 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 2322 hi2c->XferISR = I2C_Master_ISR_DMA;
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2325 {
<> 144:ef7eb2e8f9f7 2326 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2327 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2328 }
<> 144:ef7eb2e8f9f7 2329 else
<> 144:ef7eb2e8f9f7 2330 {
<> 144:ef7eb2e8f9f7 2331 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2332 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 2333 }
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 /* Send Slave Address and Memory Address */
<> 144:ef7eb2e8f9f7 2336 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2337 {
<> 144:ef7eb2e8f9f7 2338 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 2339 {
<> 144:ef7eb2e8f9f7 2340 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2341 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2342 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2343 }
<> 144:ef7eb2e8f9f7 2344 else
<> 144:ef7eb2e8f9f7 2345 {
<> 144:ef7eb2e8f9f7 2346 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2347 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2348 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2349 }
<> 144:ef7eb2e8f9f7 2350 }
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /* Set the I2C DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 2353 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2356 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Set the unused DMA callbacks to NULL */
<> 144:ef7eb2e8f9f7 2359 hi2c->hdmarx->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 2360 hi2c->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 2363 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
<> 144:ef7eb2e8f9f7 2366 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
<> 144:ef7eb2e8f9f7 2367
<> 144:ef7eb2e8f9f7 2368 /* Update XferCount value */
<> 144:ef7eb2e8f9f7 2369 hi2c->XferCount -= hi2c->XferSize;
<> 144:ef7eb2e8f9f7 2370
<> 144:ef7eb2e8f9f7 2371 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2372 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 2375 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2378 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2379 process unlock */
<> 144:ef7eb2e8f9f7 2380 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 2381 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 return HAL_OK;
<> 144:ef7eb2e8f9f7 2384 }
<> 144:ef7eb2e8f9f7 2385 else
<> 144:ef7eb2e8f9f7 2386 {
<> 144:ef7eb2e8f9f7 2387 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2388 }
<> 144:ef7eb2e8f9f7 2389 }
<> 144:ef7eb2e8f9f7 2390
<> 144:ef7eb2e8f9f7 2391 /**
<> 144:ef7eb2e8f9f7 2392 * @brief Checks if target device is ready for communication.
<> 144:ef7eb2e8f9f7 2393 * @note This function is used with Memory devices
<> 144:ef7eb2e8f9f7 2394 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2395 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2396 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2397 * @param Trials: Number of trials
<> 144:ef7eb2e8f9f7 2398 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 2399 * @retval HAL status
<> 144:ef7eb2e8f9f7 2400 */
<> 144:ef7eb2e8f9f7 2401 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 2402 {
<> 144:ef7eb2e8f9f7 2403 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 2404
<> 144:ef7eb2e8f9f7 2405 __IO uint32_t I2C_Trials = 0;
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2408 {
<> 144:ef7eb2e8f9f7 2409 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
<> 144:ef7eb2e8f9f7 2410 {
<> 144:ef7eb2e8f9f7 2411 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2412 }
<> 144:ef7eb2e8f9f7 2413
<> 144:ef7eb2e8f9f7 2414 /* Process Locked */
<> 144:ef7eb2e8f9f7 2415 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2416
<> 144:ef7eb2e8f9f7 2417 hi2c->State = HAL_I2C_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2418 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2419
<> 144:ef7eb2e8f9f7 2420 do
<> 144:ef7eb2e8f9f7 2421 {
<> 144:ef7eb2e8f9f7 2422 /* Generate Start */
<> 144:ef7eb2e8f9f7 2423 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
<> 144:ef7eb2e8f9f7 2426 /* Wait until STOPF flag is set or a NACK flag is set*/
<> 144:ef7eb2e8f9f7 2427 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 2428 while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
<> 144:ef7eb2e8f9f7 2429 {
<> 144:ef7eb2e8f9f7 2430 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 2431 {
<> 144:ef7eb2e8f9f7 2432 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 2433 {
<> 144:ef7eb2e8f9f7 2434 /* Device is ready */
<> 144:ef7eb2e8f9f7 2435 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 2436 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2437 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2438 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2439 }
<> 144:ef7eb2e8f9f7 2440 }
<> 144:ef7eb2e8f9f7 2441 }
<> 144:ef7eb2e8f9f7 2442
<> 144:ef7eb2e8f9f7 2443 /* Check if the NACKF flag has not been set */
<> 144:ef7eb2e8f9f7 2444 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
<> 144:ef7eb2e8f9f7 2445 {
<> 144:ef7eb2e8f9f7 2446 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 2447 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2448 {
<> 144:ef7eb2e8f9f7 2449 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2450 }
<> 144:ef7eb2e8f9f7 2451
<> 144:ef7eb2e8f9f7 2452 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 2453 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 2454
<> 144:ef7eb2e8f9f7 2455 /* Device is ready */
<> 144:ef7eb2e8f9f7 2456 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 2457
<> 144:ef7eb2e8f9f7 2458 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2459 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2460
<> 144:ef7eb2e8f9f7 2461 return HAL_OK;
<> 144:ef7eb2e8f9f7 2462 }
<> 144:ef7eb2e8f9f7 2463 else
<> 144:ef7eb2e8f9f7 2464 {
<> 144:ef7eb2e8f9f7 2465 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 2466 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2467 {
<> 144:ef7eb2e8f9f7 2468 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2469 }
<> 144:ef7eb2e8f9f7 2470
<> 144:ef7eb2e8f9f7 2471 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 2472 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /* Clear STOP Flag, auto generated with autoend*/
<> 144:ef7eb2e8f9f7 2475 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 2476 }
<> 144:ef7eb2e8f9f7 2477
<> 144:ef7eb2e8f9f7 2478 /* Check if the maximum allowed number of trials has been reached */
<> 144:ef7eb2e8f9f7 2479 if (I2C_Trials++ == Trials)
<> 144:ef7eb2e8f9f7 2480 {
<> 144:ef7eb2e8f9f7 2481 /* Generate Stop */
<> 144:ef7eb2e8f9f7 2482 hi2c->Instance->CR2 |= I2C_CR2_STOP;
<> 144:ef7eb2e8f9f7 2483
<> 144:ef7eb2e8f9f7 2484 /* Wait until STOPF flag is reset */
<> 144:ef7eb2e8f9f7 2485 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 2486 {
<> 144:ef7eb2e8f9f7 2487 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2488 }
<> 144:ef7eb2e8f9f7 2489
<> 144:ef7eb2e8f9f7 2490 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 2491 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 2492 }
<> 144:ef7eb2e8f9f7 2493 }while(I2C_Trials < Trials);
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 2496
<> 144:ef7eb2e8f9f7 2497 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2498 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2499
<> 144:ef7eb2e8f9f7 2500 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 2501 }
<> 144:ef7eb2e8f9f7 2502 else
<> 144:ef7eb2e8f9f7 2503 {
<> 144:ef7eb2e8f9f7 2504 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2505 }
<> 144:ef7eb2e8f9f7 2506 }
<> 144:ef7eb2e8f9f7 2507
<> 144:ef7eb2e8f9f7 2508 /**
<> 144:ef7eb2e8f9f7 2509 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
<> 144:ef7eb2e8f9f7 2510 * @note This interface allow to manage repeated start condition when a direction change during transfer
<> 144:ef7eb2e8f9f7 2511 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2512 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2513 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2514 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2515 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2516 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
<> 144:ef7eb2e8f9f7 2517 * @retval HAL status
<> 144:ef7eb2e8f9f7 2518 */
<> 144:ef7eb2e8f9f7 2519 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 2520 {
<> 144:ef7eb2e8f9f7 2521 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 2522 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2525 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 2526
<> 144:ef7eb2e8f9f7 2527 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2528 {
<> 144:ef7eb2e8f9f7 2529 /* Process Locked */
<> 144:ef7eb2e8f9f7 2530 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2531
<> 144:ef7eb2e8f9f7 2532 hi2c->State = HAL_I2C_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 2533 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 2534 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2535
<> 144:ef7eb2e8f9f7 2536 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2537 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2538 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2539 hi2c->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 2540 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 2541
<> 144:ef7eb2e8f9f7 2542 /* If size > MAX_NBYTE_SIZE, use reload mode */
<> 144:ef7eb2e8f9f7 2543 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2544 {
<> 144:ef7eb2e8f9f7 2545 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2546 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2547 }
<> 144:ef7eb2e8f9f7 2548 else
<> 144:ef7eb2e8f9f7 2549 {
<> 144:ef7eb2e8f9f7 2550 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2551 xfermode = hi2c->XferOptions;
<> 144:ef7eb2e8f9f7 2552
<> 144:ef7eb2e8f9f7 2553 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 2554 /* Mean Previous state is same as current state */
<> 144:ef7eb2e8f9f7 2555 if(hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_TX)
<> 144:ef7eb2e8f9f7 2556 {
<> 144:ef7eb2e8f9f7 2557 xferrequest = I2C_NO_STARTSTOP;
<> 144:ef7eb2e8f9f7 2558 }
<> 144:ef7eb2e8f9f7 2559 }
<> 144:ef7eb2e8f9f7 2560
<> 144:ef7eb2e8f9f7 2561 /* Send Slave Address and set NBYTES to write */
<> 144:ef7eb2e8f9f7 2562 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2565 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2566
<> 144:ef7eb2e8f9f7 2567 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2568 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2569 process unlock */
<> 144:ef7eb2e8f9f7 2570 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 2571
<> 144:ef7eb2e8f9f7 2572 return HAL_OK;
<> 144:ef7eb2e8f9f7 2573 }
<> 144:ef7eb2e8f9f7 2574 else
<> 144:ef7eb2e8f9f7 2575 {
<> 144:ef7eb2e8f9f7 2576 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2577 }
<> 144:ef7eb2e8f9f7 2578 }
<> 144:ef7eb2e8f9f7 2579
<> 144:ef7eb2e8f9f7 2580 /**
<> 144:ef7eb2e8f9f7 2581 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 2582 * @note This interface allow to manage repeated start condition when a direction change during transfer
<> 144:ef7eb2e8f9f7 2583 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2584 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2585 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2586 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2587 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2588 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
<> 144:ef7eb2e8f9f7 2589 * @retval HAL status
<> 144:ef7eb2e8f9f7 2590 */
<> 144:ef7eb2e8f9f7 2591 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 2592 {
<> 144:ef7eb2e8f9f7 2593 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 2594 uint32_t xferrequest = I2C_GENERATE_START_READ;
<> 144:ef7eb2e8f9f7 2595
<> 144:ef7eb2e8f9f7 2596 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2597 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 2598
<> 144:ef7eb2e8f9f7 2599 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2600 {
<> 144:ef7eb2e8f9f7 2601 /* Process Locked */
<> 144:ef7eb2e8f9f7 2602 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2603
<> 144:ef7eb2e8f9f7 2604 hi2c->State = HAL_I2C_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 2605 hi2c->Mode = HAL_I2C_MODE_MASTER;
<> 144:ef7eb2e8f9f7 2606 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2607
<> 144:ef7eb2e8f9f7 2608 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2609 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2610 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2611 hi2c->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 2612 hi2c->XferISR = I2C_Master_ISR_IT;
<> 144:ef7eb2e8f9f7 2613
<> 144:ef7eb2e8f9f7 2614 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
<> 144:ef7eb2e8f9f7 2615 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 2616 {
<> 144:ef7eb2e8f9f7 2617 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 2618 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 2619 }
<> 144:ef7eb2e8f9f7 2620 else
<> 144:ef7eb2e8f9f7 2621 {
<> 144:ef7eb2e8f9f7 2622 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2623 xfermode = hi2c->XferOptions;
<> 144:ef7eb2e8f9f7 2624
<> 144:ef7eb2e8f9f7 2625 /* If transfer direction not change, do not generate Restart Condition */
<> 144:ef7eb2e8f9f7 2626 /* Mean Previous state is same as current state */
<> 144:ef7eb2e8f9f7 2627 if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<> 144:ef7eb2e8f9f7 2628 {
<> 144:ef7eb2e8f9f7 2629 xferrequest = I2C_NO_STARTSTOP;
<> 144:ef7eb2e8f9f7 2630 }
<> 144:ef7eb2e8f9f7 2631 }
<> 144:ef7eb2e8f9f7 2632
<> 144:ef7eb2e8f9f7 2633 /* Send Slave Address and set NBYTES to read */
<> 144:ef7eb2e8f9f7 2634 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
<> 144:ef7eb2e8f9f7 2635
<> 144:ef7eb2e8f9f7 2636 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2637 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2638
<> 144:ef7eb2e8f9f7 2639 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2640 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2641 process unlock */
<> 144:ef7eb2e8f9f7 2642 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 2643
<> 144:ef7eb2e8f9f7 2644 return HAL_OK;
<> 144:ef7eb2e8f9f7 2645 }
<> 144:ef7eb2e8f9f7 2646 else
<> 144:ef7eb2e8f9f7 2647 {
<> 144:ef7eb2e8f9f7 2648 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2649 }
<> 144:ef7eb2e8f9f7 2650 }
<> 144:ef7eb2e8f9f7 2651
<> 144:ef7eb2e8f9f7 2652 /**
<> 144:ef7eb2e8f9f7 2653 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 2654 * @note This interface allow to manage repeated start condition when a direction change during transfer
<> 144:ef7eb2e8f9f7 2655 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2656 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2657 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2658 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2659 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
<> 144:ef7eb2e8f9f7 2660 * @retval HAL status
<> 144:ef7eb2e8f9f7 2661 */
<> 144:ef7eb2e8f9f7 2662 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 2663 {
<> 144:ef7eb2e8f9f7 2664 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2665 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 2666
<> 144:ef7eb2e8f9f7 2667 if(hi2c->State == HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 2668 {
<> 144:ef7eb2e8f9f7 2669 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 2670 {
<> 144:ef7eb2e8f9f7 2671 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2672 }
<> 144:ef7eb2e8f9f7 2673
<> 144:ef7eb2e8f9f7 2674 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 2675 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 2676
<> 144:ef7eb2e8f9f7 2677 /* Process Locked */
<> 144:ef7eb2e8f9f7 2678 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2679
<> 144:ef7eb2e8f9f7 2680 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
<> 144:ef7eb2e8f9f7 2681 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 2682 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2683
<> 144:ef7eb2e8f9f7 2684 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 2685 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 2686
<> 144:ef7eb2e8f9f7 2687 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2688 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2689 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2690 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2691 hi2c->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 2692 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 2693
<> 144:ef7eb2e8f9f7 2694 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
<> 144:ef7eb2e8f9f7 2695 {
<> 144:ef7eb2e8f9f7 2696 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 2697 /* This action will generate an acknowledge to the Master */
<> 144:ef7eb2e8f9f7 2698 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 2699 }
<> 144:ef7eb2e8f9f7 2700
<> 144:ef7eb2e8f9f7 2701 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2702 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2703
<> 144:ef7eb2e8f9f7 2704 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2705 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2706 process unlock */
<> 144:ef7eb2e8f9f7 2707 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 2708 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 2709
<> 144:ef7eb2e8f9f7 2710 return HAL_OK;
<> 144:ef7eb2e8f9f7 2711 }
<> 144:ef7eb2e8f9f7 2712 else
<> 144:ef7eb2e8f9f7 2713 {
<> 144:ef7eb2e8f9f7 2714 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2715 }
<> 144:ef7eb2e8f9f7 2716 }
<> 144:ef7eb2e8f9f7 2717
<> 144:ef7eb2e8f9f7 2718 /**
<> 144:ef7eb2e8f9f7 2719 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 2720 * @note This interface allow to manage repeated start condition when a direction change during transfer
<> 144:ef7eb2e8f9f7 2721 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2722 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2723 * @param pData: Pointer to data buffer
<> 144:ef7eb2e8f9f7 2724 * @param Size: Amount of data to be sent
<> 144:ef7eb2e8f9f7 2725 * @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
<> 144:ef7eb2e8f9f7 2726 * @retval HAL status
<> 144:ef7eb2e8f9f7 2727 */
<> 144:ef7eb2e8f9f7 2728 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
<> 144:ef7eb2e8f9f7 2729 {
<> 144:ef7eb2e8f9f7 2730 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2731 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<> 144:ef7eb2e8f9f7 2732
<> 144:ef7eb2e8f9f7 2733 if(hi2c->State == HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 2734 {
<> 144:ef7eb2e8f9f7 2735 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 2736 {
<> 144:ef7eb2e8f9f7 2737 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2738 }
<> 144:ef7eb2e8f9f7 2739
<> 144:ef7eb2e8f9f7 2740 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
<> 144:ef7eb2e8f9f7 2741 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 2742
<> 144:ef7eb2e8f9f7 2743 /* Process Locked */
<> 144:ef7eb2e8f9f7 2744 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2745
<> 144:ef7eb2e8f9f7 2746 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
<> 144:ef7eb2e8f9f7 2747 hi2c->Mode = HAL_I2C_MODE_SLAVE;
<> 144:ef7eb2e8f9f7 2748 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 2749
<> 144:ef7eb2e8f9f7 2750 /* Enable Address Acknowledge */
<> 144:ef7eb2e8f9f7 2751 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 2752
<> 144:ef7eb2e8f9f7 2753 /* Prepare transfer parameters */
<> 144:ef7eb2e8f9f7 2754 hi2c->pBuffPtr = pData;
<> 144:ef7eb2e8f9f7 2755 hi2c->XferCount = Size;
<> 144:ef7eb2e8f9f7 2756 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 2757 hi2c->XferOptions = XferOptions;
<> 144:ef7eb2e8f9f7 2758 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 2759
<> 144:ef7eb2e8f9f7 2760 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
<> 144:ef7eb2e8f9f7 2761 {
<> 144:ef7eb2e8f9f7 2762 /* Clear ADDR flag after prepare the transfer parameters */
<> 144:ef7eb2e8f9f7 2763 /* This action will generate an acknowledge to the Master */
<> 144:ef7eb2e8f9f7 2764 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 2765 }
<> 144:ef7eb2e8f9f7 2766
<> 144:ef7eb2e8f9f7 2767 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2768 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2769
<> 144:ef7eb2e8f9f7 2770 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2771 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2772 process unlock */
<> 144:ef7eb2e8f9f7 2773 /* REnable ADDR interrupt */
<> 144:ef7eb2e8f9f7 2774 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 2775
<> 144:ef7eb2e8f9f7 2776 return HAL_OK;
<> 144:ef7eb2e8f9f7 2777 }
<> 144:ef7eb2e8f9f7 2778 else
<> 144:ef7eb2e8f9f7 2779 {
<> 144:ef7eb2e8f9f7 2780 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2781 }
<> 144:ef7eb2e8f9f7 2782 }
<> 144:ef7eb2e8f9f7 2783
<> 144:ef7eb2e8f9f7 2784 /**
<> 144:ef7eb2e8f9f7 2785 * @brief Enable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 2786 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2787 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2788 * @retval HAL status
<> 144:ef7eb2e8f9f7 2789 */
<> 144:ef7eb2e8f9f7 2790 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2791 {
<> 144:ef7eb2e8f9f7 2792 if(hi2c->State == HAL_I2C_STATE_READY)
<> 144:ef7eb2e8f9f7 2793 {
<> 144:ef7eb2e8f9f7 2794 hi2c->State = HAL_I2C_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 2795 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 2796
<> 144:ef7eb2e8f9f7 2797 /* Enable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 2798 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 2799
<> 144:ef7eb2e8f9f7 2800 return HAL_OK;
<> 144:ef7eb2e8f9f7 2801 }
<> 144:ef7eb2e8f9f7 2802 else
<> 144:ef7eb2e8f9f7 2803 {
<> 144:ef7eb2e8f9f7 2804 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2805 }
<> 144:ef7eb2e8f9f7 2806 }
<> 144:ef7eb2e8f9f7 2807
<> 144:ef7eb2e8f9f7 2808 /**
<> 144:ef7eb2e8f9f7 2809 * @brief Disable the Address listen mode with Interrupt.
<> 144:ef7eb2e8f9f7 2810 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2811 * the configuration information for the specified I2C
<> 144:ef7eb2e8f9f7 2812 * @retval HAL status
<> 144:ef7eb2e8f9f7 2813 */
<> 144:ef7eb2e8f9f7 2814 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2815 {
<> 144:ef7eb2e8f9f7 2816 /* Declaration of tmp to prevent undefined behavior of volatile usage */
<> 144:ef7eb2e8f9f7 2817 uint32_t tmp;
<> 144:ef7eb2e8f9f7 2818
<> 144:ef7eb2e8f9f7 2819 /* Disable Address listen mode only if a transfer is not ongoing */
<> 144:ef7eb2e8f9f7 2820 if(hi2c->State == HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 2821 {
<> 144:ef7eb2e8f9f7 2822 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<> 144:ef7eb2e8f9f7 2823 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
<> 144:ef7eb2e8f9f7 2824 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 2825 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 2826 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 2827
<> 144:ef7eb2e8f9f7 2828 /* Disable the Address Match interrupt */
<> 144:ef7eb2e8f9f7 2829 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 2830
<> 144:ef7eb2e8f9f7 2831 return HAL_OK;
<> 144:ef7eb2e8f9f7 2832 }
<> 144:ef7eb2e8f9f7 2833 else
<> 144:ef7eb2e8f9f7 2834 {
<> 144:ef7eb2e8f9f7 2835 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2836 }
<> 144:ef7eb2e8f9f7 2837 }
<> 144:ef7eb2e8f9f7 2838
<> 144:ef7eb2e8f9f7 2839 /**
<> 144:ef7eb2e8f9f7 2840 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
<> 144:ef7eb2e8f9f7 2841 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2842 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2843 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 2844 * @retval HAL status
<> 144:ef7eb2e8f9f7 2845 */
<> 144:ef7eb2e8f9f7 2846 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<> 144:ef7eb2e8f9f7 2847 {
<> 144:ef7eb2e8f9f7 2848 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<> 144:ef7eb2e8f9f7 2849 {
<> 144:ef7eb2e8f9f7 2850 /* Process Locked */
<> 144:ef7eb2e8f9f7 2851 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 2852
<> 144:ef7eb2e8f9f7 2853 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 2854 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 2855 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 2856
<> 144:ef7eb2e8f9f7 2857 /* Set State at HAL_I2C_STATE_ABORT */
<> 144:ef7eb2e8f9f7 2858 hi2c->State = HAL_I2C_STATE_ABORT;
<> 144:ef7eb2e8f9f7 2859
<> 144:ef7eb2e8f9f7 2860 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
<> 144:ef7eb2e8f9f7 2861 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
<> 144:ef7eb2e8f9f7 2862 I2C_TransferConfig(hi2c, 0, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
<> 144:ef7eb2e8f9f7 2863
<> 144:ef7eb2e8f9f7 2864 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 2865 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 2866
<> 144:ef7eb2e8f9f7 2867 /* Note : The I2C interrupts must be enabled after unlocking current process
<> 144:ef7eb2e8f9f7 2868 to avoid the risk of I2C interrupt handle execution before current
<> 144:ef7eb2e8f9f7 2869 process unlock */
<> 144:ef7eb2e8f9f7 2870 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<> 144:ef7eb2e8f9f7 2871
<> 144:ef7eb2e8f9f7 2872 return HAL_OK;
<> 144:ef7eb2e8f9f7 2873 }
<> 144:ef7eb2e8f9f7 2874 else
<> 144:ef7eb2e8f9f7 2875 {
<> 144:ef7eb2e8f9f7 2876 /* Wrong usage of abort function */
<> 144:ef7eb2e8f9f7 2877 /* This function should be used only in case of abort monitored by master device */
<> 144:ef7eb2e8f9f7 2878 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2879 }
<> 144:ef7eb2e8f9f7 2880 }
<> 144:ef7eb2e8f9f7 2881
<> 144:ef7eb2e8f9f7 2882 /**
<> 144:ef7eb2e8f9f7 2883 * @}
<> 144:ef7eb2e8f9f7 2884 */
<> 144:ef7eb2e8f9f7 2885
<> 144:ef7eb2e8f9f7 2886 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 2887 * @{
<> 144:ef7eb2e8f9f7 2888 */
<> 144:ef7eb2e8f9f7 2889
<> 144:ef7eb2e8f9f7 2890 /**
<> 144:ef7eb2e8f9f7 2891 * @brief This function handles I2C event interrupt request.
<> 144:ef7eb2e8f9f7 2892 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2893 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2894 * @retval None
<> 144:ef7eb2e8f9f7 2895 */
<> 144:ef7eb2e8f9f7 2896 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2897 {
<> 144:ef7eb2e8f9f7 2898 /* Get current IT Flags and IT sources value */
<> 144:ef7eb2e8f9f7 2899 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
<> 144:ef7eb2e8f9f7 2900 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
<> 144:ef7eb2e8f9f7 2901
<> 144:ef7eb2e8f9f7 2902 /* I2C events treatment -------------------------------------*/
<> 144:ef7eb2e8f9f7 2903 if(hi2c->XferISR != NULL)
<> 144:ef7eb2e8f9f7 2904 {
<> 144:ef7eb2e8f9f7 2905 hi2c->XferISR(hi2c, itflags, itsources);
<> 144:ef7eb2e8f9f7 2906 }
<> 144:ef7eb2e8f9f7 2907 }
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 /**
<> 144:ef7eb2e8f9f7 2910 * @brief This function handles I2C error interrupt request.
<> 144:ef7eb2e8f9f7 2911 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2912 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2913 * @retval None
<> 144:ef7eb2e8f9f7 2914 */
<> 144:ef7eb2e8f9f7 2915 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2916 {
<> 144:ef7eb2e8f9f7 2917 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
<> 144:ef7eb2e8f9f7 2918 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
<> 144:ef7eb2e8f9f7 2919
<> 144:ef7eb2e8f9f7 2920 /* I2C Bus error interrupt occurred ------------------------------------*/
<> 144:ef7eb2e8f9f7 2921 if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 2922 {
<> 144:ef7eb2e8f9f7 2923 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
<> 144:ef7eb2e8f9f7 2924
<> 144:ef7eb2e8f9f7 2925 /* Clear BERR flag */
<> 144:ef7eb2e8f9f7 2926 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<> 144:ef7eb2e8f9f7 2927 }
<> 144:ef7eb2e8f9f7 2928
<> 144:ef7eb2e8f9f7 2929 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
<> 144:ef7eb2e8f9f7 2930 if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 2931 {
<> 144:ef7eb2e8f9f7 2932 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
<> 144:ef7eb2e8f9f7 2933
<> 144:ef7eb2e8f9f7 2934 /* Clear OVR flag */
<> 144:ef7eb2e8f9f7 2935 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<> 144:ef7eb2e8f9f7 2936 }
<> 144:ef7eb2e8f9f7 2937
<> 144:ef7eb2e8f9f7 2938 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 2939 if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
<> 144:ef7eb2e8f9f7 2940 {
<> 144:ef7eb2e8f9f7 2941 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
<> 144:ef7eb2e8f9f7 2942
<> 144:ef7eb2e8f9f7 2943 /* Clear ARLO flag */
<> 144:ef7eb2e8f9f7 2944 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<> 144:ef7eb2e8f9f7 2945 }
<> 144:ef7eb2e8f9f7 2946
<> 144:ef7eb2e8f9f7 2947 /* Call the Error Callback in case of Error detected */
<> 144:ef7eb2e8f9f7 2948 if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
<> 144:ef7eb2e8f9f7 2949 {
<> 144:ef7eb2e8f9f7 2950 I2C_ITError(hi2c, hi2c->ErrorCode);
<> 144:ef7eb2e8f9f7 2951 }
<> 144:ef7eb2e8f9f7 2952 }
<> 144:ef7eb2e8f9f7 2953
<> 144:ef7eb2e8f9f7 2954 /**
<> 144:ef7eb2e8f9f7 2955 * @brief Master Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2956 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2957 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2958 * @retval None
<> 144:ef7eb2e8f9f7 2959 */
<> 144:ef7eb2e8f9f7 2960 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2961 {
<> 144:ef7eb2e8f9f7 2962 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2963 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 2964
<> 144:ef7eb2e8f9f7 2965 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2966 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2967 */
<> 144:ef7eb2e8f9f7 2968 }
<> 144:ef7eb2e8f9f7 2969
<> 144:ef7eb2e8f9f7 2970 /**
<> 144:ef7eb2e8f9f7 2971 * @brief Master Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2972 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2973 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2974 * @retval None
<> 144:ef7eb2e8f9f7 2975 */
<> 144:ef7eb2e8f9f7 2976 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2977 {
<> 144:ef7eb2e8f9f7 2978 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2979 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 2980
<> 144:ef7eb2e8f9f7 2981 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2982 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2983 */
<> 144:ef7eb2e8f9f7 2984 }
<> 144:ef7eb2e8f9f7 2985
<> 144:ef7eb2e8f9f7 2986 /** @brief Slave Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 2987 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2988 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 2989 * @retval None
<> 144:ef7eb2e8f9f7 2990 */
<> 144:ef7eb2e8f9f7 2991 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 2992 {
<> 144:ef7eb2e8f9f7 2993 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2994 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 2995
<> 144:ef7eb2e8f9f7 2996 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2997 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 2998 */
<> 144:ef7eb2e8f9f7 2999 }
<> 144:ef7eb2e8f9f7 3000
<> 144:ef7eb2e8f9f7 3001 /**
<> 144:ef7eb2e8f9f7 3002 * @brief Slave Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 3003 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3004 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3005 * @retval None
<> 144:ef7eb2e8f9f7 3006 */
<> 144:ef7eb2e8f9f7 3007 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3008 {
<> 144:ef7eb2e8f9f7 3009 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3010 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3011
<> 144:ef7eb2e8f9f7 3012 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3013 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 3014 */
<> 144:ef7eb2e8f9f7 3015 }
<> 144:ef7eb2e8f9f7 3016
<> 144:ef7eb2e8f9f7 3017 /**
<> 144:ef7eb2e8f9f7 3018 * @brief Slave Address Match callback.
<> 144:ef7eb2e8f9f7 3019 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3020 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3021 * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
<> 144:ef7eb2e8f9f7 3022 * @param AddrMatchCode: Address Match Code
<> 144:ef7eb2e8f9f7 3023 * @retval None
<> 144:ef7eb2e8f9f7 3024 */
<> 144:ef7eb2e8f9f7 3025 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<> 144:ef7eb2e8f9f7 3026 {
<> 144:ef7eb2e8f9f7 3027 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3028 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3029 UNUSED(TransferDirection);
<> 144:ef7eb2e8f9f7 3030 UNUSED(AddrMatchCode);
<> 144:ef7eb2e8f9f7 3031
<> 144:ef7eb2e8f9f7 3032 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3033 the HAL_I2C_AddrCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 3034 */
<> 144:ef7eb2e8f9f7 3035 }
<> 144:ef7eb2e8f9f7 3036
<> 144:ef7eb2e8f9f7 3037 /**
<> 144:ef7eb2e8f9f7 3038 * @brief Listen Complete callback.
<> 144:ef7eb2e8f9f7 3039 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3040 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3041 * @retval None
<> 144:ef7eb2e8f9f7 3042 */
<> 144:ef7eb2e8f9f7 3043 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3044 {
<> 144:ef7eb2e8f9f7 3045 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3046 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3047
<> 144:ef7eb2e8f9f7 3048 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3049 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
<> 144:ef7eb2e8f9f7 3050 */
<> 144:ef7eb2e8f9f7 3051 }
<> 144:ef7eb2e8f9f7 3052
<> 144:ef7eb2e8f9f7 3053 /**
<> 144:ef7eb2e8f9f7 3054 * @brief Memory Tx Transfer completed callback.
<> 144:ef7eb2e8f9f7 3055 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3056 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3057 * @retval None
<> 144:ef7eb2e8f9f7 3058 */
<> 144:ef7eb2e8f9f7 3059 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3060 {
<> 144:ef7eb2e8f9f7 3061 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3062 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3063
<> 144:ef7eb2e8f9f7 3064 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3065 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 3066 */
<> 144:ef7eb2e8f9f7 3067 }
<> 144:ef7eb2e8f9f7 3068
<> 144:ef7eb2e8f9f7 3069 /**
<> 144:ef7eb2e8f9f7 3070 * @brief Memory Rx Transfer completed callback.
<> 144:ef7eb2e8f9f7 3071 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3072 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3073 * @retval None
<> 144:ef7eb2e8f9f7 3074 */
<> 144:ef7eb2e8f9f7 3075 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3076 {
<> 144:ef7eb2e8f9f7 3077 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3078 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3079
<> 144:ef7eb2e8f9f7 3080 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3081 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 3082 */
<> 144:ef7eb2e8f9f7 3083 }
<> 144:ef7eb2e8f9f7 3084
<> 144:ef7eb2e8f9f7 3085 /**
<> 144:ef7eb2e8f9f7 3086 * @brief I2C error callback.
<> 144:ef7eb2e8f9f7 3087 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3088 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3089 * @retval None
<> 144:ef7eb2e8f9f7 3090 */
<> 144:ef7eb2e8f9f7 3091 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3092 {
<> 144:ef7eb2e8f9f7 3093 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3094 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3095
<> 144:ef7eb2e8f9f7 3096 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3097 the HAL_I2C_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 3098 */
<> 144:ef7eb2e8f9f7 3099 }
<> 144:ef7eb2e8f9f7 3100
<> 144:ef7eb2e8f9f7 3101 /**
<> 144:ef7eb2e8f9f7 3102 * @brief I2C abort callback.
<> 144:ef7eb2e8f9f7 3103 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3104 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3105 * @retval None
<> 144:ef7eb2e8f9f7 3106 */
<> 144:ef7eb2e8f9f7 3107 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3108 {
<> 144:ef7eb2e8f9f7 3109 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 3110 UNUSED(hi2c);
<> 144:ef7eb2e8f9f7 3111
<> 144:ef7eb2e8f9f7 3112 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 3113 the HAL_I2C_AbortCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 3114 */
<> 144:ef7eb2e8f9f7 3115 }
<> 144:ef7eb2e8f9f7 3116
<> 144:ef7eb2e8f9f7 3117 /**
<> 144:ef7eb2e8f9f7 3118 * @}
<> 144:ef7eb2e8f9f7 3119 */
<> 144:ef7eb2e8f9f7 3120
<> 144:ef7eb2e8f9f7 3121 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<> 144:ef7eb2e8f9f7 3122 * @brief Peripheral State, Mode and Error functions
<> 144:ef7eb2e8f9f7 3123 *
<> 144:ef7eb2e8f9f7 3124 @verbatim
<> 144:ef7eb2e8f9f7 3125 ===============================================================================
<> 144:ef7eb2e8f9f7 3126 ##### Peripheral State, Mode and Error functions #####
<> 144:ef7eb2e8f9f7 3127 ===============================================================================
<> 144:ef7eb2e8f9f7 3128 [..]
<> 144:ef7eb2e8f9f7 3129 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 3130 and the data flow.
<> 144:ef7eb2e8f9f7 3131
<> 144:ef7eb2e8f9f7 3132 @endverbatim
<> 144:ef7eb2e8f9f7 3133 * @{
<> 144:ef7eb2e8f9f7 3134 */
<> 144:ef7eb2e8f9f7 3135
<> 144:ef7eb2e8f9f7 3136 /**
<> 144:ef7eb2e8f9f7 3137 * @brief Return the I2C handle state.
<> 144:ef7eb2e8f9f7 3138 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3139 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3140 * @retval HAL state
<> 144:ef7eb2e8f9f7 3141 */
<> 144:ef7eb2e8f9f7 3142 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3143 {
<> 144:ef7eb2e8f9f7 3144 /* Return I2C handle state */
<> 144:ef7eb2e8f9f7 3145 return hi2c->State;
<> 144:ef7eb2e8f9f7 3146 }
<> 144:ef7eb2e8f9f7 3147
<> 144:ef7eb2e8f9f7 3148 /**
<> 144:ef7eb2e8f9f7 3149 * @brief Returns the I2C Master, Slave, Memory or no mode.
<> 144:ef7eb2e8f9f7 3150 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3151 * the configuration information for I2C module
<> 144:ef7eb2e8f9f7 3152 * @retval HAL mode
<> 144:ef7eb2e8f9f7 3153 */
<> 144:ef7eb2e8f9f7 3154 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3155 {
<> 144:ef7eb2e8f9f7 3156 return hi2c->Mode;
<> 144:ef7eb2e8f9f7 3157 }
<> 144:ef7eb2e8f9f7 3158
<> 144:ef7eb2e8f9f7 3159 /**
<> 144:ef7eb2e8f9f7 3160 * @brief Return the I2C error code.
<> 144:ef7eb2e8f9f7 3161 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3162 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3163 * @retval I2C Error Code
<> 144:ef7eb2e8f9f7 3164 */
<> 144:ef7eb2e8f9f7 3165 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3166 {
<> 144:ef7eb2e8f9f7 3167 return hi2c->ErrorCode;
<> 144:ef7eb2e8f9f7 3168 }
<> 144:ef7eb2e8f9f7 3169
<> 144:ef7eb2e8f9f7 3170 /**
<> 144:ef7eb2e8f9f7 3171 * @}
<> 144:ef7eb2e8f9f7 3172 */
<> 144:ef7eb2e8f9f7 3173
<> 144:ef7eb2e8f9f7 3174 /**
<> 144:ef7eb2e8f9f7 3175 * @}
<> 144:ef7eb2e8f9f7 3176 */
<> 144:ef7eb2e8f9f7 3177
<> 144:ef7eb2e8f9f7 3178 /** @addtogroup I2C_Private_Functions
<> 144:ef7eb2e8f9f7 3179 * @{
<> 144:ef7eb2e8f9f7 3180 */
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 /**
<> 144:ef7eb2e8f9f7 3183 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
<> 144:ef7eb2e8f9f7 3184 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3185 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3186 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3187 * @param ITSources: Interrupt sources enabled.
<> 144:ef7eb2e8f9f7 3188 * @retval HAL status
<> 144:ef7eb2e8f9f7 3189 */
<> 144:ef7eb2e8f9f7 3190 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<> 144:ef7eb2e8f9f7 3191 {
<> 144:ef7eb2e8f9f7 3192 uint16_t devaddress = 0;
<> 144:ef7eb2e8f9f7 3193
<> 144:ef7eb2e8f9f7 3194 /* Process Locked */
<> 144:ef7eb2e8f9f7 3195 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 3196
<> 144:ef7eb2e8f9f7 3197 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<> 144:ef7eb2e8f9f7 3198 {
<> 144:ef7eb2e8f9f7 3199 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3200 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3201
<> 144:ef7eb2e8f9f7 3202 /* Set corresponding Error Code */
<> 144:ef7eb2e8f9f7 3203 /* No need to generate STOP, it is automatically done */
<> 144:ef7eb2e8f9f7 3204 /* Error callback will be send during stop flag treatment */
<> 144:ef7eb2e8f9f7 3205 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3206
<> 144:ef7eb2e8f9f7 3207 /* Flush TX register */
<> 144:ef7eb2e8f9f7 3208 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 3209 }
<> 144:ef7eb2e8f9f7 3210 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
<> 144:ef7eb2e8f9f7 3211 {
<> 144:ef7eb2e8f9f7 3212 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 3213 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 3214 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 3215 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 3216 }
<> 144:ef7eb2e8f9f7 3217 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
<> 144:ef7eb2e8f9f7 3218 {
<> 144:ef7eb2e8f9f7 3219 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 3220 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<> 144:ef7eb2e8f9f7 3221 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 3222 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 3223 }
<> 144:ef7eb2e8f9f7 3224 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<> 144:ef7eb2e8f9f7 3225 {
<> 144:ef7eb2e8f9f7 3226 if((hi2c->XferSize == 0) && (hi2c->XferCount != 0))
<> 144:ef7eb2e8f9f7 3227 {
<> 144:ef7eb2e8f9f7 3228 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<> 144:ef7eb2e8f9f7 3229
<> 144:ef7eb2e8f9f7 3230 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 3231 {
<> 144:ef7eb2e8f9f7 3232 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 3233 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 3234 }
<> 144:ef7eb2e8f9f7 3235 else
<> 144:ef7eb2e8f9f7 3236 {
<> 144:ef7eb2e8f9f7 3237 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 3238 if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
<> 144:ef7eb2e8f9f7 3239 {
<> 144:ef7eb2e8f9f7 3240 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 3241 }
<> 144:ef7eb2e8f9f7 3242 else
<> 144:ef7eb2e8f9f7 3243 {
<> 144:ef7eb2e8f9f7 3244 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 3245 }
<> 144:ef7eb2e8f9f7 3246 }
<> 144:ef7eb2e8f9f7 3247 }
<> 144:ef7eb2e8f9f7 3248 else
<> 144:ef7eb2e8f9f7 3249 {
<> 144:ef7eb2e8f9f7 3250 /* Call TxCpltCallback() if no stop mode is set */
<> 144:ef7eb2e8f9f7 3251 if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
<> 144:ef7eb2e8f9f7 3252 {
<> 144:ef7eb2e8f9f7 3253 /* Call I2C Master Sequential complete process */
<> 144:ef7eb2e8f9f7 3254 I2C_ITMasterSequentialCplt(hi2c);
<> 144:ef7eb2e8f9f7 3255 }
<> 144:ef7eb2e8f9f7 3256 else
<> 144:ef7eb2e8f9f7 3257 {
<> 144:ef7eb2e8f9f7 3258 /* Wrong size Status regarding TCR flag event */
<> 144:ef7eb2e8f9f7 3259 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3260 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<> 144:ef7eb2e8f9f7 3261 }
<> 144:ef7eb2e8f9f7 3262 }
<> 144:ef7eb2e8f9f7 3263 }
<> 144:ef7eb2e8f9f7 3264 else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<> 144:ef7eb2e8f9f7 3265 {
<> 144:ef7eb2e8f9f7 3266 if(hi2c->XferCount == 0)
<> 144:ef7eb2e8f9f7 3267 {
<> 144:ef7eb2e8f9f7 3268 if((I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)&&(hi2c->Mode == HAL_I2C_MODE_MASTER))
<> 144:ef7eb2e8f9f7 3269 {
<> 144:ef7eb2e8f9f7 3270 /* Call I2C Master Sequential complete process */
<> 144:ef7eb2e8f9f7 3271 I2C_ITMasterSequentialCplt(hi2c);
<> 144:ef7eb2e8f9f7 3272 }
<> 144:ef7eb2e8f9f7 3273 }
<> 144:ef7eb2e8f9f7 3274 else
<> 144:ef7eb2e8f9f7 3275 {
<> 144:ef7eb2e8f9f7 3276 /* Wrong size Status regarding TC flag event */
<> 144:ef7eb2e8f9f7 3277 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3278 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<> 144:ef7eb2e8f9f7 3279 }
<> 144:ef7eb2e8f9f7 3280 }
<> 144:ef7eb2e8f9f7 3281
<> 144:ef7eb2e8f9f7 3282 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<> 144:ef7eb2e8f9f7 3283 {
<> 144:ef7eb2e8f9f7 3284 /* Call I2C Master complete process */
<> 144:ef7eb2e8f9f7 3285 I2C_ITMasterCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3286 }
<> 144:ef7eb2e8f9f7 3287
<> 144:ef7eb2e8f9f7 3288 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3289 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3290
<> 144:ef7eb2e8f9f7 3291 return HAL_OK;
<> 144:ef7eb2e8f9f7 3292 }
<> 144:ef7eb2e8f9f7 3293
<> 144:ef7eb2e8f9f7 3294 /**
<> 144:ef7eb2e8f9f7 3295 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
<> 144:ef7eb2e8f9f7 3296 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3297 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3298 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3299 * @param ITSources: Interrupt sources enabled.
<> 144:ef7eb2e8f9f7 3300 * @retval HAL status
<> 144:ef7eb2e8f9f7 3301 */
<> 144:ef7eb2e8f9f7 3302 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<> 144:ef7eb2e8f9f7 3303 {
<> 144:ef7eb2e8f9f7 3304 /* Process locked */
<> 144:ef7eb2e8f9f7 3305 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 3306
<> 144:ef7eb2e8f9f7 3307 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<> 144:ef7eb2e8f9f7 3308 {
<> 144:ef7eb2e8f9f7 3309 /* Check that I2C transfer finished */
<> 144:ef7eb2e8f9f7 3310 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
<> 144:ef7eb2e8f9f7 3311 /* Mean XferCount == 0*/
<> 144:ef7eb2e8f9f7 3312 /* So clear Flag NACKF only */
<> 144:ef7eb2e8f9f7 3313 if(hi2c->XferCount == 0)
<> 144:ef7eb2e8f9f7 3314 {
<> 144:ef7eb2e8f9f7 3315 if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
<> 144:ef7eb2e8f9f7 3316 (hi2c->State == HAL_I2C_STATE_LISTEN))
<> 144:ef7eb2e8f9f7 3317 {
<> 144:ef7eb2e8f9f7 3318 /* Call I2C Listen complete process */
<> 144:ef7eb2e8f9f7 3319 I2C_ITListenCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3320 }
<> 144:ef7eb2e8f9f7 3321 else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
<> 144:ef7eb2e8f9f7 3322 {
<> 144:ef7eb2e8f9f7 3323 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3324 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3325
<> 144:ef7eb2e8f9f7 3326 /* Flush TX register */
<> 144:ef7eb2e8f9f7 3327 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 3328
<> 144:ef7eb2e8f9f7 3329 /* Last Byte is Transmitted */
<> 144:ef7eb2e8f9f7 3330 /* Call I2C Slave Sequential complete process */
<> 144:ef7eb2e8f9f7 3331 I2C_ITSlaveSequentialCplt(hi2c);
<> 144:ef7eb2e8f9f7 3332 }
<> 144:ef7eb2e8f9f7 3333 else
<> 144:ef7eb2e8f9f7 3334 {
<> 144:ef7eb2e8f9f7 3335 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3336 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3337 }
<> 144:ef7eb2e8f9f7 3338 }
<> 144:ef7eb2e8f9f7 3339 else
<> 144:ef7eb2e8f9f7 3340 {
<> 144:ef7eb2e8f9f7 3341 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
<> 144:ef7eb2e8f9f7 3342 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3343 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3344
<> 144:ef7eb2e8f9f7 3345 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 3346 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3347 }
<> 144:ef7eb2e8f9f7 3348 }
<> 144:ef7eb2e8f9f7 3349 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
<> 144:ef7eb2e8f9f7 3350 {
<> 144:ef7eb2e8f9f7 3351 if(hi2c->XferCount > 0)
<> 144:ef7eb2e8f9f7 3352 {
<> 144:ef7eb2e8f9f7 3353 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 3354 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 3355 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 3356 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 3357 }
<> 144:ef7eb2e8f9f7 3358
<> 144:ef7eb2e8f9f7 3359 if((hi2c->XferCount == 0) && \
<> 144:ef7eb2e8f9f7 3360 (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
<> 144:ef7eb2e8f9f7 3361 {
<> 144:ef7eb2e8f9f7 3362 /* Call I2C Slave Sequential complete process */
<> 144:ef7eb2e8f9f7 3363 I2C_ITSlaveSequentialCplt(hi2c);
<> 144:ef7eb2e8f9f7 3364 }
<> 144:ef7eb2e8f9f7 3365 }
<> 144:ef7eb2e8f9f7 3366 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
<> 144:ef7eb2e8f9f7 3367 {
<> 144:ef7eb2e8f9f7 3368 I2C_ITAddrCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3369 }
<> 144:ef7eb2e8f9f7 3370 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
<> 144:ef7eb2e8f9f7 3371 {
<> 144:ef7eb2e8f9f7 3372 /* Write data to TXDR only if XferCount not reach "0" */
<> 144:ef7eb2e8f9f7 3373 /* A TXIS flag can be set, during STOP treatment */
<> 144:ef7eb2e8f9f7 3374 /* Check if all Datas have already been sent */
<> 144:ef7eb2e8f9f7 3375 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
<> 144:ef7eb2e8f9f7 3376 if(hi2c->XferCount > 0)
<> 144:ef7eb2e8f9f7 3377 {
<> 144:ef7eb2e8f9f7 3378 /* Write data to TXDR */
<> 144:ef7eb2e8f9f7 3379 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
<> 144:ef7eb2e8f9f7 3380 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 3381 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 3382 }
<> 144:ef7eb2e8f9f7 3383 else
<> 144:ef7eb2e8f9f7 3384 {
<> 144:ef7eb2e8f9f7 3385 if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
<> 144:ef7eb2e8f9f7 3386 {
<> 144:ef7eb2e8f9f7 3387 /* Last Byte is Transmitted */
<> 144:ef7eb2e8f9f7 3388 /* Call I2C Slave Sequential complete process */
<> 144:ef7eb2e8f9f7 3389 I2C_ITSlaveSequentialCplt(hi2c);
<> 144:ef7eb2e8f9f7 3390 }
<> 144:ef7eb2e8f9f7 3391 }
<> 144:ef7eb2e8f9f7 3392 }
<> 144:ef7eb2e8f9f7 3393
<> 144:ef7eb2e8f9f7 3394 /* Check if STOPF is set */
<> 144:ef7eb2e8f9f7 3395 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<> 144:ef7eb2e8f9f7 3396 {
<> 144:ef7eb2e8f9f7 3397 /* Call I2C Slave complete process */
<> 144:ef7eb2e8f9f7 3398 I2C_ITSlaveCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3399 }
<> 144:ef7eb2e8f9f7 3400
<> 144:ef7eb2e8f9f7 3401 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3402 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3403
<> 144:ef7eb2e8f9f7 3404 return HAL_OK;
<> 144:ef7eb2e8f9f7 3405 }
<> 144:ef7eb2e8f9f7 3406
<> 144:ef7eb2e8f9f7 3407 /**
<> 144:ef7eb2e8f9f7 3408 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
<> 144:ef7eb2e8f9f7 3409 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3410 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3411 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3412 * @param ITSources: Interrupt sources enabled.
<> 144:ef7eb2e8f9f7 3413 * @retval HAL status
<> 144:ef7eb2e8f9f7 3414 */
<> 144:ef7eb2e8f9f7 3415 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<> 144:ef7eb2e8f9f7 3416 {
<> 144:ef7eb2e8f9f7 3417 uint16_t devaddress = 0;
<> 144:ef7eb2e8f9f7 3418 uint32_t xfermode = 0;
<> 144:ef7eb2e8f9f7 3419
<> 144:ef7eb2e8f9f7 3420 /* Process Locked */
<> 144:ef7eb2e8f9f7 3421 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 3422
<> 144:ef7eb2e8f9f7 3423 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<> 144:ef7eb2e8f9f7 3424 {
<> 144:ef7eb2e8f9f7 3425 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3426 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3427
<> 144:ef7eb2e8f9f7 3428 /* Set corresponding Error Code */
<> 144:ef7eb2e8f9f7 3429 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3430
<> 144:ef7eb2e8f9f7 3431 /* No need to generate STOP, it is automatically done */
<> 144:ef7eb2e8f9f7 3432 /* But enable STOP interrupt, to treat it */
<> 144:ef7eb2e8f9f7 3433 /* Error callback will be send during stop flag treatment */
<> 144:ef7eb2e8f9f7 3434 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<> 144:ef7eb2e8f9f7 3435
<> 144:ef7eb2e8f9f7 3436 /* Flush TX register */
<> 144:ef7eb2e8f9f7 3437 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 3438 }
<> 144:ef7eb2e8f9f7 3439 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
<> 144:ef7eb2e8f9f7 3440 {
<> 144:ef7eb2e8f9f7 3441 /* Disable TC interrupt */
<> 144:ef7eb2e8f9f7 3442 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
<> 144:ef7eb2e8f9f7 3443
<> 144:ef7eb2e8f9f7 3444 if(hi2c->XferCount != 0)
<> 144:ef7eb2e8f9f7 3445 {
<> 144:ef7eb2e8f9f7 3446 /* Recover Slave address */
<> 144:ef7eb2e8f9f7 3447 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
<> 144:ef7eb2e8f9f7 3448
<> 144:ef7eb2e8f9f7 3449 /* Prepare the new XferSize to transfer */
<> 144:ef7eb2e8f9f7 3450 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 3451 {
<> 144:ef7eb2e8f9f7 3452 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 3453 xfermode = I2C_RELOAD_MODE;
<> 144:ef7eb2e8f9f7 3454 }
<> 144:ef7eb2e8f9f7 3455 else
<> 144:ef7eb2e8f9f7 3456 {
<> 144:ef7eb2e8f9f7 3457 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 3458 xfermode = I2C_AUTOEND_MODE;
<> 144:ef7eb2e8f9f7 3459 }
<> 144:ef7eb2e8f9f7 3460
<> 144:ef7eb2e8f9f7 3461 /* Set the new XferSize in Nbytes register */
<> 144:ef7eb2e8f9f7 3462 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
<> 144:ef7eb2e8f9f7 3463
<> 144:ef7eb2e8f9f7 3464 /* Update XferCount value */
<> 144:ef7eb2e8f9f7 3465 hi2c->XferCount -= hi2c->XferSize;
<> 144:ef7eb2e8f9f7 3466
<> 144:ef7eb2e8f9f7 3467 /* Enable DMA Request */
<> 144:ef7eb2e8f9f7 3468 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3469 {
<> 144:ef7eb2e8f9f7 3470 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 3471 }
<> 144:ef7eb2e8f9f7 3472 else
<> 144:ef7eb2e8f9f7 3473 {
<> 144:ef7eb2e8f9f7 3474 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 3475 }
<> 144:ef7eb2e8f9f7 3476 }
<> 144:ef7eb2e8f9f7 3477 else
<> 144:ef7eb2e8f9f7 3478 {
<> 144:ef7eb2e8f9f7 3479 /* Wrong size Status regarding TCR flag event */
<> 144:ef7eb2e8f9f7 3480 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3481 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
<> 144:ef7eb2e8f9f7 3482 }
<> 144:ef7eb2e8f9f7 3483 }
<> 144:ef7eb2e8f9f7 3484 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<> 144:ef7eb2e8f9f7 3485 {
<> 144:ef7eb2e8f9f7 3486 /* Call I2C Master complete process */
<> 144:ef7eb2e8f9f7 3487 I2C_ITMasterCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3488 }
<> 144:ef7eb2e8f9f7 3489
<> 144:ef7eb2e8f9f7 3490 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3491 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3492
<> 144:ef7eb2e8f9f7 3493 return HAL_OK;
<> 144:ef7eb2e8f9f7 3494 }
<> 144:ef7eb2e8f9f7 3495
<> 144:ef7eb2e8f9f7 3496 /**
<> 144:ef7eb2e8f9f7 3497 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
<> 144:ef7eb2e8f9f7 3498 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3499 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3500 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3501 * @param ITSources: Interrupt sources enabled.
<> 144:ef7eb2e8f9f7 3502 * @retval HAL status
<> 144:ef7eb2e8f9f7 3503 */
<> 144:ef7eb2e8f9f7 3504 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
<> 144:ef7eb2e8f9f7 3505 {
<> 144:ef7eb2e8f9f7 3506 /* Process locked */
<> 144:ef7eb2e8f9f7 3507 __HAL_LOCK(hi2c);
<> 144:ef7eb2e8f9f7 3508
<> 144:ef7eb2e8f9f7 3509 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
<> 144:ef7eb2e8f9f7 3510 {
<> 144:ef7eb2e8f9f7 3511 /* Check that I2C transfer finished */
<> 144:ef7eb2e8f9f7 3512 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
<> 144:ef7eb2e8f9f7 3513 /* Mean XferCount == 0 */
<> 144:ef7eb2e8f9f7 3514 /* So clear Flag NACKF only */
<> 144:ef7eb2e8f9f7 3515 if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0)
<> 144:ef7eb2e8f9f7 3516 {
<> 144:ef7eb2e8f9f7 3517 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3518 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3519 }
<> 144:ef7eb2e8f9f7 3520 else
<> 144:ef7eb2e8f9f7 3521 {
<> 144:ef7eb2e8f9f7 3522 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
<> 144:ef7eb2e8f9f7 3523 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3524 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3525
<> 144:ef7eb2e8f9f7 3526 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 3527 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3528 }
<> 144:ef7eb2e8f9f7 3529 }
<> 144:ef7eb2e8f9f7 3530 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
<> 144:ef7eb2e8f9f7 3531 {
<> 144:ef7eb2e8f9f7 3532 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 3533 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 3534 }
<> 144:ef7eb2e8f9f7 3535 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
<> 144:ef7eb2e8f9f7 3536 {
<> 144:ef7eb2e8f9f7 3537 /* Call I2C Slave complete process */
<> 144:ef7eb2e8f9f7 3538 I2C_ITSlaveCplt(hi2c, ITFlags);
<> 144:ef7eb2e8f9f7 3539 }
<> 144:ef7eb2e8f9f7 3540
<> 144:ef7eb2e8f9f7 3541 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3542 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3543
<> 144:ef7eb2e8f9f7 3544 return HAL_OK;
<> 144:ef7eb2e8f9f7 3545 }
<> 144:ef7eb2e8f9f7 3546
<> 144:ef7eb2e8f9f7 3547 /**
<> 144:ef7eb2e8f9f7 3548 * @brief Master sends target device address followed by internal memory address for write request.
<> 144:ef7eb2e8f9f7 3549 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3550 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3551 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 3552 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 3553 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 3554 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 3555 * @param Tickstart Tick start value
<> 144:ef7eb2e8f9f7 3556 * @retval HAL status
<> 144:ef7eb2e8f9f7 3557 */
<> 144:ef7eb2e8f9f7 3558 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3559 {
<> 144:ef7eb2e8f9f7 3560 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 3561
<> 144:ef7eb2e8f9f7 3562 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 3563 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3564 {
<> 144:ef7eb2e8f9f7 3565 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 3566 {
<> 144:ef7eb2e8f9f7 3567 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3568 }
<> 144:ef7eb2e8f9f7 3569 else
<> 144:ef7eb2e8f9f7 3570 {
<> 144:ef7eb2e8f9f7 3571 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3572 }
<> 144:ef7eb2e8f9f7 3573 }
<> 144:ef7eb2e8f9f7 3574
<> 144:ef7eb2e8f9f7 3575 /* If Memory address size is 8Bit */
<> 144:ef7eb2e8f9f7 3576 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<> 144:ef7eb2e8f9f7 3577 {
<> 144:ef7eb2e8f9f7 3578 /* Send Memory Address */
<> 144:ef7eb2e8f9f7 3579 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<> 144:ef7eb2e8f9f7 3580 }
<> 144:ef7eb2e8f9f7 3581 /* If Memory address size is 16Bit */
<> 144:ef7eb2e8f9f7 3582 else
<> 144:ef7eb2e8f9f7 3583 {
<> 144:ef7eb2e8f9f7 3584 /* Send MSB of Memory Address */
<> 144:ef7eb2e8f9f7 3585 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
<> 144:ef7eb2e8f9f7 3586
<> 144:ef7eb2e8f9f7 3587 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 3588 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3589 {
<> 144:ef7eb2e8f9f7 3590 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 3591 {
<> 144:ef7eb2e8f9f7 3592 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3593 }
<> 144:ef7eb2e8f9f7 3594 else
<> 144:ef7eb2e8f9f7 3595 {
<> 144:ef7eb2e8f9f7 3596 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3597 }
<> 144:ef7eb2e8f9f7 3598 }
<> 144:ef7eb2e8f9f7 3599
<> 144:ef7eb2e8f9f7 3600 /* Send LSB of Memory Address */
<> 144:ef7eb2e8f9f7 3601 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<> 144:ef7eb2e8f9f7 3602 }
<> 144:ef7eb2e8f9f7 3603
<> 144:ef7eb2e8f9f7 3604 /* Wait until TCR flag is set */
<> 144:ef7eb2e8f9f7 3605 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3606 {
<> 144:ef7eb2e8f9f7 3607 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3608 }
<> 144:ef7eb2e8f9f7 3609
<> 144:ef7eb2e8f9f7 3610 return HAL_OK;
<> 144:ef7eb2e8f9f7 3611 }
<> 144:ef7eb2e8f9f7 3612
<> 144:ef7eb2e8f9f7 3613 /**
<> 144:ef7eb2e8f9f7 3614 * @brief Master sends target device address followed by internal memory address for read request.
<> 144:ef7eb2e8f9f7 3615 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3616 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 3617 * @param DevAddress: Target device address
<> 144:ef7eb2e8f9f7 3618 * @param MemAddress: Internal memory address
<> 144:ef7eb2e8f9f7 3619 * @param MemAddSize: Size of internal memory address
<> 144:ef7eb2e8f9f7 3620 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 3621 * @param Tickstart Tick start value
<> 144:ef7eb2e8f9f7 3622 * @retval HAL status
<> 144:ef7eb2e8f9f7 3623 */
<> 144:ef7eb2e8f9f7 3624 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 3625 {
<> 144:ef7eb2e8f9f7 3626 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
<> 144:ef7eb2e8f9f7 3627
<> 144:ef7eb2e8f9f7 3628 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 3629 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3630 {
<> 144:ef7eb2e8f9f7 3631 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 3632 {
<> 144:ef7eb2e8f9f7 3633 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3634 }
<> 144:ef7eb2e8f9f7 3635 else
<> 144:ef7eb2e8f9f7 3636 {
<> 144:ef7eb2e8f9f7 3637 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3638 }
<> 144:ef7eb2e8f9f7 3639 }
<> 144:ef7eb2e8f9f7 3640
<> 144:ef7eb2e8f9f7 3641 /* If Memory address size is 8Bit */
<> 144:ef7eb2e8f9f7 3642 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<> 144:ef7eb2e8f9f7 3643 {
<> 144:ef7eb2e8f9f7 3644 /* Send Memory Address */
<> 144:ef7eb2e8f9f7 3645 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<> 144:ef7eb2e8f9f7 3646 }
<> 144:ef7eb2e8f9f7 3647 /* If Memory address size is 16Bit */
<> 144:ef7eb2e8f9f7 3648 else
<> 144:ef7eb2e8f9f7 3649 {
<> 144:ef7eb2e8f9f7 3650 /* Send MSB of Memory Address */
<> 144:ef7eb2e8f9f7 3651 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
<> 144:ef7eb2e8f9f7 3652
<> 144:ef7eb2e8f9f7 3653 /* Wait until TXIS flag is set */
<> 144:ef7eb2e8f9f7 3654 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3655 {
<> 144:ef7eb2e8f9f7 3656 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<> 144:ef7eb2e8f9f7 3657 {
<> 144:ef7eb2e8f9f7 3658 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3659 }
<> 144:ef7eb2e8f9f7 3660 else
<> 144:ef7eb2e8f9f7 3661 {
<> 144:ef7eb2e8f9f7 3662 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3663 }
<> 144:ef7eb2e8f9f7 3664 }
<> 144:ef7eb2e8f9f7 3665
<> 144:ef7eb2e8f9f7 3666 /* Send LSB of Memory Address */
<> 144:ef7eb2e8f9f7 3667 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
<> 144:ef7eb2e8f9f7 3668 }
<> 144:ef7eb2e8f9f7 3669
<> 144:ef7eb2e8f9f7 3670 /* Wait until TC flag is set */
<> 144:ef7eb2e8f9f7 3671 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 3672 {
<> 144:ef7eb2e8f9f7 3673 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 3674 }
<> 144:ef7eb2e8f9f7 3675
<> 144:ef7eb2e8f9f7 3676 return HAL_OK;
<> 144:ef7eb2e8f9f7 3677 }
<> 144:ef7eb2e8f9f7 3678
<> 144:ef7eb2e8f9f7 3679 /**
<> 144:ef7eb2e8f9f7 3680 * @brief I2C Address complete process callback.
<> 144:ef7eb2e8f9f7 3681 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 3682 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3683 * @retval None
<> 144:ef7eb2e8f9f7 3684 */
<> 144:ef7eb2e8f9f7 3685 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<> 144:ef7eb2e8f9f7 3686 {
<> 144:ef7eb2e8f9f7 3687 uint8_t transferdirection = 0;
<> 144:ef7eb2e8f9f7 3688 uint16_t slaveaddrcode = 0;
<> 144:ef7eb2e8f9f7 3689 uint16_t ownadd1code = 0;
<> 144:ef7eb2e8f9f7 3690 uint16_t ownadd2code = 0;
<> 144:ef7eb2e8f9f7 3691
<> 144:ef7eb2e8f9f7 3692 /* In case of Listen state, need to inform upper layer of address match code event */
<> 144:ef7eb2e8f9f7 3693 if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 3694 {
<> 144:ef7eb2e8f9f7 3695 transferdirection = I2C_GET_DIR(hi2c);
<> 144:ef7eb2e8f9f7 3696 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
<> 144:ef7eb2e8f9f7 3697 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
<> 144:ef7eb2e8f9f7 3698 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
<> 144:ef7eb2e8f9f7 3699
<> 144:ef7eb2e8f9f7 3700 /* If 10bits addressing mode is selected */
<> 144:ef7eb2e8f9f7 3701 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<> 144:ef7eb2e8f9f7 3702 {
<> 144:ef7eb2e8f9f7 3703 if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
<> 144:ef7eb2e8f9f7 3704 {
<> 144:ef7eb2e8f9f7 3705 slaveaddrcode = ownadd1code;
<> 144:ef7eb2e8f9f7 3706 hi2c->AddrEventCount++;
<> 144:ef7eb2e8f9f7 3707 if(hi2c->AddrEventCount == 2)
<> 144:ef7eb2e8f9f7 3708 {
<> 144:ef7eb2e8f9f7 3709 /* Reset Address Event counter */
<> 144:ef7eb2e8f9f7 3710 hi2c->AddrEventCount = 0;
<> 144:ef7eb2e8f9f7 3711
<> 144:ef7eb2e8f9f7 3712 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 3713 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 3714
<> 144:ef7eb2e8f9f7 3715 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3716 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3717
<> 144:ef7eb2e8f9f7 3718 /* Call Slave Addr callback */
<> 144:ef7eb2e8f9f7 3719 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<> 144:ef7eb2e8f9f7 3720 }
<> 144:ef7eb2e8f9f7 3721 }
<> 144:ef7eb2e8f9f7 3722 else
<> 144:ef7eb2e8f9f7 3723 {
<> 144:ef7eb2e8f9f7 3724 slaveaddrcode = ownadd2code;
<> 144:ef7eb2e8f9f7 3725
<> 144:ef7eb2e8f9f7 3726 /* Disable ADDR Interrupts */
<> 144:ef7eb2e8f9f7 3727 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 3728
<> 144:ef7eb2e8f9f7 3729 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3730 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3731
<> 144:ef7eb2e8f9f7 3732 /* Call Slave Addr callback */
<> 144:ef7eb2e8f9f7 3733 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<> 144:ef7eb2e8f9f7 3734 }
<> 144:ef7eb2e8f9f7 3735 }
<> 144:ef7eb2e8f9f7 3736 /* else 7 bits addressing mode is selected */
<> 144:ef7eb2e8f9f7 3737 else
<> 144:ef7eb2e8f9f7 3738 {
<> 144:ef7eb2e8f9f7 3739 /* Disable ADDR Interrupts */
<> 144:ef7eb2e8f9f7 3740 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
<> 144:ef7eb2e8f9f7 3741
<> 144:ef7eb2e8f9f7 3742 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3743 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3744
<> 144:ef7eb2e8f9f7 3745 /* Call Slave Addr callback */
<> 144:ef7eb2e8f9f7 3746 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
<> 144:ef7eb2e8f9f7 3747 }
<> 144:ef7eb2e8f9f7 3748 }
<> 144:ef7eb2e8f9f7 3749 /* Else clear address flag only */
<> 144:ef7eb2e8f9f7 3750 else
<> 144:ef7eb2e8f9f7 3751 {
<> 144:ef7eb2e8f9f7 3752 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 3753 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 3754
<> 144:ef7eb2e8f9f7 3755 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3756 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3757 }
<> 144:ef7eb2e8f9f7 3758 }
<> 144:ef7eb2e8f9f7 3759
<> 144:ef7eb2e8f9f7 3760 /**
<> 144:ef7eb2e8f9f7 3761 * @brief I2C Master sequential complete process.
<> 144:ef7eb2e8f9f7 3762 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 3763 * @retval None
<> 144:ef7eb2e8f9f7 3764 */
<> 144:ef7eb2e8f9f7 3765 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3766 {
<> 144:ef7eb2e8f9f7 3767 /* Reset I2C handle mode */
<> 144:ef7eb2e8f9f7 3768 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3769
<> 144:ef7eb2e8f9f7 3770 /* No Generate Stop, to permit restart mode */
<> 144:ef7eb2e8f9f7 3771 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
<> 144:ef7eb2e8f9f7 3772 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 3773 {
<> 144:ef7eb2e8f9f7 3774 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 3775 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<> 144:ef7eb2e8f9f7 3776 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 3777
<> 144:ef7eb2e8f9f7 3778 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 3779 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 3780
<> 144:ef7eb2e8f9f7 3781 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3782 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3783
<> 144:ef7eb2e8f9f7 3784 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3785 HAL_I2C_MasterTxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3786 }
<> 144:ef7eb2e8f9f7 3787 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 3788 else
<> 144:ef7eb2e8f9f7 3789 {
<> 144:ef7eb2e8f9f7 3790 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 3791 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<> 144:ef7eb2e8f9f7 3792 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 3793
<> 144:ef7eb2e8f9f7 3794 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 3795 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 3796
<> 144:ef7eb2e8f9f7 3797 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3798 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3799
<> 144:ef7eb2e8f9f7 3800 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3801 HAL_I2C_MasterRxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3802 }
<> 144:ef7eb2e8f9f7 3803 }
<> 144:ef7eb2e8f9f7 3804
<> 144:ef7eb2e8f9f7 3805 /**
<> 144:ef7eb2e8f9f7 3806 * @brief I2C Slave sequential complete process.
<> 144:ef7eb2e8f9f7 3807 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 3808 * @retval None
<> 144:ef7eb2e8f9f7 3809 */
<> 144:ef7eb2e8f9f7 3810 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 3811 {
<> 144:ef7eb2e8f9f7 3812 /* Reset I2C handle mode */
<> 144:ef7eb2e8f9f7 3813 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3814
<> 144:ef7eb2e8f9f7 3815 if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
<> 144:ef7eb2e8f9f7 3816 {
<> 144:ef7eb2e8f9f7 3817 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 3818 hi2c->State = HAL_I2C_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 3819 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<> 144:ef7eb2e8f9f7 3820
<> 144:ef7eb2e8f9f7 3821 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 3822 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 3823
<> 144:ef7eb2e8f9f7 3824 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3825 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3826
<> 144:ef7eb2e8f9f7 3827 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
<> 144:ef7eb2e8f9f7 3828 HAL_I2C_SlaveTxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3829 }
<> 144:ef7eb2e8f9f7 3830
<> 144:ef7eb2e8f9f7 3831 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
<> 144:ef7eb2e8f9f7 3832 {
<> 144:ef7eb2e8f9f7 3833 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
<> 144:ef7eb2e8f9f7 3834 hi2c->State = HAL_I2C_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 3835 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
<> 144:ef7eb2e8f9f7 3836
<> 144:ef7eb2e8f9f7 3837 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 3838 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 3839
<> 144:ef7eb2e8f9f7 3840 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3841 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3842
<> 144:ef7eb2e8f9f7 3843 /* Call the Rx complete callback to inform upper layer of the end of receive process */
<> 144:ef7eb2e8f9f7 3844 HAL_I2C_SlaveRxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3845 }
<> 144:ef7eb2e8f9f7 3846 }
<> 144:ef7eb2e8f9f7 3847
<> 144:ef7eb2e8f9f7 3848 /**
<> 144:ef7eb2e8f9f7 3849 * @brief I2C Master complete process.
<> 144:ef7eb2e8f9f7 3850 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 3851 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3852 * @retval None
<> 144:ef7eb2e8f9f7 3853 */
<> 144:ef7eb2e8f9f7 3854 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<> 144:ef7eb2e8f9f7 3855 {
<> 144:ef7eb2e8f9f7 3856 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 3857 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 3858
<> 144:ef7eb2e8f9f7 3859 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 3860 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 3861
<> 144:ef7eb2e8f9f7 3862 /* Reset handle parameters */
<> 144:ef7eb2e8f9f7 3863 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 3864 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 3865 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 3866
<> 144:ef7eb2e8f9f7 3867 if((ITFlags & I2C_FLAG_AF) != RESET)
<> 144:ef7eb2e8f9f7 3868 {
<> 144:ef7eb2e8f9f7 3869 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 3870 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 3871
<> 144:ef7eb2e8f9f7 3872 /* Set acknowledge error code */
<> 144:ef7eb2e8f9f7 3873 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3874 }
<> 144:ef7eb2e8f9f7 3875
<> 144:ef7eb2e8f9f7 3876 /* Flush TX register */
<> 144:ef7eb2e8f9f7 3877 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 3878
<> 144:ef7eb2e8f9f7 3879 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 3880 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 3881
<> 144:ef7eb2e8f9f7 3882 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3883 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<> 144:ef7eb2e8f9f7 3884 {
<> 144:ef7eb2e8f9f7 3885 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3886 I2C_ITError(hi2c, hi2c->ErrorCode);
<> 144:ef7eb2e8f9f7 3887 }
<> 144:ef7eb2e8f9f7 3888 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
<> 144:ef7eb2e8f9f7 3889 else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 3890 {
<> 144:ef7eb2e8f9f7 3891 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 3892
<> 144:ef7eb2e8f9f7 3893 if (hi2c->Mode == HAL_I2C_MODE_MEM)
<> 144:ef7eb2e8f9f7 3894 {
<> 144:ef7eb2e8f9f7 3895 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3896
<> 144:ef7eb2e8f9f7 3897 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3898 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3899
<> 144:ef7eb2e8f9f7 3900 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3901 HAL_I2C_MemTxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3902 }
<> 144:ef7eb2e8f9f7 3903 else
<> 144:ef7eb2e8f9f7 3904 {
<> 144:ef7eb2e8f9f7 3905 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3906
<> 144:ef7eb2e8f9f7 3907 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3908 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3909
<> 144:ef7eb2e8f9f7 3910 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 3911 HAL_I2C_MasterTxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3912 }
<> 144:ef7eb2e8f9f7 3913 }
<> 144:ef7eb2e8f9f7 3914 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
<> 144:ef7eb2e8f9f7 3915 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 3916 {
<> 144:ef7eb2e8f9f7 3917 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 3918
<> 144:ef7eb2e8f9f7 3919 if (hi2c->Mode == HAL_I2C_MODE_MEM)
<> 144:ef7eb2e8f9f7 3920 {
<> 144:ef7eb2e8f9f7 3921 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3922
<> 144:ef7eb2e8f9f7 3923 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3924 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926 HAL_I2C_MemRxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3927 }
<> 144:ef7eb2e8f9f7 3928 else
<> 144:ef7eb2e8f9f7 3929 {
<> 144:ef7eb2e8f9f7 3930 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3931
<> 144:ef7eb2e8f9f7 3932 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 3933 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 3934
<> 144:ef7eb2e8f9f7 3935 HAL_I2C_MasterRxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 3936 }
<> 144:ef7eb2e8f9f7 3937 }
<> 144:ef7eb2e8f9f7 3938 }
<> 144:ef7eb2e8f9f7 3939
<> 144:ef7eb2e8f9f7 3940 /**
<> 144:ef7eb2e8f9f7 3941 * @brief I2C Slave complete process.
<> 144:ef7eb2e8f9f7 3942 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 3943 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 3944 * @retval None
<> 144:ef7eb2e8f9f7 3945 */
<> 144:ef7eb2e8f9f7 3946 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<> 144:ef7eb2e8f9f7 3947 {
<> 144:ef7eb2e8f9f7 3948 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 3949 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 3950
<> 144:ef7eb2e8f9f7 3951 /* Clear ADDR flag */
<> 144:ef7eb2e8f9f7 3952 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
<> 144:ef7eb2e8f9f7 3953
<> 144:ef7eb2e8f9f7 3954 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 3955 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957 /* Disable Address Acknowledge */
<> 144:ef7eb2e8f9f7 3958 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 3959
<> 144:ef7eb2e8f9f7 3960 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 3961 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 3962
<> 144:ef7eb2e8f9f7 3963 /* Flush TX register */
<> 144:ef7eb2e8f9f7 3964 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 3965
<> 144:ef7eb2e8f9f7 3966 /* If a DMA is ongoing, Update handle size context */
<> 144:ef7eb2e8f9f7 3967 if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
<> 144:ef7eb2e8f9f7 3968 ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
<> 144:ef7eb2e8f9f7 3969 {
<> 144:ef7eb2e8f9f7 3970 if((hi2c->XferSize - I2C_GET_DMA_REMAIN_DATA(hi2c)) != hi2c->XferSize)
<> 144:ef7eb2e8f9f7 3971 {
<> 144:ef7eb2e8f9f7 3972 hi2c->XferSize = I2C_GET_DMA_REMAIN_DATA(hi2c);
<> 144:ef7eb2e8f9f7 3973 hi2c->XferCount += hi2c->XferSize;
<> 144:ef7eb2e8f9f7 3974
<> 144:ef7eb2e8f9f7 3975 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 3976 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3977 }
<> 144:ef7eb2e8f9f7 3978 }
<> 144:ef7eb2e8f9f7 3979
<> 144:ef7eb2e8f9f7 3980 /* Store Last receive data if any */
<> 144:ef7eb2e8f9f7 3981 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 3982 {
<> 144:ef7eb2e8f9f7 3983 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 3984 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 3985
<> 144:ef7eb2e8f9f7 3986 if((hi2c->XferSize > 0))
<> 144:ef7eb2e8f9f7 3987 {
<> 144:ef7eb2e8f9f7 3988 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 3989 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 3990
<> 144:ef7eb2e8f9f7 3991 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 3992 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 3993 }
<> 144:ef7eb2e8f9f7 3994 }
<> 144:ef7eb2e8f9f7 3995
<> 144:ef7eb2e8f9f7 3996 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 3997 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 3998 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 3999
<> 144:ef7eb2e8f9f7 4000 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<> 144:ef7eb2e8f9f7 4001 {
<> 144:ef7eb2e8f9f7 4002 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 4003 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4004
<> 144:ef7eb2e8f9f7 4005 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4006 I2C_ITError(hi2c, hi2c->ErrorCode);
<> 144:ef7eb2e8f9f7 4007 }
<> 144:ef7eb2e8f9f7 4008 else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
<> 144:ef7eb2e8f9f7 4009 {
<> 144:ef7eb2e8f9f7 4010 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 4011 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4012
<> 144:ef7eb2e8f9f7 4013 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4014 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4015
<> 144:ef7eb2e8f9f7 4016 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<> 144:ef7eb2e8f9f7 4017 HAL_I2C_ListenCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4018 }
<> 144:ef7eb2e8f9f7 4019 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4020 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 4021 {
<> 144:ef7eb2e8f9f7 4022 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4023
<> 144:ef7eb2e8f9f7 4024 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4025 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4026
<> 144:ef7eb2e8f9f7 4027 /* Call the Slave Rx Complete callback */
<> 144:ef7eb2e8f9f7 4028 HAL_I2C_SlaveRxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4029 }
<> 144:ef7eb2e8f9f7 4030 else
<> 144:ef7eb2e8f9f7 4031 {
<> 144:ef7eb2e8f9f7 4032 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4033
<> 144:ef7eb2e8f9f7 4034 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4035 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4036
<> 144:ef7eb2e8f9f7 4037 /* Call the Slave Tx Complete callback */
<> 144:ef7eb2e8f9f7 4038 HAL_I2C_SlaveTxCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4039 }
<> 144:ef7eb2e8f9f7 4040 }
<> 144:ef7eb2e8f9f7 4041
<> 144:ef7eb2e8f9f7 4042 /**
<> 144:ef7eb2e8f9f7 4043 * @brief I2C Listen complete process.
<> 144:ef7eb2e8f9f7 4044 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 4045 * @param ITFlags: Interrupt flags to handle.
<> 144:ef7eb2e8f9f7 4046 * @retval None
<> 144:ef7eb2e8f9f7 4047 */
<> 144:ef7eb2e8f9f7 4048 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
<> 144:ef7eb2e8f9f7 4049 {
<> 144:ef7eb2e8f9f7 4050 /* Reset handle parameters */
<> 144:ef7eb2e8f9f7 4051 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 4052 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 4053 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4054 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4055 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 4056
<> 144:ef7eb2e8f9f7 4057 /* Store Last receive data if any */
<> 144:ef7eb2e8f9f7 4058 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 4059 {
<> 144:ef7eb2e8f9f7 4060 /* Read data from RXDR */
<> 144:ef7eb2e8f9f7 4061 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
<> 144:ef7eb2e8f9f7 4062
<> 144:ef7eb2e8f9f7 4063 if((hi2c->XferSize > 0))
<> 144:ef7eb2e8f9f7 4064 {
<> 144:ef7eb2e8f9f7 4065 hi2c->XferSize--;
<> 144:ef7eb2e8f9f7 4066 hi2c->XferCount--;
<> 144:ef7eb2e8f9f7 4067
<> 144:ef7eb2e8f9f7 4068 /* Set ErrorCode corresponding to a Non-Acknowledge */
<> 144:ef7eb2e8f9f7 4069 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 4070 }
<> 144:ef7eb2e8f9f7 4071 }
<> 144:ef7eb2e8f9f7 4072
<> 144:ef7eb2e8f9f7 4073 /* Disable all Interrupts*/
<> 144:ef7eb2e8f9f7 4074 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 4075
<> 144:ef7eb2e8f9f7 4076 /* Clear NACK Flag */
<> 144:ef7eb2e8f9f7 4077 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 4078
<> 144:ef7eb2e8f9f7 4079 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4080 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4081
<> 144:ef7eb2e8f9f7 4082 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<> 144:ef7eb2e8f9f7 4083 HAL_I2C_ListenCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4084 }
<> 144:ef7eb2e8f9f7 4085
<> 144:ef7eb2e8f9f7 4086 /**
<> 144:ef7eb2e8f9f7 4087 * @brief I2C interrupts error process.
<> 144:ef7eb2e8f9f7 4088 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 4089 * @param ErrorCode: Error code to handle.
<> 144:ef7eb2e8f9f7 4090 * @retval None
<> 144:ef7eb2e8f9f7 4091 */
<> 144:ef7eb2e8f9f7 4092 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
<> 144:ef7eb2e8f9f7 4093 {
<> 144:ef7eb2e8f9f7 4094 /* Reset handle parameters */
<> 144:ef7eb2e8f9f7 4095 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4096 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<> 144:ef7eb2e8f9f7 4097 hi2c->XferCount = 0;
<> 144:ef7eb2e8f9f7 4098
<> 144:ef7eb2e8f9f7 4099 /* Set new error code */
<> 144:ef7eb2e8f9f7 4100 hi2c->ErrorCode |= ErrorCode;
<> 144:ef7eb2e8f9f7 4101
<> 144:ef7eb2e8f9f7 4102 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 4103 if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
<> 144:ef7eb2e8f9f7 4104 (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
<> 144:ef7eb2e8f9f7 4105 (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
<> 144:ef7eb2e8f9f7 4106 {
<> 144:ef7eb2e8f9f7 4107 /* Disable all interrupts, except interrupts related to LISTEN state */
<> 144:ef7eb2e8f9f7 4108 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 4109
<> 144:ef7eb2e8f9f7 4110 /* keep HAL_I2C_STATE_LISTEN if set */
<> 144:ef7eb2e8f9f7 4111 hi2c->State = HAL_I2C_STATE_LISTEN;
<> 144:ef7eb2e8f9f7 4112 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 4113 hi2c->XferISR = I2C_Slave_ISR_IT;
<> 144:ef7eb2e8f9f7 4114 }
<> 144:ef7eb2e8f9f7 4115 else
<> 144:ef7eb2e8f9f7 4116 {
<> 144:ef7eb2e8f9f7 4117 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 4118 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
<> 144:ef7eb2e8f9f7 4119
<> 144:ef7eb2e8f9f7 4120 /* Set HAL_I2C_STATE_READY */
<> 144:ef7eb2e8f9f7 4121 hi2c->State = HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4122 hi2c->PreviousState = I2C_STATE_NONE;
<> 144:ef7eb2e8f9f7 4123 hi2c->XferISR = NULL;
<> 144:ef7eb2e8f9f7 4124 }
<> 144:ef7eb2e8f9f7 4125
<> 144:ef7eb2e8f9f7 4126 /* Abort DMA TX transfer if any */
<> 144:ef7eb2e8f9f7 4127 if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
<> 144:ef7eb2e8f9f7 4128 {
<> 144:ef7eb2e8f9f7 4129 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 4130
<> 144:ef7eb2e8f9f7 4131 /* Set the I2C DMA Abort callback :
<> 144:ef7eb2e8f9f7 4132 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 4133 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<> 144:ef7eb2e8f9f7 4134
<> 144:ef7eb2e8f9f7 4135 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4136 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4137
<> 144:ef7eb2e8f9f7 4138 /* Abort DMA TX */
<> 144:ef7eb2e8f9f7 4139 if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<> 144:ef7eb2e8f9f7 4140 {
<> 144:ef7eb2e8f9f7 4141 /* Call Directly XferAbortCallback function in case of error */
<> 144:ef7eb2e8f9f7 4142 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<> 144:ef7eb2e8f9f7 4143 }
<> 144:ef7eb2e8f9f7 4144 }
<> 144:ef7eb2e8f9f7 4145 /* Abort DMA RX transfer if any */
<> 144:ef7eb2e8f9f7 4146 else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
<> 144:ef7eb2e8f9f7 4147 {
<> 144:ef7eb2e8f9f7 4148 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 4149
<> 144:ef7eb2e8f9f7 4150 /* Set the I2C DMA Abort callback :
<> 144:ef7eb2e8f9f7 4151 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<> 144:ef7eb2e8f9f7 4152 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4155 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4156
<> 144:ef7eb2e8f9f7 4157 /* Abort DMA RX */
<> 144:ef7eb2e8f9f7 4158 if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<> 144:ef7eb2e8f9f7 4159 {
<> 144:ef7eb2e8f9f7 4160 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<> 144:ef7eb2e8f9f7 4161 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<> 144:ef7eb2e8f9f7 4162 }
<> 144:ef7eb2e8f9f7 4163 }
<> 144:ef7eb2e8f9f7 4164 else if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
<> 144:ef7eb2e8f9f7 4165 {
<> 144:ef7eb2e8f9f7 4166 hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
<> 144:ef7eb2e8f9f7 4167
<> 144:ef7eb2e8f9f7 4168 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4169 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4170
<> 144:ef7eb2e8f9f7 4171 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4172 HAL_I2C_AbortCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4173 }
<> 144:ef7eb2e8f9f7 4174 else
<> 144:ef7eb2e8f9f7 4175 {
<> 144:ef7eb2e8f9f7 4176 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4177 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4178
<> 144:ef7eb2e8f9f7 4179 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4180 HAL_I2C_ErrorCallback(hi2c);
<> 144:ef7eb2e8f9f7 4181 }
<> 144:ef7eb2e8f9f7 4182 }
<> 144:ef7eb2e8f9f7 4183
<> 144:ef7eb2e8f9f7 4184 /**
<> 144:ef7eb2e8f9f7 4185 * @brief I2C Tx data register flush process.
<> 144:ef7eb2e8f9f7 4186 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 4187 * @retval None
<> 144:ef7eb2e8f9f7 4188 */
<> 144:ef7eb2e8f9f7 4189 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
<> 144:ef7eb2e8f9f7 4190 {
<> 144:ef7eb2e8f9f7 4191 /* If a pending TXIS flag is set */
<> 144:ef7eb2e8f9f7 4192 /* Write a dummy data in TXDR to clear it */
<> 144:ef7eb2e8f9f7 4193 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
<> 144:ef7eb2e8f9f7 4194 {
<> 144:ef7eb2e8f9f7 4195 hi2c->Instance->TXDR = 0x00;
<> 144:ef7eb2e8f9f7 4196 }
<> 144:ef7eb2e8f9f7 4197
<> 144:ef7eb2e8f9f7 4198 /* Flush TX register if not empty */
<> 144:ef7eb2e8f9f7 4199 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<> 144:ef7eb2e8f9f7 4200 {
<> 144:ef7eb2e8f9f7 4201 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
<> 144:ef7eb2e8f9f7 4202 }
<> 144:ef7eb2e8f9f7 4203 }
<> 144:ef7eb2e8f9f7 4204
<> 144:ef7eb2e8f9f7 4205 /**
<> 144:ef7eb2e8f9f7 4206 * @brief DMA I2C master transmit process complete callback.
<> 144:ef7eb2e8f9f7 4207 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 4208 * @retval None
<> 144:ef7eb2e8f9f7 4209 */
<> 144:ef7eb2e8f9f7 4210 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4211 {
<> 144:ef7eb2e8f9f7 4212 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 4213
<> 144:ef7eb2e8f9f7 4214 /* Disable DMA Request */
<> 144:ef7eb2e8f9f7 4215 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
<> 144:ef7eb2e8f9f7 4216
<> 144:ef7eb2e8f9f7 4217 /* If last transfer, enable STOP interrupt */
<> 144:ef7eb2e8f9f7 4218 if(hi2c->XferCount == 0)
<> 144:ef7eb2e8f9f7 4219 {
<> 144:ef7eb2e8f9f7 4220 /* Enable STOP interrupt */
<> 144:ef7eb2e8f9f7 4221 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<> 144:ef7eb2e8f9f7 4222 }
<> 144:ef7eb2e8f9f7 4223 /* else prepare a new DMA transfer and enable TCReload interrupt */
<> 144:ef7eb2e8f9f7 4224 else
<> 144:ef7eb2e8f9f7 4225 {
<> 144:ef7eb2e8f9f7 4226 /* Update Buffer pointer */
<> 144:ef7eb2e8f9f7 4227 hi2c->pBuffPtr += hi2c->XferSize;
<> 144:ef7eb2e8f9f7 4228
<> 144:ef7eb2e8f9f7 4229 /* Set the XferSize to transfer */
<> 144:ef7eb2e8f9f7 4230 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 4231 {
<> 144:ef7eb2e8f9f7 4232 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 4233 }
<> 144:ef7eb2e8f9f7 4234 else
<> 144:ef7eb2e8f9f7 4235 {
<> 144:ef7eb2e8f9f7 4236 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 4237 }
<> 144:ef7eb2e8f9f7 4238
<> 144:ef7eb2e8f9f7 4239 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 4240 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 4241
<> 144:ef7eb2e8f9f7 4242 /* Enable TC interrupts */
<> 144:ef7eb2e8f9f7 4243 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
<> 144:ef7eb2e8f9f7 4244 }
<> 144:ef7eb2e8f9f7 4245 }
<> 144:ef7eb2e8f9f7 4246
<> 144:ef7eb2e8f9f7 4247 /**
<> 144:ef7eb2e8f9f7 4248 * @brief DMA I2C slave transmit process complete callback.
<> 144:ef7eb2e8f9f7 4249 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 4250 * @retval None
<> 144:ef7eb2e8f9f7 4251 */
<> 144:ef7eb2e8f9f7 4252 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4253 {
<> 144:ef7eb2e8f9f7 4254 /* No specific action, Master fully manage the generation of STOP condition */
<> 144:ef7eb2e8f9f7 4255 /* Mean that this generation can arrive at any time, at the end or during DMA process */
<> 144:ef7eb2e8f9f7 4256 /* So STOP condition should be manage through Interrupt treatment */
<> 144:ef7eb2e8f9f7 4257 }
<> 144:ef7eb2e8f9f7 4258
<> 144:ef7eb2e8f9f7 4259 /**
<> 144:ef7eb2e8f9f7 4260 * @brief DMA I2C master receive process complete callback.
<> 144:ef7eb2e8f9f7 4261 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 4262 * @retval None
<> 144:ef7eb2e8f9f7 4263 */
<> 144:ef7eb2e8f9f7 4264 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4265 {
<> 144:ef7eb2e8f9f7 4266 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 /* Disable DMA Request */
<> 144:ef7eb2e8f9f7 4269 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
<> 144:ef7eb2e8f9f7 4270
<> 144:ef7eb2e8f9f7 4271 /* If last transfer, enable STOP interrupt */
<> 144:ef7eb2e8f9f7 4272 if(hi2c->XferCount == 0)
<> 144:ef7eb2e8f9f7 4273 {
<> 144:ef7eb2e8f9f7 4274 /* Enable STOP interrupt */
<> 144:ef7eb2e8f9f7 4275 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
<> 144:ef7eb2e8f9f7 4276 }
<> 144:ef7eb2e8f9f7 4277 /* else prepare a new DMA transfer and enable TCReload interrupt */
<> 144:ef7eb2e8f9f7 4278 else
<> 144:ef7eb2e8f9f7 4279 {
<> 144:ef7eb2e8f9f7 4280 /* Update Buffer pointer */
<> 144:ef7eb2e8f9f7 4281 hi2c->pBuffPtr += hi2c->XferSize;
<> 144:ef7eb2e8f9f7 4282
<> 144:ef7eb2e8f9f7 4283 /* Set the XferSize to transfer */
<> 144:ef7eb2e8f9f7 4284 if(hi2c->XferCount > MAX_NBYTE_SIZE)
<> 144:ef7eb2e8f9f7 4285 {
<> 144:ef7eb2e8f9f7 4286 hi2c->XferSize = MAX_NBYTE_SIZE;
<> 144:ef7eb2e8f9f7 4287 }
<> 144:ef7eb2e8f9f7 4288 else
<> 144:ef7eb2e8f9f7 4289 {
<> 144:ef7eb2e8f9f7 4290 hi2c->XferSize = hi2c->XferCount;
<> 144:ef7eb2e8f9f7 4291 }
<> 144:ef7eb2e8f9f7 4292
<> 144:ef7eb2e8f9f7 4293 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 4294 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<> 144:ef7eb2e8f9f7 4295
<> 144:ef7eb2e8f9f7 4296 /* Enable TC interrupts */
<> 144:ef7eb2e8f9f7 4297 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
<> 144:ef7eb2e8f9f7 4298 }
<> 144:ef7eb2e8f9f7 4299 }
<> 144:ef7eb2e8f9f7 4300
<> 144:ef7eb2e8f9f7 4301 /**
<> 144:ef7eb2e8f9f7 4302 * @brief DMA I2C slave receive process complete callback.
<> 144:ef7eb2e8f9f7 4303 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 4304 * @retval None
<> 144:ef7eb2e8f9f7 4305 */
<> 144:ef7eb2e8f9f7 4306 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4307 {
<> 144:ef7eb2e8f9f7 4308 /* No specific action, Master fully manage the generation of STOP condition */
<> 144:ef7eb2e8f9f7 4309 /* Mean that this generation can arrive at any time, at the end or during DMA process */
<> 144:ef7eb2e8f9f7 4310 /* So STOP condition should be manage through Interrupt treatment */
<> 144:ef7eb2e8f9f7 4311 }
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 /**
<> 144:ef7eb2e8f9f7 4314 * @brief DMA I2C communication error callback.
<> 144:ef7eb2e8f9f7 4315 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 4316 * @retval None
<> 144:ef7eb2e8f9f7 4317 */
<> 144:ef7eb2e8f9f7 4318 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4319 {
<> 144:ef7eb2e8f9f7 4320 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4321
<> 144:ef7eb2e8f9f7 4322 /* Disable Acknowledge */
<> 144:ef7eb2e8f9f7 4323 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 4324
<> 144:ef7eb2e8f9f7 4325 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4326 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
<> 144:ef7eb2e8f9f7 4327 }
<> 144:ef7eb2e8f9f7 4328
<> 144:ef7eb2e8f9f7 4329 /**
<> 144:ef7eb2e8f9f7 4330 * @brief DMA I2C communication abort callback
<> 144:ef7eb2e8f9f7 4331 * (To be called at end of DMA Abort procedure).
<> 144:ef7eb2e8f9f7 4332 * @param hdma: DMA handle.
<> 144:ef7eb2e8f9f7 4333 * @retval None
<> 144:ef7eb2e8f9f7 4334 */
<> 144:ef7eb2e8f9f7 4335 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4336 {
<> 144:ef7eb2e8f9f7 4337 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4338
<> 144:ef7eb2e8f9f7 4339 /* Disable Acknowledge */
<> 144:ef7eb2e8f9f7 4340 hi2c->Instance->CR2 |= I2C_CR2_NACK;
<> 144:ef7eb2e8f9f7 4341
<> 144:ef7eb2e8f9f7 4342 /* Reset AbortCpltCallback */
<> 144:ef7eb2e8f9f7 4343 hi2c->hdmatx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 4344 hi2c->hdmarx->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 4345
<> 144:ef7eb2e8f9f7 4346 /* Check if come from abort from user */
<> 144:ef7eb2e8f9f7 4347 if(hi2c->ErrorCode == HAL_I2C_ERROR_ABORT)
<> 144:ef7eb2e8f9f7 4348 {
<> 144:ef7eb2e8f9f7 4349 hi2c->ErrorCode &= ~HAL_I2C_ERROR_ABORT;
<> 144:ef7eb2e8f9f7 4350
<> 144:ef7eb2e8f9f7 4351 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4352 HAL_I2C_AbortCpltCallback(hi2c);
<> 144:ef7eb2e8f9f7 4353 }
<> 144:ef7eb2e8f9f7 4354 else
<> 144:ef7eb2e8f9f7 4355 {
<> 144:ef7eb2e8f9f7 4356 /* Call the corresponding callback to inform upper layer of End of Transfer */
<> 144:ef7eb2e8f9f7 4357 HAL_I2C_ErrorCallback(hi2c);
<> 144:ef7eb2e8f9f7 4358 }
<> 144:ef7eb2e8f9f7 4359 }
<> 144:ef7eb2e8f9f7 4360
<> 144:ef7eb2e8f9f7 4361 /**
<> 144:ef7eb2e8f9f7 4362 * @brief This function handles I2C Communication Timeout.
<> 144:ef7eb2e8f9f7 4363 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4364 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4365 * @param Flag: Specifies the I2C flag to check.
<> 144:ef7eb2e8f9f7 4366 * @param Status: The new Flag status (SET or RESET).
<> 144:ef7eb2e8f9f7 4367 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 4368 * @param Tickstart: Tick start value
<> 144:ef7eb2e8f9f7 4369 * @retval HAL status
<> 144:ef7eb2e8f9f7 4370 */
<> 144:ef7eb2e8f9f7 4371 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 4372 {
<> 144:ef7eb2e8f9f7 4373 while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
<> 144:ef7eb2e8f9f7 4374 {
<> 144:ef7eb2e8f9f7 4375 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 4376 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 4377 {
<> 144:ef7eb2e8f9f7 4378 if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 4379 {
<> 144:ef7eb2e8f9f7 4380 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4381 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4382
<> 144:ef7eb2e8f9f7 4383 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4384 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4385 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4386 }
<> 144:ef7eb2e8f9f7 4387 }
<> 144:ef7eb2e8f9f7 4388 }
<> 144:ef7eb2e8f9f7 4389 return HAL_OK;
<> 144:ef7eb2e8f9f7 4390 }
<> 144:ef7eb2e8f9f7 4391
<> 144:ef7eb2e8f9f7 4392 /**
<> 144:ef7eb2e8f9f7 4393 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
<> 144:ef7eb2e8f9f7 4394 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4395 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4396 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 4397 * @param Tickstart: Tick start value
<> 144:ef7eb2e8f9f7 4398 * @retval HAL status
<> 144:ef7eb2e8f9f7 4399 */
<> 144:ef7eb2e8f9f7 4400 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 4401 {
<> 144:ef7eb2e8f9f7 4402 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
<> 144:ef7eb2e8f9f7 4403 {
<> 144:ef7eb2e8f9f7 4404 /* Check if a NACK is detected */
<> 144:ef7eb2e8f9f7 4405 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 4406 {
<> 144:ef7eb2e8f9f7 4407 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4408 }
<> 144:ef7eb2e8f9f7 4409
<> 144:ef7eb2e8f9f7 4410 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 4411 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 4412 {
<> 144:ef7eb2e8f9f7 4413 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4414 {
<> 144:ef7eb2e8f9f7 4415 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 4416 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4417 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4418
<> 144:ef7eb2e8f9f7 4419 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4420 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4421
<> 144:ef7eb2e8f9f7 4422 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4423 }
<> 144:ef7eb2e8f9f7 4424 }
<> 144:ef7eb2e8f9f7 4425 }
<> 144:ef7eb2e8f9f7 4426 return HAL_OK;
<> 144:ef7eb2e8f9f7 4427 }
<> 144:ef7eb2e8f9f7 4428
<> 144:ef7eb2e8f9f7 4429 /**
<> 144:ef7eb2e8f9f7 4430 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<> 144:ef7eb2e8f9f7 4431 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4432 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4433 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 4434 * @param Tickstart: Tick start value
<> 144:ef7eb2e8f9f7 4435 * @retval HAL status
<> 144:ef7eb2e8f9f7 4436 */
<> 144:ef7eb2e8f9f7 4437 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 4438 {
<> 144:ef7eb2e8f9f7 4439 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<> 144:ef7eb2e8f9f7 4440 {
<> 144:ef7eb2e8f9f7 4441 /* Check if a NACK is detected */
<> 144:ef7eb2e8f9f7 4442 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 4443 {
<> 144:ef7eb2e8f9f7 4444 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4445 }
<> 144:ef7eb2e8f9f7 4446
<> 144:ef7eb2e8f9f7 4447 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 4448 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4449 {
<> 144:ef7eb2e8f9f7 4450 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 4451 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4452 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4453
<> 144:ef7eb2e8f9f7 4454 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4455 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4456
<> 144:ef7eb2e8f9f7 4457 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4458 }
<> 144:ef7eb2e8f9f7 4459 }
<> 144:ef7eb2e8f9f7 4460 return HAL_OK;
<> 144:ef7eb2e8f9f7 4461 }
<> 144:ef7eb2e8f9f7 4462
<> 144:ef7eb2e8f9f7 4463 /**
<> 144:ef7eb2e8f9f7 4464 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<> 144:ef7eb2e8f9f7 4465 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4466 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4467 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 4468 * @param Tickstart: Tick start value
<> 144:ef7eb2e8f9f7 4469 * @retval HAL status
<> 144:ef7eb2e8f9f7 4470 */
<> 144:ef7eb2e8f9f7 4471 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 4472 {
<> 144:ef7eb2e8f9f7 4473 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<> 144:ef7eb2e8f9f7 4474 {
<> 144:ef7eb2e8f9f7 4475 /* Check if a NACK is detected */
<> 144:ef7eb2e8f9f7 4476 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
<> 144:ef7eb2e8f9f7 4477 {
<> 144:ef7eb2e8f9f7 4478 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4479 }
<> 144:ef7eb2e8f9f7 4480
<> 144:ef7eb2e8f9f7 4481 /* Check if a STOPF is detected */
<> 144:ef7eb2e8f9f7 4482 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<> 144:ef7eb2e8f9f7 4483 {
<> 144:ef7eb2e8f9f7 4484 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 4485 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 4486
<> 144:ef7eb2e8f9f7 4487 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 4488 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 4489
<> 144:ef7eb2e8f9f7 4490 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<> 144:ef7eb2e8f9f7 4491 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4492 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4493
<> 144:ef7eb2e8f9f7 4494 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4495 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4496
<> 144:ef7eb2e8f9f7 4497 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4498 }
<> 144:ef7eb2e8f9f7 4499
<> 144:ef7eb2e8f9f7 4500 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 4501 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4502 {
<> 144:ef7eb2e8f9f7 4503 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 4504 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4505
<> 144:ef7eb2e8f9f7 4506 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4507 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4508
<> 144:ef7eb2e8f9f7 4509 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4510 }
<> 144:ef7eb2e8f9f7 4511 }
<> 144:ef7eb2e8f9f7 4512 return HAL_OK;
<> 144:ef7eb2e8f9f7 4513 }
<> 144:ef7eb2e8f9f7 4514
<> 144:ef7eb2e8f9f7 4515 /**
<> 144:ef7eb2e8f9f7 4516 * @brief This function handles Acknowledge failed detection during an I2C Communication.
<> 144:ef7eb2e8f9f7 4517 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4518 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4519 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 4520 * @param Tickstart: Tick start value
<> 144:ef7eb2e8f9f7 4521 * @retval HAL status
<> 144:ef7eb2e8f9f7 4522 */
<> 144:ef7eb2e8f9f7 4523 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<> 144:ef7eb2e8f9f7 4524 {
<> 144:ef7eb2e8f9f7 4525 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<> 144:ef7eb2e8f9f7 4526 {
<> 144:ef7eb2e8f9f7 4527 /* Wait until STOP Flag is reset */
<> 144:ef7eb2e8f9f7 4528 /* AutoEnd should be initiate after AF */
<> 144:ef7eb2e8f9f7 4529 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<> 144:ef7eb2e8f9f7 4530 {
<> 144:ef7eb2e8f9f7 4531 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 4532 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 4533 {
<> 144:ef7eb2e8f9f7 4534 if((Timeout == 0)||((HAL_GetTick() - Tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 4535 {
<> 144:ef7eb2e8f9f7 4536 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4537 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4538
<> 144:ef7eb2e8f9f7 4539 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4540 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4541 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 4542 }
<> 144:ef7eb2e8f9f7 4543 }
<> 144:ef7eb2e8f9f7 4544 }
<> 144:ef7eb2e8f9f7 4545
<> 144:ef7eb2e8f9f7 4546 /* Clear NACKF Flag */
<> 144:ef7eb2e8f9f7 4547 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<> 144:ef7eb2e8f9f7 4548
<> 144:ef7eb2e8f9f7 4549 /* Clear STOP Flag */
<> 144:ef7eb2e8f9f7 4550 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<> 144:ef7eb2e8f9f7 4551
<> 144:ef7eb2e8f9f7 4552 /* Flush TX register */
<> 144:ef7eb2e8f9f7 4553 I2C_Flush_TXDR(hi2c);
<> 144:ef7eb2e8f9f7 4554
<> 144:ef7eb2e8f9f7 4555 /* Clear Configuration Register 2 */
<> 144:ef7eb2e8f9f7 4556 I2C_RESET_CR2(hi2c);
<> 144:ef7eb2e8f9f7 4557
<> 144:ef7eb2e8f9f7 4558 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<> 144:ef7eb2e8f9f7 4559 hi2c->State= HAL_I2C_STATE_READY;
<> 144:ef7eb2e8f9f7 4560 hi2c->Mode = HAL_I2C_MODE_NONE;
<> 144:ef7eb2e8f9f7 4561
<> 144:ef7eb2e8f9f7 4562 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 4563 __HAL_UNLOCK(hi2c);
<> 144:ef7eb2e8f9f7 4564
<> 144:ef7eb2e8f9f7 4565 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 4566 }
<> 144:ef7eb2e8f9f7 4567 return HAL_OK;
<> 144:ef7eb2e8f9f7 4568 }
<> 144:ef7eb2e8f9f7 4569
<> 144:ef7eb2e8f9f7 4570 /**
<> 144:ef7eb2e8f9f7 4571 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<> 144:ef7eb2e8f9f7 4572 * @param hi2c: I2C handle.
<> 144:ef7eb2e8f9f7 4573 * @param DevAddress: Specifies the slave address to be programmed.
<> 144:ef7eb2e8f9f7 4574 * @param Size: Specifies the number of bytes to be programmed.
<> 144:ef7eb2e8f9f7 4575 * This parameter must be a value between 0 and 255.
<> 144:ef7eb2e8f9f7 4576 * @param Mode: New state of the I2C START condition generation.
<> 144:ef7eb2e8f9f7 4577 * This parameter can be a value of @ref I2C_RELOAD_END_MODE.
<> 144:ef7eb2e8f9f7 4578 * @param Request: New state of the I2C START condition generation.
<> 144:ef7eb2e8f9f7 4579 * This parameter can be a value of I2C_START_STOP_MODE.
<> 144:ef7eb2e8f9f7 4580 * @retval None
<> 144:ef7eb2e8f9f7 4581 */
<> 144:ef7eb2e8f9f7 4582 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
<> 144:ef7eb2e8f9f7 4583 {
<> 144:ef7eb2e8f9f7 4584 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4587 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<> 144:ef7eb2e8f9f7 4588 assert_param(IS_TRANSFER_MODE(Mode));
<> 144:ef7eb2e8f9f7 4589 assert_param(IS_TRANSFER_REQUEST(Request));
<> 144:ef7eb2e8f9f7 4590
<> 144:ef7eb2e8f9f7 4591 /* Get the CR2 register value */
<> 144:ef7eb2e8f9f7 4592 tmpreg = hi2c->Instance->CR2;
<> 144:ef7eb2e8f9f7 4593
<> 144:ef7eb2e8f9f7 4594 /* clear tmpreg specific bits */
<> 144:ef7eb2e8f9f7 4595 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
<> 144:ef7eb2e8f9f7 4596
<> 144:ef7eb2e8f9f7 4597 /* update tmpreg */
<> 144:ef7eb2e8f9f7 4598 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
<> 144:ef7eb2e8f9f7 4599 (uint32_t)Mode | (uint32_t)Request);
<> 144:ef7eb2e8f9f7 4600
<> 144:ef7eb2e8f9f7 4601 /* update CR2 register */
<> 144:ef7eb2e8f9f7 4602 hi2c->Instance->CR2 = tmpreg;
<> 144:ef7eb2e8f9f7 4603 }
<> 144:ef7eb2e8f9f7 4604
<> 144:ef7eb2e8f9f7 4605 /**
<> 144:ef7eb2e8f9f7 4606 * @brief Manage the enabling of Interrupts.
<> 144:ef7eb2e8f9f7 4607 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4608 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4609 * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 4610 * @retval HAL status
<> 144:ef7eb2e8f9f7 4611 */
<> 144:ef7eb2e8f9f7 4612 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 4613 {
<> 144:ef7eb2e8f9f7 4614 uint32_t tmpisr = 0;
<> 144:ef7eb2e8f9f7 4615
<> 144:ef7eb2e8f9f7 4616 if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
<> 144:ef7eb2e8f9f7 4617 (hi2c->XferISR == I2C_Slave_ISR_DMA))
<> 144:ef7eb2e8f9f7 4618 {
<> 144:ef7eb2e8f9f7 4619 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<> 144:ef7eb2e8f9f7 4620 {
<> 144:ef7eb2e8f9f7 4621 /* Enable ERR, STOP, NACK and ADDR interrupts */
<> 144:ef7eb2e8f9f7 4622 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
<> 144:ef7eb2e8f9f7 4623 }
<> 144:ef7eb2e8f9f7 4624
<> 144:ef7eb2e8f9f7 4625 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
<> 144:ef7eb2e8f9f7 4626 {
<> 144:ef7eb2e8f9f7 4627 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 4628 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
<> 144:ef7eb2e8f9f7 4629 }
<> 144:ef7eb2e8f9f7 4630
<> 144:ef7eb2e8f9f7 4631 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<> 144:ef7eb2e8f9f7 4632 {
<> 144:ef7eb2e8f9f7 4633 /* Enable STOP interrupts */
<> 144:ef7eb2e8f9f7 4634 tmpisr |= I2C_IT_STOPI;
<> 144:ef7eb2e8f9f7 4635 }
<> 144:ef7eb2e8f9f7 4636
<> 144:ef7eb2e8f9f7 4637 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
<> 144:ef7eb2e8f9f7 4638 {
<> 144:ef7eb2e8f9f7 4639 /* Enable TC interrupts */
<> 144:ef7eb2e8f9f7 4640 tmpisr |= I2C_IT_TCI;
<> 144:ef7eb2e8f9f7 4641 }
<> 144:ef7eb2e8f9f7 4642 }
<> 144:ef7eb2e8f9f7 4643 else
<> 144:ef7eb2e8f9f7 4644 {
<> 144:ef7eb2e8f9f7 4645 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<> 144:ef7eb2e8f9f7 4646 {
<> 144:ef7eb2e8f9f7 4647 /* Enable ERR, STOP, NACK, and ADDR interrupts */
<> 144:ef7eb2e8f9f7 4648 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
<> 144:ef7eb2e8f9f7 4649 }
<> 144:ef7eb2e8f9f7 4650
<> 144:ef7eb2e8f9f7 4651 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
<> 144:ef7eb2e8f9f7 4652 {
<> 144:ef7eb2e8f9f7 4653 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
<> 144:ef7eb2e8f9f7 4654 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
<> 144:ef7eb2e8f9f7 4655 }
<> 144:ef7eb2e8f9f7 4656
<> 144:ef7eb2e8f9f7 4657 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
<> 144:ef7eb2e8f9f7 4658 {
<> 144:ef7eb2e8f9f7 4659 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
<> 144:ef7eb2e8f9f7 4660 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
<> 144:ef7eb2e8f9f7 4661 }
<> 144:ef7eb2e8f9f7 4662
<> 144:ef7eb2e8f9f7 4663 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<> 144:ef7eb2e8f9f7 4664 {
<> 144:ef7eb2e8f9f7 4665 /* Enable STOP interrupts */
<> 144:ef7eb2e8f9f7 4666 tmpisr |= I2C_IT_STOPI;
<> 144:ef7eb2e8f9f7 4667 }
<> 144:ef7eb2e8f9f7 4668 }
<> 144:ef7eb2e8f9f7 4669
<> 144:ef7eb2e8f9f7 4670 /* Enable interrupts only at the end */
<> 144:ef7eb2e8f9f7 4671 /* to avoid the risk of I2C interrupt handle execution before */
<> 144:ef7eb2e8f9f7 4672 /* all interrupts requested done */
<> 144:ef7eb2e8f9f7 4673 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
<> 144:ef7eb2e8f9f7 4674
<> 144:ef7eb2e8f9f7 4675 return HAL_OK;
<> 144:ef7eb2e8f9f7 4676 }
<> 144:ef7eb2e8f9f7 4677
<> 144:ef7eb2e8f9f7 4678 /**
<> 144:ef7eb2e8f9f7 4679 * @brief Manage the disabling of Interrupts.
<> 144:ef7eb2e8f9f7 4680 * @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4681 * the configuration information for the specified I2C.
<> 144:ef7eb2e8f9f7 4682 * @param InterruptRequest: Value of @ref I2C_Interrupt_configuration_definition.
<> 144:ef7eb2e8f9f7 4683 * @retval HAL status
<> 144:ef7eb2e8f9f7 4684 */
<> 144:ef7eb2e8f9f7 4685 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
<> 144:ef7eb2e8f9f7 4686 {
<> 144:ef7eb2e8f9f7 4687 uint32_t tmpisr = 0;
<> 144:ef7eb2e8f9f7 4688
<> 144:ef7eb2e8f9f7 4689 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
<> 144:ef7eb2e8f9f7 4690 {
<> 144:ef7eb2e8f9f7 4691 /* Disable TC and TXI interrupts */
<> 144:ef7eb2e8f9f7 4692 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 4695 {
<> 144:ef7eb2e8f9f7 4696 /* Disable NACK and STOP interrupts */
<> 144:ef7eb2e8f9f7 4697 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
<> 144:ef7eb2e8f9f7 4698 }
<> 144:ef7eb2e8f9f7 4699 }
<> 144:ef7eb2e8f9f7 4700
<> 144:ef7eb2e8f9f7 4701 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
<> 144:ef7eb2e8f9f7 4702 {
<> 144:ef7eb2e8f9f7 4703 /* Disable TC and RXI interrupts */
<> 144:ef7eb2e8f9f7 4704 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
<> 144:ef7eb2e8f9f7 4705
<> 144:ef7eb2e8f9f7 4706 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
<> 144:ef7eb2e8f9f7 4707 {
<> 144:ef7eb2e8f9f7 4708 /* Disable NACK and STOP interrupts */
<> 144:ef7eb2e8f9f7 4709 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
<> 144:ef7eb2e8f9f7 4710 }
<> 144:ef7eb2e8f9f7 4711 }
<> 144:ef7eb2e8f9f7 4712
<> 144:ef7eb2e8f9f7 4713 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
<> 144:ef7eb2e8f9f7 4714 {
<> 144:ef7eb2e8f9f7 4715 /* Disable ADDR, NACK and STOP interrupts */
<> 144:ef7eb2e8f9f7 4716 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
<> 144:ef7eb2e8f9f7 4717 }
<> 144:ef7eb2e8f9f7 4718
<> 144:ef7eb2e8f9f7 4719 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
<> 144:ef7eb2e8f9f7 4720 {
<> 144:ef7eb2e8f9f7 4721 /* Enable ERR and NACK interrupts */
<> 144:ef7eb2e8f9f7 4722 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
<> 144:ef7eb2e8f9f7 4723 }
<> 144:ef7eb2e8f9f7 4724
<> 144:ef7eb2e8f9f7 4725 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
<> 144:ef7eb2e8f9f7 4726 {
<> 144:ef7eb2e8f9f7 4727 /* Enable STOP interrupts */
<> 144:ef7eb2e8f9f7 4728 tmpisr |= I2C_IT_STOPI;
<> 144:ef7eb2e8f9f7 4729 }
<> 144:ef7eb2e8f9f7 4730
<> 144:ef7eb2e8f9f7 4731 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
<> 144:ef7eb2e8f9f7 4732 {
<> 144:ef7eb2e8f9f7 4733 /* Enable TC interrupts */
<> 144:ef7eb2e8f9f7 4734 tmpisr |= I2C_IT_TCI;
<> 144:ef7eb2e8f9f7 4735 }
<> 144:ef7eb2e8f9f7 4736
<> 144:ef7eb2e8f9f7 4737 /* Disable interrupts only at the end */
<> 144:ef7eb2e8f9f7 4738 /* to avoid a breaking situation like at "t" time */
<> 144:ef7eb2e8f9f7 4739 /* all disable interrupts request are not done */
<> 144:ef7eb2e8f9f7 4740 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
<> 144:ef7eb2e8f9f7 4741
<> 144:ef7eb2e8f9f7 4742 return HAL_OK;
<> 144:ef7eb2e8f9f7 4743 }
<> 144:ef7eb2e8f9f7 4744
<> 144:ef7eb2e8f9f7 4745 /**
<> 144:ef7eb2e8f9f7 4746 * @}
<> 144:ef7eb2e8f9f7 4747 */
<> 144:ef7eb2e8f9f7 4748
<> 144:ef7eb2e8f9f7 4749 #endif /* HAL_I2C_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 4750 /**
<> 144:ef7eb2e8f9f7 4751 * @}
<> 144:ef7eb2e8f9f7 4752 */
<> 144:ef7eb2e8f9f7 4753
<> 144:ef7eb2e8f9f7 4754 /**
<> 144:ef7eb2e8f9f7 4755 * @}
<> 144:ef7eb2e8f9f7 4756 */
<> 144:ef7eb2e8f9f7 4757
<> 144:ef7eb2e8f9f7 4758 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/