Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + IO operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and errors functions
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
<> 144:ef7eb2e8f9f7 20 (except for internal SRAM/FLASH memories: no initialization is
<> 144:ef7eb2e8f9f7 21 necessary) please refer to Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 22 and DMA requests .
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) For a given Stream, program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 Transfer Direction, Source and Destination data formats,
<> 144:ef7eb2e8f9f7 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
<> 144:ef7eb2e8f9f7 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
<> 144:ef7eb2e8f9f7 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 31 =================================
<> 144:ef7eb2e8f9f7 32 [..]
<> 144:ef7eb2e8f9f7 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 144:ef7eb2e8f9f7 34 address and destination address and the Length of data to be transferred
<> 144:ef7eb2e8f9f7 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 144:ef7eb2e8f9f7 36 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 39 ===================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 144:ef7eb2e8f9f7 44 Source address and destination address and the Length of data to be transferred. In this
<> 144:ef7eb2e8f9f7 45 case the DMA interrupt is configured
<> 144:ef7eb2e8f9f7 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 144:ef7eb2e8f9f7 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 48 add his own function by customization of function pointer XferCpltCallback and
<> 144:ef7eb2e8f9f7 49 XferErrorCallback (i.e a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 52 detection.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
<> 144:ef7eb2e8f9f7 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
<> 144:ef7eb2e8f9f7 60 Half-Word data size for the peripheral to access its data register and set Word data size
<> 144:ef7eb2e8f9f7 61 for the Memory to gain in access time. Each two half words will be packed and written in
<> 144:ef7eb2e8f9f7 62 a single access to a Word in the Memory).
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
<> 144:ef7eb2e8f9f7 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
<> 144:ef7eb2e8f9f7 66 and Destination.
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 69 =============================================
<> 144:ef7eb2e8f9f7 70 [..]
<> 144:ef7eb2e8f9f7 71 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
<> 144:ef7eb2e8f9f7 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
<> 144:ef7eb2e8f9f7 76 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
<> 144:ef7eb2e8f9f7 77 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
<> 144:ef7eb2e8f9f7 78 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 @endverbatim
<> 144:ef7eb2e8f9f7 84 ******************************************************************************
<> 144:ef7eb2e8f9f7 85 * @attention
<> 144:ef7eb2e8f9f7 86 *
<> 144:ef7eb2e8f9f7 87 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 90 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 91 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 92 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 93 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 94 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 95 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 96 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 97 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 98 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 ******************************************************************************
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 122 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 typedef struct
<> 144:ef7eb2e8f9f7 130 {
<> 144:ef7eb2e8f9f7 131 __IO uint32_t ISR; /*!< DMA interrupt status register */
<> 144:ef7eb2e8f9f7 132 __IO uint32_t Reserved0;
<> 144:ef7eb2e8f9f7 133 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
<> 144:ef7eb2e8f9f7 134 } DMA_Base_Registers;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 /** @addtogroup DMA_Private_Constants
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 144:ef7eb2e8f9f7 141 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 147 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 152 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 164 *
<> 144:ef7eb2e8f9f7 165 @verbatim
<> 144:ef7eb2e8f9f7 166 ===============================================================================
<> 144:ef7eb2e8f9f7 167 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 168 ===============================================================================
<> 144:ef7eb2e8f9f7 169 [..]
<> 144:ef7eb2e8f9f7 170 This section provides functions allowing to initialize the DMA Stream source
<> 144:ef7eb2e8f9f7 171 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 172 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
<> 144:ef7eb2e8f9f7 173 [..]
<> 144:ef7eb2e8f9f7 174 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 175 reference manual.
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 @endverbatim
<> 144:ef7eb2e8f9f7 178 * @{
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @brief Initialize the DMA according to the specified
<> 144:ef7eb2e8f9f7 183 * parameters in the DMA_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 184 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 185 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 186 * @retval HAL status
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 191 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 192 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 195 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Check the parameters */
<> 144:ef7eb2e8f9f7 201 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 202 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
<> 144:ef7eb2e8f9f7 203 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 204 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 205 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 206 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 207 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 208 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 209 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 144:ef7eb2e8f9f7 210 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
<> 144:ef7eb2e8f9f7 211 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
<> 144:ef7eb2e8f9f7 212 when FIFO mode is enabled */
<> 144:ef7eb2e8f9f7 213 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
<> 144:ef7eb2e8f9f7 216 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
<> 144:ef7eb2e8f9f7 217 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Allocate lock resource */
<> 144:ef7eb2e8f9f7 221 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 224 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Disable the peripheral */
<> 144:ef7eb2e8f9f7 227 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Check if the DMA Stream is effectively disabled */
<> 144:ef7eb2e8f9f7 230 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 233 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Update error code */
<> 144:ef7eb2e8f9f7 236 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 239 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 246 tmp = hdma->Instance->CR;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
<> 144:ef7eb2e8f9f7 249 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
<> 144:ef7eb2e8f9f7 250 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
<> 144:ef7eb2e8f9f7 251 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
<> 144:ef7eb2e8f9f7 252 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Prepare the DMA Stream configuration */
<> 144:ef7eb2e8f9f7 255 tmp |= hdma->Init.Channel | hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 256 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 257 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 258 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
<> 144:ef7eb2e8f9f7 261 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Get memory burst and peripheral burst */
<> 144:ef7eb2e8f9f7 264 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Write to DMA Stream CR register */
<> 144:ef7eb2e8f9f7 268 hdma->Instance->CR = tmp;
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Get the FCR register value */
<> 144:ef7eb2e8f9f7 271 tmp = hdma->Instance->FCR;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Clear Direct mode and FIFO threshold bits */
<> 144:ef7eb2e8f9f7 274 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Prepare the DMA Stream FIFO configuration */
<> 144:ef7eb2e8f9f7 277 tmp |= hdma->Init.FIFOMode;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* the FIFO threshold is not used when the FIFO mode is disabled */
<> 144:ef7eb2e8f9f7 280 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Get the FIFO threshold */
<> 144:ef7eb2e8f9f7 283 tmp |= hdma->Init.FIFOThreshold;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 if (DMA_CheckFifoParam(hdma) != HAL_OK)
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 /* Update error code */
<> 144:ef7eb2e8f9f7 288 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 291 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Write to DMA Stream FCR */
<> 144:ef7eb2e8f9f7 298 hdma->Instance->FCR = tmp;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
<> 144:ef7eb2e8f9f7 301 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
<> 144:ef7eb2e8f9f7 302 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Clear all interrupt flags */
<> 144:ef7eb2e8f9f7 305 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 308 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 311 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 return HAL_OK;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief DeInitializes the DMA peripheral
<> 144:ef7eb2e8f9f7 318 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 319 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 320 * @retval HAL status
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 327 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Check the DMA peripheral state */
<> 144:ef7eb2e8f9f7 333 if(hdma->State == HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 /* Return error status */
<> 144:ef7eb2e8f9f7 336 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Disable the selected DMA Streamx */
<> 144:ef7eb2e8f9f7 340 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Reset DMA Streamx control register */
<> 144:ef7eb2e8f9f7 343 hdma->Instance->CR = 0U;
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Reset DMA Streamx number of data to transfer register */
<> 144:ef7eb2e8f9f7 346 hdma->Instance->NDTR = 0U;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Reset DMA Streamx peripheral address register */
<> 144:ef7eb2e8f9f7 349 hdma->Instance->PAR = 0U;
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Reset DMA Streamx memory 0 address register */
<> 144:ef7eb2e8f9f7 352 hdma->Instance->M0AR = 0U;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Reset DMA Streamx memory 1 address register */
<> 144:ef7eb2e8f9f7 355 hdma->Instance->M1AR = 0U;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Reset DMA Streamx FIFO control register */
<> 144:ef7eb2e8f9f7 358 hdma->Instance->FCR = (uint32_t)0x00000021U;
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Get DMA steam Base Address */
<> 144:ef7eb2e8f9f7 361 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 364 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 367 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 370 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Release Lock */
<> 144:ef7eb2e8f9f7 373 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 return HAL_OK;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 383 *
<> 144:ef7eb2e8f9f7 384 @verbatim
<> 144:ef7eb2e8f9f7 385 ===============================================================================
<> 144:ef7eb2e8f9f7 386 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 387 ===============================================================================
<> 144:ef7eb2e8f9f7 388 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 389 (+) Configure the source, destination address and data length and Start DMA transfer
<> 144:ef7eb2e8f9f7 390 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 391 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 392 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 393 (+) Poll for transfer complete
<> 144:ef7eb2e8f9f7 394 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 @endverbatim
<> 144:ef7eb2e8f9f7 397 * @{
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @brief Starts the DMA Transfer.
<> 144:ef7eb2e8f9f7 402 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 403 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 404 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 405 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 406 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 407 * @retval HAL status
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Check the parameters */
<> 144:ef7eb2e8f9f7 414 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Process locked */
<> 144:ef7eb2e8f9f7 417 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 422 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 425 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 428 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 431 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433 else
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Process unlocked */
<> 144:ef7eb2e8f9f7 436 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Return error status */
<> 144:ef7eb2e8f9f7 439 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 return status;
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @brief Start the DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 446 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 447 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 448 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 449 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 450 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 451 * @retval HAL status
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 458 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Check the parameters */
<> 144:ef7eb2e8f9f7 461 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Process locked */
<> 144:ef7eb2e8f9f7 464 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 469 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 472 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 475 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 478 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Enable Common interrupts*/
<> 144:ef7eb2e8f9f7 481 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
<> 144:ef7eb2e8f9f7 482 hdma->Instance->FCR |= DMA_IT_FE;
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 hdma->Instance->CR |= DMA_IT_HT;
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 490 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 /* Process unlocked */
<> 144:ef7eb2e8f9f7 495 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /* Return error status */
<> 144:ef7eb2e8f9f7 498 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 return status;
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @brief Aborts the DMA Transfer.
<> 144:ef7eb2e8f9f7 506 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 507 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 508 *
<> 144:ef7eb2e8f9f7 509 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
<> 144:ef7eb2e8f9f7 510 * effectively disabled is added. If a Stream is disabled
<> 144:ef7eb2e8f9f7 511 * while a data transfer is ongoing, the current data will be transferred
<> 144:ef7eb2e8f9f7 512 * and the Stream will be effectively disabled only after the transfer of
<> 144:ef7eb2e8f9f7 513 * this single data is finished.
<> 144:ef7eb2e8f9f7 514 * @retval HAL status
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 519 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 if(hdma->State != HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 528 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 else
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Disable all the transfer interrupts */
<> 144:ef7eb2e8f9f7 535 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
<> 144:ef7eb2e8f9f7 536 hdma->Instance->FCR &= ~(DMA_IT_FE);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Disable the stream */
<> 144:ef7eb2e8f9f7 544 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Check if the DMA Stream is effectively disabled */
<> 144:ef7eb2e8f9f7 547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 550 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Update error code */
<> 144:ef7eb2e8f9f7 553 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 556 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 559 hdma->State = HAL_DMA_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 566 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 569 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Change the DMA state*/
<> 144:ef7eb2e8f9f7 572 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 return HAL_OK;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /**
<> 144:ef7eb2e8f9f7 578 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 144:ef7eb2e8f9f7 579 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 580 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 581 * @retval HAL status
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 if(hdma->State != HAL_DMA_STATE_BUSY)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 144:ef7eb2e8f9f7 588 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590 else
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Set Abort State */
<> 144:ef7eb2e8f9f7 593 hdma->State = HAL_DMA_STATE_ABORT;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Disable the stream */
<> 144:ef7eb2e8f9f7 596 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 return HAL_OK;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /**
<> 144:ef7eb2e8f9f7 603 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 604 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 605 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 606 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 607 * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
<> 144:ef7eb2e8f9f7 608 * This model could be used for debug purpose.
<> 144:ef7eb2e8f9f7 609 * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
<> 144:ef7eb2e8f9f7 610 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 611 * @retval HAL status
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 616 uint32_t temp;
<> 144:ef7eb2e8f9f7 617 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 618 uint32_t tmpisr;
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 621 DMA_Base_Registers *regs;
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /* Polling mode not supported in circular mode and double buffering mode */
<> 144:ef7eb2e8f9f7 624 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
<> 144:ef7eb2e8f9f7 625 {
<> 144:ef7eb2e8f9f7 626 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 627 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 631 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 634 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 else
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 639 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 643 tmpisr = regs->ISR;
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 while((tmpisr & temp) == RESET )
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 /* Check for the Timeout (Not applicable in circular mode)*/
<> 144:ef7eb2e8f9f7 648 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 /* Update error code */
<> 144:ef7eb2e8f9f7 653 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 656 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 659 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 /* Update error code */
<> 144:ef7eb2e8f9f7 668 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 671 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 675 {
<> 144:ef7eb2e8f9f7 676 /* Update error code */
<> 144:ef7eb2e8f9f7 677 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /* Clear the FIFO error flag */
<> 144:ef7eb2e8f9f7 680 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 /* Update error code */
<> 144:ef7eb2e8f9f7 686 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Clear the Direct Mode error flag */
<> 144:ef7eb2e8f9f7 689 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 HAL_DMA_Abort(hdma);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 700 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 703 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 706 hdma->State= HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 715 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 718 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 721 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725 else
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 /* Clear the half transfer and transfer complete flags */
<> 144:ef7eb2e8f9f7 728 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 return status;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 736 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 737 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 738 * @retval None
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 741 {
<> 144:ef7eb2e8f9f7 742 uint32_t tmpisr;
<> 144:ef7eb2e8f9f7 743 __IO uint32_t count = 0;
<> 144:ef7eb2e8f9f7 744 uint32_t timeout = SystemCoreClock / 9600;
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* calculate DMA base and stream number */
<> 144:ef7eb2e8f9f7 747 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 tmpisr = regs->ISR;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 752 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 /* Disable the transfer error interrupt */
<> 144:ef7eb2e8f9f7 757 hdma->Instance->CR &= ~(DMA_IT_TE);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 760 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Update error code */
<> 144:ef7eb2e8f9f7 763 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766 /* FIFO Error Interrupt management ******************************************/
<> 144:ef7eb2e8f9f7 767 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771 /* Clear the FIFO error flag */
<> 144:ef7eb2e8f9f7 772 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Update error code */
<> 144:ef7eb2e8f9f7 775 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 /* Direct Mode Error Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 779 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 /* Clear the direct mode error flag */
<> 144:ef7eb2e8f9f7 784 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Update error code */
<> 144:ef7eb2e8f9f7 787 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 /* Half Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 791 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 796 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Multi_Buffering mode enabled */
<> 144:ef7eb2e8f9f7 799 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* Current memory buffer used is Memory 0 */
<> 144:ef7eb2e8f9f7 802 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 807 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 /* Current memory buffer used is Memory 1 */
<> 144:ef7eb2e8f9f7 811 else
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 if(hdma->XferM1HalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 816 hdma->XferM1HalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 else
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 823 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* Disable the half transfer interrupt */
<> 144:ef7eb2e8f9f7 826 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Half transfer callback */
<> 144:ef7eb2e8f9f7 832 hdma->XferHalfCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 /* Transfer Complete Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 838 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 841 {
<> 144:ef7eb2e8f9f7 842 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 843 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 if(HAL_DMA_STATE_ABORT == hdma->State)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 /* Disable all the transfer interrupts */
<> 144:ef7eb2e8f9f7 848 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
<> 144:ef7eb2e8f9f7 849 hdma->Instance->FCR &= ~(DMA_IT_FE);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 hdma->Instance->CR &= ~(DMA_IT_HT);
<> 144:ef7eb2e8f9f7 854 }
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Clear all interrupt flags at correct offset within the register */
<> 144:ef7eb2e8f9f7 857 regs->IFCR = 0x3FU << hdma->StreamIndex;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 860 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 863 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 if(hdma->XferAbortCallback != NULL)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 hdma->XferAbortCallback(hdma);
<> 144:ef7eb2e8f9f7 868 }
<> 144:ef7eb2e8f9f7 869 return;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
<> 144:ef7eb2e8f9f7 873 {
<> 144:ef7eb2e8f9f7 874 /* Current memory buffer used is Memory 0 */
<> 144:ef7eb2e8f9f7 875 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 if(hdma->XferM1CpltCallback != NULL)
<> 144:ef7eb2e8f9f7 878 {
<> 144:ef7eb2e8f9f7 879 /* Transfer complete Callback for memory1 */
<> 144:ef7eb2e8f9f7 880 hdma->XferM1CpltCallback(hdma);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 /* Current memory buffer used is Memory 1 */
<> 144:ef7eb2e8f9f7 884 else
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 887 {
<> 144:ef7eb2e8f9f7 888 /* Transfer complete Callback for memory0 */
<> 144:ef7eb2e8f9f7 889 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892 }
<> 144:ef7eb2e8f9f7 893 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
<> 144:ef7eb2e8f9f7 894 else
<> 144:ef7eb2e8f9f7 895 {
<> 144:ef7eb2e8f9f7 896 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 899 hdma->Instance->CR &= ~(DMA_IT_TC);
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 902 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 905 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 if(hdma->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* Transfer complete callback */
<> 144:ef7eb2e8f9f7 911 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 912 }
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 }
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* manage error case */
<> 144:ef7eb2e8f9f7 918 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
<> 144:ef7eb2e8f9f7 921 {
<> 144:ef7eb2e8f9f7 922 hdma->State = HAL_DMA_STATE_ABORT;
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Disable the stream */
<> 144:ef7eb2e8f9f7 925 __HAL_DMA_DISABLE(hdma);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 do
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 if (++count > timeout)
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 break;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 937 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 940 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 if(hdma->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 /* Transfer error callback */
<> 144:ef7eb2e8f9f7 946 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @brief Register callbacks
<> 144:ef7eb2e8f9f7 953 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 954 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 955 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 956 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 957 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 144:ef7eb2e8f9f7 958 * a DMA_HandleTypeDef structure as parameter.
<> 144:ef7eb2e8f9f7 959 * @retval HAL status
<> 144:ef7eb2e8f9f7 960 */
<> 144:ef7eb2e8f9f7 961 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
<> 144:ef7eb2e8f9f7 962 {
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /* Process locked */
<> 144:ef7eb2e8f9f7 967 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 switch (CallbackID)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 974 hdma->XferCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 975 break;
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 978 hdma->XferHalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 979 break;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 case HAL_DMA_XFER_M1CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 982 hdma->XferM1CpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 983 break;
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 986 hdma->XferM1HalfCpltCallback = pCallback;
<> 144:ef7eb2e8f9f7 987 break;
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 990 hdma->XferErrorCallback = pCallback;
<> 144:ef7eb2e8f9f7 991 break;
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 994 hdma->XferAbortCallback = pCallback;
<> 144:ef7eb2e8f9f7 995 break;
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 default:
<> 144:ef7eb2e8f9f7 998 break;
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001 else
<> 144:ef7eb2e8f9f7 1002 {
<> 144:ef7eb2e8f9f7 1003 /* Return error status */
<> 144:ef7eb2e8f9f7 1004 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Release Lock */
<> 144:ef7eb2e8f9f7 1008 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 return status;
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /**
<> 144:ef7eb2e8f9f7 1014 * @brief UnRegister callbacks
<> 144:ef7eb2e8f9f7 1015 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1016 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1017 * @param CallbackID: User Callback identifer
<> 144:ef7eb2e8f9f7 1018 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 144:ef7eb2e8f9f7 1019 * @retval HAL status
<> 144:ef7eb2e8f9f7 1020 */
<> 144:ef7eb2e8f9f7 1021 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* Process locked */
<> 144:ef7eb2e8f9f7 1026 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 switch (CallbackID)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 case HAL_DMA_XFER_CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1033 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1034 break;
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1037 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1038 break;
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 case HAL_DMA_XFER_M1CPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1041 hdma->XferM1CpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1042 break;
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
<> 144:ef7eb2e8f9f7 1045 hdma->XferM1HalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1046 break;
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 case HAL_DMA_XFER_ERROR_CB_ID:
<> 144:ef7eb2e8f9f7 1049 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 1050 break;
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 case HAL_DMA_XFER_ABORT_CB_ID:
<> 144:ef7eb2e8f9f7 1053 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1054 break;
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 case HAL_DMA_XFER_ALL_CB_ID:
<> 144:ef7eb2e8f9f7 1057 hdma->XferCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1058 hdma->XferHalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1059 hdma->XferM1CpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1060 hdma->XferM1HalfCpltCallback = NULL;
<> 144:ef7eb2e8f9f7 1061 hdma->XferErrorCallback = NULL;
<> 144:ef7eb2e8f9f7 1062 hdma->XferAbortCallback = NULL;
<> 144:ef7eb2e8f9f7 1063 break;
<> 144:ef7eb2e8f9f7 1064
<> 144:ef7eb2e8f9f7 1065 default:
<> 144:ef7eb2e8f9f7 1066 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1067 break;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 else
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Release Lock */
<> 144:ef7eb2e8f9f7 1076 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 return status;
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /**
<> 144:ef7eb2e8f9f7 1082 * @}
<> 144:ef7eb2e8f9f7 1083 */
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1086 *
<> 144:ef7eb2e8f9f7 1087 @verbatim
<> 144:ef7eb2e8f9f7 1088 ===============================================================================
<> 144:ef7eb2e8f9f7 1089 ##### State and Errors functions #####
<> 144:ef7eb2e8f9f7 1090 ===============================================================================
<> 144:ef7eb2e8f9f7 1091 [..]
<> 144:ef7eb2e8f9f7 1092 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 1093 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 1094 (+) Get error code
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 @endverbatim
<> 144:ef7eb2e8f9f7 1097 * @{
<> 144:ef7eb2e8f9f7 1098 */
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /**
<> 144:ef7eb2e8f9f7 1101 * @brief Returns the DMA state.
<> 144:ef7eb2e8f9f7 1102 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1103 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1104 * @retval HAL state
<> 144:ef7eb2e8f9f7 1105 */
<> 144:ef7eb2e8f9f7 1106 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 return hdma->State;
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /**
<> 144:ef7eb2e8f9f7 1112 * @brief Return the DMA error code
<> 144:ef7eb2e8f9f7 1113 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1114 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1115 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1118 {
<> 144:ef7eb2e8f9f7 1119 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @}
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /**
<> 144:ef7eb2e8f9f7 1127 * @}
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 1131 * @{
<> 144:ef7eb2e8f9f7 1132 */
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 1136 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1137 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1138 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 1139 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 1140 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 1141 * @retval HAL status
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 /* Clear DBM bit */
<> 144:ef7eb2e8f9f7 1146 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /* Configure DMA Stream data length */
<> 144:ef7eb2e8f9f7 1149 hdma->Instance->NDTR = DataLength;
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 1152 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 1155 hdma->Instance->PAR = DstAddress;
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 1158 hdma->Instance->M0AR = SrcAddress;
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 1161 else
<> 144:ef7eb2e8f9f7 1162 {
<> 144:ef7eb2e8f9f7 1163 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 1164 hdma->Instance->PAR = SrcAddress;
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 1167 hdma->Instance->M0AR = DstAddress;
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /**
<> 144:ef7eb2e8f9f7 1172 * @brief Returns the DMA Stream base address depending on stream number
<> 144:ef7eb2e8f9f7 1173 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1174 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1175 * @retval Stream base address
<> 144:ef7eb2e8f9f7 1176 */
<> 144:ef7eb2e8f9f7 1177 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* lookup table for necessary bitshift of flags within status registers */
<> 144:ef7eb2e8f9f7 1182 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
<> 144:ef7eb2e8f9f7 1183 hdma->StreamIndex = flagBitshiftOffset[stream_number];
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 if (stream_number > 3U)
<> 144:ef7eb2e8f9f7 1186 {
<> 144:ef7eb2e8f9f7 1187 /* return pointer to HISR and HIFCR */
<> 144:ef7eb2e8f9f7 1188 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
<> 144:ef7eb2e8f9f7 1189 }
<> 144:ef7eb2e8f9f7 1190 else
<> 144:ef7eb2e8f9f7 1191 {
<> 144:ef7eb2e8f9f7 1192 /* return pointer to LISR and LIFCR */
<> 144:ef7eb2e8f9f7 1193 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 return hdma->StreamBaseAddress;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /**
<> 144:ef7eb2e8f9f7 1200 * @brief Check compatibility between FIFO threshold level and size of the memory burst
<> 144:ef7eb2e8f9f7 1201 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1202 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 1203 * @retval HAL status
<> 144:ef7eb2e8f9f7 1204 */
<> 144:ef7eb2e8f9f7 1205 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1206 {
<> 144:ef7eb2e8f9f7 1207 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1208 uint32_t tmp = hdma->Init.FIFOThreshold;
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Memory Data size equal to Byte */
<> 144:ef7eb2e8f9f7 1211 if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
<> 144:ef7eb2e8f9f7 1212 {
<> 144:ef7eb2e8f9f7 1213 switch (tmp)
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<> 144:ef7eb2e8f9f7 1216 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<> 144:ef7eb2e8f9f7 1217 {
<> 144:ef7eb2e8f9f7 1218 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220 break;
<> 144:ef7eb2e8f9f7 1221 case DMA_FIFO_THRESHOLD_HALFFULL:
<> 144:ef7eb2e8f9f7 1222 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
<> 144:ef7eb2e8f9f7 1223 {
<> 144:ef7eb2e8f9f7 1224 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1225 }
<> 144:ef7eb2e8f9f7 1226 break;
<> 144:ef7eb2e8f9f7 1227 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<> 144:ef7eb2e8f9f7 1228 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<> 144:ef7eb2e8f9f7 1229 {
<> 144:ef7eb2e8f9f7 1230 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1231 }
<> 144:ef7eb2e8f9f7 1232 break;
<> 144:ef7eb2e8f9f7 1233 case DMA_FIFO_THRESHOLD_FULL:
<> 144:ef7eb2e8f9f7 1234 break;
<> 144:ef7eb2e8f9f7 1235 default:
<> 144:ef7eb2e8f9f7 1236 break;
<> 144:ef7eb2e8f9f7 1237 }
<> 144:ef7eb2e8f9f7 1238 }
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Memory Data size equal to Half-Word */
<> 144:ef7eb2e8f9f7 1241 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 switch (tmp)
<> 144:ef7eb2e8f9f7 1244 {
<> 144:ef7eb2e8f9f7 1245 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<> 144:ef7eb2e8f9f7 1246 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1247 break;
<> 144:ef7eb2e8f9f7 1248 case DMA_FIFO_THRESHOLD_HALFFULL:
<> 144:ef7eb2e8f9f7 1249 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<> 144:ef7eb2e8f9f7 1250 {
<> 144:ef7eb2e8f9f7 1251 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 break;
<> 144:ef7eb2e8f9f7 1254 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<> 144:ef7eb2e8f9f7 1255 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1256 break;
<> 144:ef7eb2e8f9f7 1257 case DMA_FIFO_THRESHOLD_FULL:
<> 144:ef7eb2e8f9f7 1258 if (hdma->Init.MemBurst == DMA_MBURST_INC16)
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262 break;
<> 144:ef7eb2e8f9f7 1263 default:
<> 144:ef7eb2e8f9f7 1264 break;
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Memory Data size equal to Word */
<> 144:ef7eb2e8f9f7 1269 else
<> 144:ef7eb2e8f9f7 1270 {
<> 144:ef7eb2e8f9f7 1271 switch (tmp)
<> 144:ef7eb2e8f9f7 1272 {
<> 144:ef7eb2e8f9f7 1273 case DMA_FIFO_THRESHOLD_1QUARTERFULL:
<> 144:ef7eb2e8f9f7 1274 case DMA_FIFO_THRESHOLD_HALFFULL:
<> 144:ef7eb2e8f9f7 1275 case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
<> 144:ef7eb2e8f9f7 1276 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1277 break;
<> 144:ef7eb2e8f9f7 1278 case DMA_FIFO_THRESHOLD_FULL:
<> 144:ef7eb2e8f9f7 1279 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
<> 144:ef7eb2e8f9f7 1280 {
<> 144:ef7eb2e8f9f7 1281 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1282 }
<> 144:ef7eb2e8f9f7 1283 break;
<> 144:ef7eb2e8f9f7 1284 default:
<> 144:ef7eb2e8f9f7 1285 break;
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287 }
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 return status;
<> 144:ef7eb2e8f9f7 1290 }
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /**
<> 144:ef7eb2e8f9f7 1293 * @}
<> 144:ef7eb2e8f9f7 1294 */
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1297 /**
<> 144:ef7eb2e8f9f7 1298 * @}
<> 144:ef7eb2e8f9f7 1299 */
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /**
<> 144:ef7eb2e8f9f7 1302 * @}
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/