Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dfsdm.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DFSDM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_DFSDM_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_DFSDM_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup DFSDM
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL DFSDM Channel states definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
<> 144:ef7eb2e8f9f7 69 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
<> 144:ef7eb2e8f9f7 70 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
<> 144:ef7eb2e8f9f7 71 }HAL_DFSDM_Channel_StateTypeDef;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /**
<> 144:ef7eb2e8f9f7 74 * @brief DFSDM channel output clock structure definition
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 typedef struct
<> 144:ef7eb2e8f9f7 77 {
<> 144:ef7eb2e8f9f7 78 FunctionalState Activation; /*!< Output clock enable/disable */
<> 144:ef7eb2e8f9f7 79 uint32_t Selection; /*!< Output clock is system clock or audio clock.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref DFSDM_Channel_OuputClock */
<> 144:ef7eb2e8f9f7 81 uint32_t Divider; /*!< Output clock divider.
<> 144:ef7eb2e8f9f7 82 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
<> 144:ef7eb2e8f9f7 83 }DFSDM_Channel_OutputClockTypeDef;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @brief DFSDM channel input structure definition
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 typedef struct
<> 144:ef7eb2e8f9f7 89 {
<> 144:ef7eb2e8f9f7 90 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
<> 144:ef7eb2e8f9f7 92 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref DFSDM_Channel_DataPacking */
<> 144:ef7eb2e8f9f7 94 uint32_t Pins; /*!< Input pins are taken from same or following channel.
<> 144:ef7eb2e8f9f7 95 This parameter can be a value of @ref DFSDM_Channel_InputPins */
<> 144:ef7eb2e8f9f7 96 }DFSDM_Channel_InputTypeDef;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /**
<> 144:ef7eb2e8f9f7 99 * @brief DFSDM channel serial interface structure definition
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 typedef struct
<> 144:ef7eb2e8f9f7 102 {
<> 144:ef7eb2e8f9f7 103 uint32_t Type; /*!< SPI or Manchester modes.
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
<> 144:ef7eb2e8f9f7 105 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref DFSDM_Channel_SpiClock */
<> 144:ef7eb2e8f9f7 107 }DFSDM_Channel_SerialInterfaceTypeDef;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @brief DFSDM channel analog watchdog structure definition
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112 typedef struct
<> 144:ef7eb2e8f9f7 113 {
<> 144:ef7eb2e8f9f7 114 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
<> 144:ef7eb2e8f9f7 115 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
<> 144:ef7eb2e8f9f7 116 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
<> 144:ef7eb2e8f9f7 117 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 118 }DFSDM_Channel_AwdTypeDef;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief DFSDM channel init structure definition
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 typedef struct
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
<> 144:ef7eb2e8f9f7 126 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
<> 144:ef7eb2e8f9f7 127 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
<> 144:ef7eb2e8f9f7 128 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
<> 144:ef7eb2e8f9f7 129 int32_t Offset; /*!< DFSDM channel offset.
<> 144:ef7eb2e8f9f7 130 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<> 144:ef7eb2e8f9f7 131 uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
<> 144:ef7eb2e8f9f7 132 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<> 144:ef7eb2e8f9f7 133 }DFSDM_Channel_InitTypeDef;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @brief DFSDM channel handle structure definition
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 typedef struct
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
<> 144:ef7eb2e8f9f7 141 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
<> 144:ef7eb2e8f9f7 142 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
<> 144:ef7eb2e8f9f7 143 }DFSDM_Channel_HandleTypeDef;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @brief HAL DFSDM Filter states definition
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 typedef enum
<> 144:ef7eb2e8f9f7 149 {
<> 144:ef7eb2e8f9f7 150 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
<> 144:ef7eb2e8f9f7 151 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
<> 144:ef7eb2e8f9f7 152 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
<> 144:ef7eb2e8f9f7 153 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
<> 144:ef7eb2e8f9f7 154 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
<> 144:ef7eb2e8f9f7 155 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
<> 144:ef7eb2e8f9f7 156 }HAL_DFSDM_Filter_StateTypeDef;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @brief DFSDM filter regular conversion parameters structure definition
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 typedef struct
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
<> 144:ef7eb2e8f9f7 164 This parameter can be a value of @ref DFSDM_Filter_Trigger */
<> 144:ef7eb2e8f9f7 165 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
<> 144:ef7eb2e8f9f7 166 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
<> 144:ef7eb2e8f9f7 167 }DFSDM_Filter_RegularParamTypeDef;
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @brief DFSDM filter injected conversion parameters structure definition
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 typedef struct
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
<> 144:ef7eb2e8f9f7 175 This parameter can be a value of @ref DFSDM_Filter_Trigger */
<> 144:ef7eb2e8f9f7 176 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
<> 144:ef7eb2e8f9f7 177 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
<> 144:ef7eb2e8f9f7 178 uint32_t ExtTrigger; /*!< External trigger.
<> 144:ef7eb2e8f9f7 179 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
<> 144:ef7eb2e8f9f7 180 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
<> 144:ef7eb2e8f9f7 181 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
<> 144:ef7eb2e8f9f7 182 }DFSDM_Filter_InjectedParamTypeDef;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @brief DFSDM filter parameters structure definition
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 typedef struct
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 uint32_t SincOrder; /*!< Sinc filter order.
<> 144:ef7eb2e8f9f7 190 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
<> 144:ef7eb2e8f9f7 191 uint32_t Oversampling; /*!< Filter oversampling ratio.
<> 144:ef7eb2e8f9f7 192 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
<> 144:ef7eb2e8f9f7 193 uint32_t IntOversampling; /*!< Integrator oversampling ratio.
<> 144:ef7eb2e8f9f7 194 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
<> 144:ef7eb2e8f9f7 195 }DFSDM_Filter_FilterParamTypeDef;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @brief DFSDM filter init structure definition
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 typedef struct
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
<> 144:ef7eb2e8f9f7 203 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
<> 144:ef7eb2e8f9f7 204 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
<> 144:ef7eb2e8f9f7 205 }DFSDM_Filter_InitTypeDef;
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief DFSDM filter handle structure definition
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210 typedef struct
<> 144:ef7eb2e8f9f7 211 {
<> 144:ef7eb2e8f9f7 212 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
<> 144:ef7eb2e8f9f7 213 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
<> 144:ef7eb2e8f9f7 214 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
<> 144:ef7eb2e8f9f7 215 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
<> 144:ef7eb2e8f9f7 216 uint32_t RegularContMode; /*!< Regular conversion continuous mode */
<> 144:ef7eb2e8f9f7 217 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
<> 144:ef7eb2e8f9f7 218 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
<> 144:ef7eb2e8f9f7 219 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
<> 144:ef7eb2e8f9f7 220 FunctionalState InjectedScanMode; /*!< Injected scanning mode */
<> 144:ef7eb2e8f9f7 221 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
<> 144:ef7eb2e8f9f7 222 uint32_t InjConvRemaining; /*!< Injected conversions remaining */
<> 144:ef7eb2e8f9f7 223 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
<> 144:ef7eb2e8f9f7 224 uint32_t ErrorCode; /*!< DFSDM filter error code */
<> 144:ef7eb2e8f9f7 225 }DFSDM_Filter_HandleTypeDef;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief DFSDM filter analog watchdog parameters structure definition
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 typedef struct
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
<> 144:ef7eb2e8f9f7 233 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
<> 144:ef7eb2e8f9f7 234 uint32_t Channel; /*!< Analog watchdog channel selection.
<> 144:ef7eb2e8f9f7 235 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
<> 144:ef7eb2e8f9f7 236 int32_t HighThreshold; /*!< High threshold for the analog watchdog.
<> 144:ef7eb2e8f9f7 237 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<> 144:ef7eb2e8f9f7 238 int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
<> 144:ef7eb2e8f9f7 239 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
<> 144:ef7eb2e8f9f7 240 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
<> 144:ef7eb2e8f9f7 241 This parameter can be a values combination of @ref DFSDM_BreakSignals */
<> 144:ef7eb2e8f9f7 242 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
<> 144:ef7eb2e8f9f7 243 This parameter can be a values combination of @ref DFSDM_BreakSignals */
<> 144:ef7eb2e8f9f7 244 }DFSDM_Filter_AwdParamTypeDef;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @}
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 /* End of exported types -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 252 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
<> 144:ef7eb2e8f9f7 257 * @{
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
<> 144:ef7eb2e8f9f7 260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
<> 144:ef7eb2e8f9f7 269 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @}
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
<> 144:ef7eb2e8f9f7 275 * @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
<> 144:ef7eb2e8f9f7 278 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
<> 144:ef7eb2e8f9f7 279 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
<> 144:ef7eb2e8f9f7 280 /**
<> 144:ef7eb2e8f9f7 281 * @}
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
<> 144:ef7eb2e8f9f7 285 * @{
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
<> 144:ef7eb2e8f9f7 288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
<> 144:ef7eb2e8f9f7 297 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
<> 144:ef7eb2e8f9f7 298 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
<> 144:ef7eb2e8f9f7 299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
<> 144:ef7eb2e8f9f7 308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
<> 144:ef7eb2e8f9f7 309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
<> 144:ef7eb2e8f9f7 310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
<> 144:ef7eb2e8f9f7 311 /**
<> 144:ef7eb2e8f9f7 312 * @}
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
<> 144:ef7eb2e8f9f7 316 * @{
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
<> 144:ef7eb2e8f9f7 319 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
<> 144:ef7eb2e8f9f7 320 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
<> 144:ef7eb2e8f9f7 321 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
<> 144:ef7eb2e8f9f7 330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
<> 144:ef7eb2e8f9f7 331 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
<> 144:ef7eb2e8f9f7 337 * @{
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 345 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
<> 144:ef7eb2e8f9f7 347 DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 348 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 349 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 350 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
<> 144:ef7eb2e8f9f7 351 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 352 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
<> 144:ef7eb2e8f9f7 353 DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @}
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
<> 144:ef7eb2e8f9f7 359 * @{
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
<> 144:ef7eb2e8f9f7 362 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
<> 144:ef7eb2e8f9f7 363 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @}
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
<> 144:ef7eb2e8f9f7 369 * @{
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
<> 144:ef7eb2e8f9f7 372 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
<> 144:ef7eb2e8f9f7 373 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
<> 144:ef7eb2e8f9f7 374 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
<> 144:ef7eb2e8f9f7 375 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
<> 144:ef7eb2e8f9f7 376 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @}
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
<> 144:ef7eb2e8f9f7 382 * @{
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
<> 144:ef7eb2e8f9f7 385 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
<> 144:ef7eb2e8f9f7 386 /**
<> 144:ef7eb2e8f9f7 387 * @}
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
<> 144:ef7eb2e8f9f7 391 * @{
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 144:ef7eb2e8f9f7 394 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
<> 144:ef7eb2e8f9f7 395 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
<> 144:ef7eb2e8f9f7 396 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @}
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @defgroup DFSDM_BreakSignals DFSDM break signals
<> 144:ef7eb2e8f9f7 402 * @{
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
<> 144:ef7eb2e8f9f7 405 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
<> 144:ef7eb2e8f9f7 406 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
<> 144:ef7eb2e8f9f7 407 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
<> 144:ef7eb2e8f9f7 408 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @}
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
<> 144:ef7eb2e8f9f7 414 * @{
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 /* DFSDM Channels ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 417 /* The DFSDM channels are defined as follows:
<> 144:ef7eb2e8f9f7 418 - in 16-bit LSB the channel mask is set
<> 144:ef7eb2e8f9f7 419 - in 16-bit MSB the channel number is set
<> 144:ef7eb2e8f9f7 420 e.g. for channel 5 definition:
<> 144:ef7eb2e8f9f7 421 - the channel mask is 0x00000020 (bit 5 is set)
<> 144:ef7eb2e8f9f7 422 - the channel number 5 is 0x00050000
<> 144:ef7eb2e8f9f7 423 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
<> 144:ef7eb2e8f9f7 424 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 425 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
<> 144:ef7eb2e8f9f7 426 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
<> 144:ef7eb2e8f9f7 427 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
<> 144:ef7eb2e8f9f7 428 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
<> 144:ef7eb2e8f9f7 429 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
<> 144:ef7eb2e8f9f7 430 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
<> 144:ef7eb2e8f9f7 431 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
<> 144:ef7eb2e8f9f7 432 /**
<> 144:ef7eb2e8f9f7 433 * @}
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
<> 144:ef7eb2e8f9f7 437 * @{
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
<> 144:ef7eb2e8f9f7 440 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @}
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
<> 144:ef7eb2e8f9f7 446 * @{
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
<> 144:ef7eb2e8f9f7 449 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @}
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 /* End of exported constants -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 460 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
<> 144:ef7eb2e8f9f7 461 * @{
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /** @brief Reset DFSDM channel handle state.
<> 144:ef7eb2e8f9f7 465 * @param __HANDLE__: DFSDM channel handle.
<> 144:ef7eb2e8f9f7 466 * @retval None
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /** @brief Reset DFSDM filter handle state.
<> 144:ef7eb2e8f9f7 471 * @param __HANDLE__: DFSDM filter handle.
<> 144:ef7eb2e8f9f7 472 * @retval None
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479 /* End of exported macros ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 482 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
<> 144:ef7eb2e8f9f7 483 * @{
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 487 * @{
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489 /* Channel initialization and de-initialization functions *********************/
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 492 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 493 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @}
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
<> 144:ef7eb2e8f9f7 499 * @{
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 /* Channel operation functions ************************************************/
<> 144:ef7eb2e8f9f7 502 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 503 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 504 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 505 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
<> 144:ef7eb2e8f9f7 508 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
<> 144:ef7eb2e8f9f7 509 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 510 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 513 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 516 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 519 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @}
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
<> 144:ef7eb2e8f9f7 525 * @{
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 /* Channel state function *****************************************************/
<> 144:ef7eb2e8f9f7 528 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @}
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 534 * @{
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536 /* Filter initialization and de-initialization functions *********************/
<> 144:ef7eb2e8f9f7 537 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 538 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 539 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 540 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @}
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
<> 144:ef7eb2e8f9f7 546 * @{
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 /* Filter control functions *********************/
<> 144:ef7eb2e8f9f7 549 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 550 uint32_t Channel,
<> 144:ef7eb2e8f9f7 551 uint32_t ContinuousMode);
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 553 uint32_t Channel);
<> 144:ef7eb2e8f9f7 554 /**
<> 144:ef7eb2e8f9f7 555 * @}
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
<> 144:ef7eb2e8f9f7 559 * @{
<> 144:ef7eb2e8f9f7 560 */
<> 144:ef7eb2e8f9f7 561 /* Filter operation functions *********************/
<> 144:ef7eb2e8f9f7 562 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 564 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 565 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 566 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 567 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 568 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 569 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 571 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 572 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 573 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 574 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 575 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 576 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 577 DFSDM_Filter_AwdParamTypeDef* awdParam);
<> 144:ef7eb2e8f9f7 578 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 579 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
<> 144:ef7eb2e8f9f7 580 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
<> 144:ef7eb2e8f9f7 583 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
<> 144:ef7eb2e8f9f7 584 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
<> 144:ef7eb2e8f9f7 585 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
<> 144:ef7eb2e8f9f7 586 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 591 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 594 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 595 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 596 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 597 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
<> 144:ef7eb2e8f9f7 598 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 599 /**
<> 144:ef7eb2e8f9f7 600 * @}
<> 144:ef7eb2e8f9f7 601 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
<> 144:ef7eb2e8f9f7 604 * @{
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 /* Filter state functions *****************************************************/
<> 144:ef7eb2e8f9f7 607 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 608 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 609 /**
<> 144:ef7eb2e8f9f7 610 * @}
<> 144:ef7eb2e8f9f7 611 */
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @}
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616 /* End of exported functions -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 619 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
<> 144:ef7eb2e8f9f7 620 * @{
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
<> 144:ef7eb2e8f9f7 623 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
<> 144:ef7eb2e8f9f7 624 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
<> 144:ef7eb2e8f9f7 625 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
<> 144:ef7eb2e8f9f7 626 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
<> 144:ef7eb2e8f9f7 627 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
<> 144:ef7eb2e8f9f7 628 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
<> 144:ef7eb2e8f9f7 629 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
<> 144:ef7eb2e8f9f7 630 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
<> 144:ef7eb2e8f9f7 631 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
<> 144:ef7eb2e8f9f7 632 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
<> 144:ef7eb2e8f9f7 633 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
<> 144:ef7eb2e8f9f7 634 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
<> 144:ef7eb2e8f9f7 635 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
<> 144:ef7eb2e8f9f7 636 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
<> 144:ef7eb2e8f9f7 637 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
<> 144:ef7eb2e8f9f7 638 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
<> 144:ef7eb2e8f9f7 639 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
<> 144:ef7eb2e8f9f7 640 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
<> 144:ef7eb2e8f9f7 641 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
<> 144:ef7eb2e8f9f7 642 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
<> 144:ef7eb2e8f9f7 643 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
<> 144:ef7eb2e8f9f7 644 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
<> 144:ef7eb2e8f9f7 645 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
<> 144:ef7eb2e8f9f7 646 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
<> 144:ef7eb2e8f9f7 647 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
<> 144:ef7eb2e8f9f7 648 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
<> 144:ef7eb2e8f9f7 649 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
<> 144:ef7eb2e8f9f7 650 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
<> 144:ef7eb2e8f9f7 651 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
<> 144:ef7eb2e8f9f7 652 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
<> 144:ef7eb2e8f9f7 653 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
<> 144:ef7eb2e8f9f7 654 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
<> 144:ef7eb2e8f9f7 655 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
<> 144:ef7eb2e8f9f7 656 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
<> 144:ef7eb2e8f9f7 657 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
<> 144:ef7eb2e8f9f7 658 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
<> 144:ef7eb2e8f9f7 659 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
<> 144:ef7eb2e8f9f7 660 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
<> 144:ef7eb2e8f9f7 661 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
<> 144:ef7eb2e8f9f7 662 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
<> 144:ef7eb2e8f9f7 663 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
<> 144:ef7eb2e8f9f7 664 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
<> 144:ef7eb2e8f9f7 665 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
<> 144:ef7eb2e8f9f7 666 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
<> 144:ef7eb2e8f9f7 667 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
<> 144:ef7eb2e8f9f7 668 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
<> 144:ef7eb2e8f9f7 669 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
<> 144:ef7eb2e8f9f7 670 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
<> 144:ef7eb2e8f9f7 671 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
<> 144:ef7eb2e8f9f7 672 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
<> 144:ef7eb2e8f9f7 673 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
<> 144:ef7eb2e8f9f7 674 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
<> 144:ef7eb2e8f9f7 675 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
<> 144:ef7eb2e8f9f7 676 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
<> 144:ef7eb2e8f9f7 677 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
<> 144:ef7eb2e8f9f7 678 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
<> 144:ef7eb2e8f9f7 679 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
<> 144:ef7eb2e8f9f7 680 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 681 ((CHANNEL) == DFSDM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 682 ((CHANNEL) == DFSDM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 683 ((CHANNEL) == DFSDM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 684 ((CHANNEL) == DFSDM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 685 ((CHANNEL) == DFSDM_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 686 ((CHANNEL) == DFSDM_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 687 ((CHANNEL) == DFSDM_CHANNEL_7))
<> 144:ef7eb2e8f9f7 688 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
<> 144:ef7eb2e8f9f7 689 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
<> 144:ef7eb2e8f9f7 690 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @}
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 /* End of private macros -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /**
<> 144:ef7eb2e8f9f7 701 * @}
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 704 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 #endif
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 #endif /* __STM32F7xx_HAL_DFSDM_H */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/