Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_cortex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of CORTEX HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_CORTEX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_CORTEX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup CORTEX
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 62 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
<> 144:ef7eb2e8f9f7 63 * @brief MPU Region initialization structure
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint8_t Enable; /*!< Specifies the status of the region.
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
<> 144:ef7eb2e8f9f7 70 uint8_t Number; /*!< Specifies the number of the region to protect.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref CORTEX_MPU_Region_Number */
<> 144:ef7eb2e8f9f7 72 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
<> 144:ef7eb2e8f9f7 73 uint8_t Size; /*!< Specifies the size of the region to protect.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref CORTEX_MPU_Region_Size */
<> 144:ef7eb2e8f9f7 75 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
<> 144:ef7eb2e8f9f7 76 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 77 uint8_t TypeExtField; /*!< Specifies the TEX field level.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
<> 144:ef7eb2e8f9f7 79 uint8_t AccessPermission; /*!< Specifies the region access permission type.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
<> 144:ef7eb2e8f9f7 81 uint8_t DisableExec; /*!< Specifies the instruction access status.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
<> 144:ef7eb2e8f9f7 83 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
<> 144:ef7eb2e8f9f7 85 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
<> 144:ef7eb2e8f9f7 87 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
<> 144:ef7eb2e8f9f7 89 }MPU_Region_InitTypeDef;
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @}
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 109 4 bits for subpriority */
<> 144:ef7eb2e8f9f7 110 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 111 3 bits for subpriority */
<> 144:ef7eb2e8f9f7 112 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 113 2 bits for subpriority */
<> 144:ef7eb2e8f9f7 114 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 115 1 bits for subpriority */
<> 144:ef7eb2e8f9f7 116 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 117 0 bits for subpriority */
<> 144:ef7eb2e8f9f7 118 /**
<> 144:ef7eb2e8f9f7 119 * @}
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 126 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /**
<> 144:ef7eb2e8f9f7 129 * @}
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 137 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 138 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 139 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
<> 144:ef7eb2e8f9f7 145 * @{
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 #define MPU_REGION_ENABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 148 #define MPU_REGION_DISABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 157 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @}
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
<> 144:ef7eb2e8f9f7 163 * @{
<> 144:ef7eb2e8f9f7 164 */
<> 144:ef7eb2e8f9f7 165 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 166 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 175 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 184 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192 #define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 193 #define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 194 #define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
<> 144:ef7eb2e8f9f7 203 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
<> 144:ef7eb2e8f9f7 204 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
<> 144:ef7eb2e8f9f7 205 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 206 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
<> 144:ef7eb2e8f9f7 207 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
<> 144:ef7eb2e8f9f7 208 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
<> 144:ef7eb2e8f9f7 209 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
<> 144:ef7eb2e8f9f7 210 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
<> 144:ef7eb2e8f9f7 211 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
<> 144:ef7eb2e8f9f7 212 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
<> 144:ef7eb2e8f9f7 213 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
<> 144:ef7eb2e8f9f7 214 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
<> 144:ef7eb2e8f9f7 215 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
<> 144:ef7eb2e8f9f7 216 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
<> 144:ef7eb2e8f9f7 217 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
<> 144:ef7eb2e8f9f7 218 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
<> 144:ef7eb2e8f9f7 219 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
<> 144:ef7eb2e8f9f7 220 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
<> 144:ef7eb2e8f9f7 221 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
<> 144:ef7eb2e8f9f7 222 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
<> 144:ef7eb2e8f9f7 223 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
<> 144:ef7eb2e8f9f7 224 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
<> 144:ef7eb2e8f9f7 225 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
<> 144:ef7eb2e8f9f7 226 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
<> 144:ef7eb2e8f9f7 227 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
<> 144:ef7eb2e8f9f7 228 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
<> 144:ef7eb2e8f9f7 229 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
<> 144:ef7eb2e8f9f7 235 * @{
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 238 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 239 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
<> 144:ef7eb2e8f9f7 240 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
<> 144:ef7eb2e8f9f7 241 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
<> 144:ef7eb2e8f9f7 242 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @}
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
<> 144:ef7eb2e8f9f7 248 * @{
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
<> 144:ef7eb2e8f9f7 251 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
<> 144:ef7eb2e8f9f7 252 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
<> 144:ef7eb2e8f9f7 253 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
<> 144:ef7eb2e8f9f7 254 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
<> 144:ef7eb2e8f9f7 255 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
<> 144:ef7eb2e8f9f7 256 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
<> 144:ef7eb2e8f9f7 257 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @}
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Exported Macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 271 /** @addtogroup CORTEX_Exported_Functions
<> 144:ef7eb2e8f9f7 272 * @{
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /** @addtogroup CORTEX_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 279 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
<> 144:ef7eb2e8f9f7 280 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
<> 144:ef7eb2e8f9f7 281 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 282 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 283 void HAL_NVIC_SystemReset(void);
<> 144:ef7eb2e8f9f7 284 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @addtogroup CORTEX_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 293 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 294 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
<> 144:ef7eb2e8f9f7 295 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 296 uint32_t HAL_NVIC_GetPriorityGrouping(void);
<> 144:ef7eb2e8f9f7 297 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
<> 144:ef7eb2e8f9f7 298 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 299 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 300 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 301 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
<> 144:ef7eb2e8f9f7 302 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
<> 144:ef7eb2e8f9f7 303 void HAL_SYSTICK_IRQHandler(void);
<> 144:ef7eb2e8f9f7 304 void HAL_SYSTICK_Callback(void);
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 314 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 315 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 316 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 317 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
<> 144:ef7eb2e8f9f7 321 ((GROUP) == NVIC_PRIORITYGROUP_1) || \
<> 144:ef7eb2e8f9f7 322 ((GROUP) == NVIC_PRIORITYGROUP_2) || \
<> 144:ef7eb2e8f9f7 323 ((GROUP) == NVIC_PRIORITYGROUP_3) || \
<> 144:ef7eb2e8f9f7 324 ((GROUP) == NVIC_PRIORITYGROUP_4))
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
<> 144:ef7eb2e8f9f7 333 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 336 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
<> 144:ef7eb2e8f9f7 337 ((STATE) == MPU_REGION_DISABLE))
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
<> 144:ef7eb2e8f9f7 340 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
<> 144:ef7eb2e8f9f7 343 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
<> 144:ef7eb2e8f9f7 346 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
<> 144:ef7eb2e8f9f7 349 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
<> 144:ef7eb2e8f9f7 352 ((TYPE) == MPU_TEX_LEVEL1) || \
<> 144:ef7eb2e8f9f7 353 ((TYPE) == MPU_TEX_LEVEL2))
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
<> 144:ef7eb2e8f9f7 356 ((TYPE) == MPU_REGION_PRIV_RW) || \
<> 144:ef7eb2e8f9f7 357 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
<> 144:ef7eb2e8f9f7 358 ((TYPE) == MPU_REGION_FULL_ACCESS) || \
<> 144:ef7eb2e8f9f7 359 ((TYPE) == MPU_REGION_PRIV_RO) || \
<> 144:ef7eb2e8f9f7 360 ((TYPE) == MPU_REGION_PRIV_RO_URO))
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
<> 144:ef7eb2e8f9f7 363 ((NUMBER) == MPU_REGION_NUMBER1) || \
<> 144:ef7eb2e8f9f7 364 ((NUMBER) == MPU_REGION_NUMBER2) || \
<> 144:ef7eb2e8f9f7 365 ((NUMBER) == MPU_REGION_NUMBER3) || \
<> 144:ef7eb2e8f9f7 366 ((NUMBER) == MPU_REGION_NUMBER4) || \
<> 144:ef7eb2e8f9f7 367 ((NUMBER) == MPU_REGION_NUMBER5) || \
<> 144:ef7eb2e8f9f7 368 ((NUMBER) == MPU_REGION_NUMBER6) || \
<> 144:ef7eb2e8f9f7 369 ((NUMBER) == MPU_REGION_NUMBER7))
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
<> 144:ef7eb2e8f9f7 372 ((SIZE) == MPU_REGION_SIZE_64B) || \
<> 144:ef7eb2e8f9f7 373 ((SIZE) == MPU_REGION_SIZE_128B) || \
<> 144:ef7eb2e8f9f7 374 ((SIZE) == MPU_REGION_SIZE_256B) || \
<> 144:ef7eb2e8f9f7 375 ((SIZE) == MPU_REGION_SIZE_512B) || \
<> 144:ef7eb2e8f9f7 376 ((SIZE) == MPU_REGION_SIZE_1KB) || \
<> 144:ef7eb2e8f9f7 377 ((SIZE) == MPU_REGION_SIZE_2KB) || \
<> 144:ef7eb2e8f9f7 378 ((SIZE) == MPU_REGION_SIZE_4KB) || \
<> 144:ef7eb2e8f9f7 379 ((SIZE) == MPU_REGION_SIZE_8KB) || \
<> 144:ef7eb2e8f9f7 380 ((SIZE) == MPU_REGION_SIZE_16KB) || \
<> 144:ef7eb2e8f9f7 381 ((SIZE) == MPU_REGION_SIZE_32KB) || \
<> 144:ef7eb2e8f9f7 382 ((SIZE) == MPU_REGION_SIZE_64KB) || \
<> 144:ef7eb2e8f9f7 383 ((SIZE) == MPU_REGION_SIZE_128KB) || \
<> 144:ef7eb2e8f9f7 384 ((SIZE) == MPU_REGION_SIZE_256KB) || \
<> 144:ef7eb2e8f9f7 385 ((SIZE) == MPU_REGION_SIZE_512KB) || \
<> 144:ef7eb2e8f9f7 386 ((SIZE) == MPU_REGION_SIZE_1MB) || \
<> 144:ef7eb2e8f9f7 387 ((SIZE) == MPU_REGION_SIZE_2MB) || \
<> 144:ef7eb2e8f9f7 388 ((SIZE) == MPU_REGION_SIZE_4MB) || \
<> 144:ef7eb2e8f9f7 389 ((SIZE) == MPU_REGION_SIZE_8MB) || \
<> 144:ef7eb2e8f9f7 390 ((SIZE) == MPU_REGION_SIZE_16MB) || \
<> 144:ef7eb2e8f9f7 391 ((SIZE) == MPU_REGION_SIZE_32MB) || \
<> 144:ef7eb2e8f9f7 392 ((SIZE) == MPU_REGION_SIZE_64MB) || \
<> 144:ef7eb2e8f9f7 393 ((SIZE) == MPU_REGION_SIZE_128MB) || \
<> 144:ef7eb2e8f9f7 394 ((SIZE) == MPU_REGION_SIZE_256MB) || \
<> 144:ef7eb2e8f9f7 395 ((SIZE) == MPU_REGION_SIZE_512MB) || \
<> 144:ef7eb2e8f9f7 396 ((SIZE) == MPU_REGION_SIZE_1GB) || \
<> 144:ef7eb2e8f9f7 397 ((SIZE) == MPU_REGION_SIZE_2GB) || \
<> 144:ef7eb2e8f9f7 398 ((SIZE) == MPU_REGION_SIZE_4GB))
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
<> 144:ef7eb2e8f9f7 401 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @}
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 408 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
<> 144:ef7eb2e8f9f7 409 * @brief CORTEX private functions
<> 144:ef7eb2e8f9f7 410 * @{
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @brief Disables the MPU
<> 144:ef7eb2e8f9f7 416 * @retval None
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 __STATIC_INLINE void HAL_MPU_Disable(void)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /* Disable fault exceptions */
<> 144:ef7eb2e8f9f7 421 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Disable the MPU */
<> 144:ef7eb2e8f9f7 424 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @brief Enables the MPU
<> 144:ef7eb2e8f9f7 429 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
<> 144:ef7eb2e8f9f7 430 * NMI, FAULTMASK and privileged access to the default memory
<> 144:ef7eb2e8f9f7 431 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 432 * @arg MPU_HFNMI_PRIVDEF_NONE
<> 144:ef7eb2e8f9f7 433 * @arg MPU_HARDFAULT_NMI
<> 144:ef7eb2e8f9f7 434 * @arg MPU_PRIVILEGED_DEFAULT
<> 144:ef7eb2e8f9f7 435 * @arg MPU_HFNMI_PRIVDEF
<> 144:ef7eb2e8f9f7 436 * @retval None
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* Enable the MPU */
<> 144:ef7eb2e8f9f7 441 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Enable fault exceptions */
<> 144:ef7eb2e8f9f7 444 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @}
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /**
<> 144:ef7eb2e8f9f7 457 * @}
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 #endif
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #endif /* __STM32F7xx_HAL_CORTEX_H */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/