Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/system_stm32f7xx.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 74:9322579e4309 1 /**
mbed_official 74:9322579e4309 2 ******************************************************************************
mbed_official 74:9322579e4309 3 * @file system_stm32f7xx.c
mbed_official 74:9322579e4309 4 * @author MCD Application Team
mbed_official 83:a036322b8637 5 * @version V1.0.2
mbed_official 83:a036322b8637 6 * @date 21-September-2015
mbed_official 74:9322579e4309 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
mbed_official 74:9322579e4309 8 *
mbed_official 74:9322579e4309 9 * This file provides two functions and one global variable to be called from
mbed_official 74:9322579e4309 10 * user application:
mbed_official 74:9322579e4309 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 74:9322579e4309 12 * before branch to main program. This call is made inside
mbed_official 74:9322579e4309 13 * the "startup_stm32f7xx.s" file.
mbed_official 74:9322579e4309 14 *
mbed_official 74:9322579e4309 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 74:9322579e4309 16 * by the user application to setup the SysTick
mbed_official 74:9322579e4309 17 * timer or configure other parameters.
mbed_official 74:9322579e4309 18 *
mbed_official 74:9322579e4309 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 74:9322579e4309 20 * be called whenever the core clock is changed
mbed_official 74:9322579e4309 21 * during program execution.
mbed_official 74:9322579e4309 22 *
mbed_official 74:9322579e4309 23 * This file configures the system clock as follows:
mbed_official 74:9322579e4309 24 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
mbed_official 74:9322579e4309 26 * | (external 25MHz xtal) | (internal 16MHz clock)
mbed_official 74:9322579e4309 27 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 28 * SYSCLK(MHz) | 216 | 216
mbed_official 74:9322579e4309 29 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 30 * AHBCLK (MHz) | 216 | 216
mbed_official 74:9322579e4309 31 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 32 * APB1CLK (MHz) | 54 | 54
mbed_official 74:9322579e4309 33 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 34 * APB2CLK (MHz) | 108 | 108
mbed_official 74:9322579e4309 35 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 36 * USB capable | YES | NO
mbed_official 74:9322579e4309 37 * with 48 MHz precise clock | |
mbed_official 74:9322579e4309 38 *-----------------------------------------------------------------------------
mbed_official 74:9322579e4309 39 ******************************************************************************
mbed_official 74:9322579e4309 40 * @attention
mbed_official 74:9322579e4309 41 *
mbed_official 83:a036322b8637 42 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
mbed_official 74:9322579e4309 43 *
mbed_official 74:9322579e4309 44 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 74:9322579e4309 45 * are permitted provided that the following conditions are met:
mbed_official 74:9322579e4309 46 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 74:9322579e4309 47 * this list of conditions and the following disclaimer.
mbed_official 74:9322579e4309 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 74:9322579e4309 49 * this list of conditions and the following disclaimer in the documentation
mbed_official 74:9322579e4309 50 * and/or other materials provided with the distribution.
mbed_official 74:9322579e4309 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 74:9322579e4309 52 * may be used to endorse or promote products derived from this software
mbed_official 74:9322579e4309 53 * without specific prior written permission.
mbed_official 74:9322579e4309 54 *
mbed_official 74:9322579e4309 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 74:9322579e4309 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 74:9322579e4309 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 74:9322579e4309 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 74:9322579e4309 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 74:9322579e4309 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 74:9322579e4309 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 74:9322579e4309 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 74:9322579e4309 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 74:9322579e4309 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 74:9322579e4309 65 *
mbed_official 74:9322579e4309 66 ******************************************************************************
mbed_official 74:9322579e4309 67 */
mbed_official 74:9322579e4309 68
mbed_official 74:9322579e4309 69 /** @addtogroup CMSIS
mbed_official 74:9322579e4309 70 * @{
mbed_official 74:9322579e4309 71 */
mbed_official 74:9322579e4309 72
mbed_official 74:9322579e4309 73 /** @addtogroup stm32f7xx_system
mbed_official 74:9322579e4309 74 * @{
mbed_official 74:9322579e4309 75 */
mbed_official 74:9322579e4309 76
mbed_official 74:9322579e4309 77 /** @addtogroup STM32F7xx_System_Private_Includes
mbed_official 74:9322579e4309 78 * @{
mbed_official 74:9322579e4309 79 */
mbed_official 74:9322579e4309 80
mbed_official 74:9322579e4309 81 #include "stm32f7xx.h"
mbed_official 74:9322579e4309 82 #include "hal_tick.h"
mbed_official 74:9322579e4309 83
mbed_official 74:9322579e4309 84 HAL_StatusTypeDef HAL_Init(void);
mbed_official 74:9322579e4309 85
mbed_official 74:9322579e4309 86 #if !defined (HSE_VALUE)
mbed_official 74:9322579e4309 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 74:9322579e4309 88 #endif /* HSE_VALUE */
mbed_official 74:9322579e4309 89
mbed_official 74:9322579e4309 90 #if !defined (HSI_VALUE)
mbed_official 74:9322579e4309 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 74:9322579e4309 92 #endif /* HSI_VALUE */
mbed_official 74:9322579e4309 93
mbed_official 74:9322579e4309 94 /**
mbed_official 74:9322579e4309 95 * @}
mbed_official 74:9322579e4309 96 */
mbed_official 74:9322579e4309 97
mbed_official 74:9322579e4309 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
mbed_official 74:9322579e4309 99 * @{
mbed_official 74:9322579e4309 100 */
mbed_official 74:9322579e4309 101
mbed_official 74:9322579e4309 102 /**
mbed_official 74:9322579e4309 103 * @}
mbed_official 74:9322579e4309 104 */
mbed_official 74:9322579e4309 105
mbed_official 74:9322579e4309 106 /** @addtogroup STM32F7xx_System_Private_Defines
mbed_official 74:9322579e4309 107 * @{
mbed_official 74:9322579e4309 108 */
mbed_official 74:9322579e4309 109
mbed_official 74:9322579e4309 110 /************************* Miscellaneous Configuration ************************/
mbed_official 83:a036322b8637 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 83:a036322b8637 112 on STMicroelectronics EVAL/Discovery boards as data memory */
mbed_official 83:a036322b8637 113 /*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
mbed_official 83:a036322b8637 114 need to be added in the project preprocessor to avoid SDRAM multiple configuration
mbed_official 83:a036322b8637 115 (the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
mbed_official 83:a036322b8637 116 /* #define DATA_IN_ExtSRAM */
mbed_official 83:a036322b8637 117 /* #define DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 118
mbed_official 74:9322579e4309 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 74:9322579e4309 120 Internal SRAM. */
mbed_official 74:9322579e4309 121 /* #define VECT_TAB_SRAM */
mbed_official 74:9322579e4309 122 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 74:9322579e4309 123 This value must be a multiple of 0x200. */
mbed_official 74:9322579e4309 124 /******************************************************************************/
mbed_official 74:9322579e4309 125
mbed_official 74:9322579e4309 126 /**
mbed_official 74:9322579e4309 127 * @}
mbed_official 74:9322579e4309 128 */
mbed_official 74:9322579e4309 129
mbed_official 74:9322579e4309 130 /** @addtogroup STM32F7xx_System_Private_Macros
mbed_official 74:9322579e4309 131 * @{
mbed_official 74:9322579e4309 132 */
mbed_official 74:9322579e4309 133
mbed_official 74:9322579e4309 134 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 74:9322579e4309 135 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 74:9322579e4309 136 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 74:9322579e4309 137
mbed_official 74:9322579e4309 138 /**
mbed_official 74:9322579e4309 139 * @}
mbed_official 74:9322579e4309 140 */
mbed_official 74:9322579e4309 141
mbed_official 74:9322579e4309 142 /** @addtogroup STM32F7xx_System_Private_Variables
mbed_official 74:9322579e4309 143 * @{
mbed_official 74:9322579e4309 144 */
mbed_official 74:9322579e4309 145
mbed_official 74:9322579e4309 146 /* This variable is updated in three ways:
mbed_official 74:9322579e4309 147 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 74:9322579e4309 148 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 74:9322579e4309 149 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 74:9322579e4309 150 Note: If you use this function to configure the system clock; then there
mbed_official 74:9322579e4309 151 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 74:9322579e4309 152 variable is updated automatically.
mbed_official 74:9322579e4309 153 */
mbed_official 74:9322579e4309 154 uint32_t SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 155 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
<> 144:ef7eb2e8f9f7 156 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
mbed_official 74:9322579e4309 157
mbed_official 74:9322579e4309 158 /**
mbed_official 74:9322579e4309 159 * @}
mbed_official 74:9322579e4309 160 */
mbed_official 74:9322579e4309 161
mbed_official 74:9322579e4309 162 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
mbed_official 74:9322579e4309 163 * @{
mbed_official 74:9322579e4309 164 */
mbed_official 83:a036322b8637 165 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 166 static void SystemInit_ExtMemCtl(void);
mbed_official 83:a036322b8637 167 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 168
mbed_official 74:9322579e4309 169 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 74:9322579e4309 170 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 74:9322579e4309 171 #endif
mbed_official 74:9322579e4309 172
mbed_official 74:9322579e4309 173 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 74:9322579e4309 174
mbed_official 74:9322579e4309 175 /**
mbed_official 74:9322579e4309 176 * @}
mbed_official 74:9322579e4309 177 */
mbed_official 74:9322579e4309 178
mbed_official 74:9322579e4309 179 /** @addtogroup STM32F7xx_System_Private_Functions
mbed_official 74:9322579e4309 180 * @{
mbed_official 74:9322579e4309 181 */
mbed_official 74:9322579e4309 182
mbed_official 74:9322579e4309 183 /**
mbed_official 74:9322579e4309 184 * @brief Setup the microcontroller system
mbed_official 74:9322579e4309 185 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 74:9322579e4309 186 * SystemFrequency variable.
mbed_official 74:9322579e4309 187 * @param None
mbed_official 74:9322579e4309 188 * @retval None
mbed_official 74:9322579e4309 189 */
mbed_official 74:9322579e4309 190 void SystemInit(void)
mbed_official 74:9322579e4309 191 {
mbed_official 74:9322579e4309 192 /* FPU settings ------------------------------------------------------------*/
mbed_official 74:9322579e4309 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 74:9322579e4309 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 74:9322579e4309 195 #endif
mbed_official 74:9322579e4309 196 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 74:9322579e4309 197 /* Set HSION bit */
mbed_official 74:9322579e4309 198 RCC->CR |= (uint32_t)0x00000001;
mbed_official 74:9322579e4309 199
mbed_official 74:9322579e4309 200 /* Reset CFGR register */
mbed_official 74:9322579e4309 201 RCC->CFGR = 0x00000000;
mbed_official 74:9322579e4309 202
mbed_official 74:9322579e4309 203 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 74:9322579e4309 204 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 74:9322579e4309 205
mbed_official 74:9322579e4309 206 /* Reset PLLCFGR register */
mbed_official 74:9322579e4309 207 RCC->PLLCFGR = 0x24003010;
mbed_official 74:9322579e4309 208
mbed_official 74:9322579e4309 209 /* Reset HSEBYP bit */
mbed_official 74:9322579e4309 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 74:9322579e4309 211
mbed_official 74:9322579e4309 212 /* Disable all interrupts */
mbed_official 74:9322579e4309 213 RCC->CIR = 0x00000000;
mbed_official 74:9322579e4309 214
mbed_official 83:a036322b8637 215 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 216 SystemInit_ExtMemCtl();
mbed_official 83:a036322b8637 217 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 218
mbed_official 74:9322579e4309 219 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 74:9322579e4309 220 #ifdef VECT_TAB_SRAM
mbed_official 83:a036322b8637 221 SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 74:9322579e4309 222 #else
mbed_official 74:9322579e4309 223 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 74:9322579e4309 224 #endif
mbed_official 74:9322579e4309 225
mbed_official 74:9322579e4309 226 /* Configure the Cube driver */
mbed_official 74:9322579e4309 227 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
mbed_official 74:9322579e4309 228 HAL_Init();
mbed_official 74:9322579e4309 229
mbed_official 74:9322579e4309 230 // Enable CPU L1-Cache
mbed_official 74:9322579e4309 231 SCB_EnableICache();
mbed_official 74:9322579e4309 232 SCB_EnableDCache();
mbed_official 74:9322579e4309 233
mbed_official 74:9322579e4309 234 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 74:9322579e4309 235 AHB/APBx prescalers and Flash settings */
mbed_official 74:9322579e4309 236 SetSysClock();
mbed_official 74:9322579e4309 237
mbed_official 74:9322579e4309 238 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 74:9322579e4309 239 TIM_MST_RESET_ON;
mbed_official 74:9322579e4309 240 TIM_MST_RESET_OFF;
mbed_official 74:9322579e4309 241 }
mbed_official 74:9322579e4309 242
mbed_official 74:9322579e4309 243 /**
mbed_official 74:9322579e4309 244 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 74:9322579e4309 245 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 74:9322579e4309 246 * be used by the user application to setup the SysTick timer or configure
mbed_official 74:9322579e4309 247 * other parameters.
mbed_official 74:9322579e4309 248 *
mbed_official 74:9322579e4309 249 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 74:9322579e4309 250 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 74:9322579e4309 251 * based on this variable will be incorrect.
mbed_official 74:9322579e4309 252 *
mbed_official 74:9322579e4309 253 * @note - The system frequency computed by this function is not the real
mbed_official 74:9322579e4309 254 * frequency in the chip. It is calculated based on the predefined
mbed_official 74:9322579e4309 255 * constant and the selected clock source:
mbed_official 74:9322579e4309 256 *
mbed_official 74:9322579e4309 257 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 74:9322579e4309 258 *
mbed_official 74:9322579e4309 259 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 74:9322579e4309 260 *
mbed_official 74:9322579e4309 261 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 74:9322579e4309 262 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 74:9322579e4309 263 *
mbed_official 74:9322579e4309 264 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 74:9322579e4309 265 * 16 MHz) but the real value may vary depending on the variations
mbed_official 74:9322579e4309 266 * in voltage and temperature.
mbed_official 74:9322579e4309 267 *
mbed_official 74:9322579e4309 268 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 74:9322579e4309 269 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 74:9322579e4309 270 * frequency of the crystal used. Otherwise, this function may
mbed_official 74:9322579e4309 271 * have wrong result.
mbed_official 74:9322579e4309 272 *
mbed_official 74:9322579e4309 273 * - The result of this function could be not correct when using fractional
mbed_official 74:9322579e4309 274 * value for HSE crystal.
mbed_official 74:9322579e4309 275 *
mbed_official 74:9322579e4309 276 * @param None
mbed_official 74:9322579e4309 277 * @retval None
mbed_official 74:9322579e4309 278 */
mbed_official 74:9322579e4309 279 void SystemCoreClockUpdate(void)
mbed_official 74:9322579e4309 280 {
mbed_official 74:9322579e4309 281 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 74:9322579e4309 282
mbed_official 74:9322579e4309 283 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 74:9322579e4309 284 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 74:9322579e4309 285
mbed_official 74:9322579e4309 286 switch (tmp)
mbed_official 74:9322579e4309 287 {
mbed_official 74:9322579e4309 288 case 0x00: /* HSI used as system clock source */
mbed_official 74:9322579e4309 289 SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 290 break;
mbed_official 74:9322579e4309 291 case 0x04: /* HSE used as system clock source */
mbed_official 74:9322579e4309 292 SystemCoreClock = HSE_VALUE;
mbed_official 74:9322579e4309 293 break;
mbed_official 74:9322579e4309 294 case 0x08: /* PLL used as system clock source */
mbed_official 74:9322579e4309 295
mbed_official 74:9322579e4309 296 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 74:9322579e4309 297 SYSCLK = PLL_VCO / PLL_P
mbed_official 74:9322579e4309 298 */
mbed_official 74:9322579e4309 299 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 74:9322579e4309 300 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 74:9322579e4309 301
mbed_official 74:9322579e4309 302 if (pllsource != 0)
mbed_official 74:9322579e4309 303 {
mbed_official 74:9322579e4309 304 /* HSE used as PLL clock source */
mbed_official 74:9322579e4309 305 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 74:9322579e4309 306 }
mbed_official 74:9322579e4309 307 else
mbed_official 74:9322579e4309 308 {
mbed_official 74:9322579e4309 309 /* HSI used as PLL clock source */
mbed_official 74:9322579e4309 310 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 74:9322579e4309 311 }
mbed_official 74:9322579e4309 312
mbed_official 74:9322579e4309 313 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 74:9322579e4309 314 SystemCoreClock = pllvco/pllp;
mbed_official 74:9322579e4309 315 break;
mbed_official 74:9322579e4309 316 default:
mbed_official 74:9322579e4309 317 SystemCoreClock = HSI_VALUE;
mbed_official 74:9322579e4309 318 break;
mbed_official 74:9322579e4309 319 }
mbed_official 74:9322579e4309 320 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 74:9322579e4309 321 /* Get HCLK prescaler */
mbed_official 74:9322579e4309 322 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 74:9322579e4309 323 /* HCLK frequency */
mbed_official 74:9322579e4309 324 SystemCoreClock >>= tmp;
mbed_official 74:9322579e4309 325 }
mbed_official 74:9322579e4309 326
mbed_official 83:a036322b8637 327 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 328 /**
mbed_official 83:a036322b8637 329 * @brief Setup the external memory controller.
mbed_official 83:a036322b8637 330 * Called in startup_stm32f7xx.s before jump to main.
mbed_official 83:a036322b8637 331 * This function configures the external memories (SRAM/SDRAM)
mbed_official 83:a036322b8637 332 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 83:a036322b8637 333 * @param None
mbed_official 83:a036322b8637 334 * @retval None
mbed_official 83:a036322b8637 335 */
mbed_official 83:a036322b8637 336 void SystemInit_ExtMemCtl(void)
mbed_official 83:a036322b8637 337 {
mbed_official 83:a036322b8637 338 __IO uint32_t tmp = 0;
mbed_official 83:a036322b8637 339 #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
mbed_official 83:a036322b8637 340 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 83:a036322b8637 341 register uint32_t index;
mbed_official 83:a036322b8637 342
mbed_official 83:a036322b8637 343 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 83:a036322b8637 344 clock */
mbed_official 83:a036322b8637 345 RCC->AHB1ENR |= 0x000001F8;
mbed_official 83:a036322b8637 346
mbed_official 83:a036322b8637 347 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 348 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 349
mbed_official 83:a036322b8637 350 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 351 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 83:a036322b8637 352 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 353 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 354 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 83:a036322b8637 355
mbed_official 83:a036322b8637 356 /* Configure PDx pins speed to 100 MHz */
mbed_official 83:a036322b8637 357 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 83:a036322b8637 358 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 359 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 360 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 361 GPIOD->PUPDR = 0x55550545;
mbed_official 83:a036322b8637 362
mbed_official 83:a036322b8637 363 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 364 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 83:a036322b8637 365 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 366 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 367 GPIOE->MODER = 0xAAAA828A;
mbed_official 83:a036322b8637 368 /* Configure PEx pins speed to 50 MHz */
mbed_official 83:a036322b8637 369 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 83:a036322b8637 370 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 371 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 372 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 373 GPIOE->PUPDR = 0x55554145;
mbed_official 83:a036322b8637 374
mbed_official 83:a036322b8637 375 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 376 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 377 GPIOF->AFR[1] = 0xCCCCC000;
mbed_official 83:a036322b8637 378 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 379 GPIOF->MODER = 0xAA800AAA;
mbed_official 83:a036322b8637 380 /* Configure PFx pins speed to 50 MHz */
mbed_official 83:a036322b8637 381 GPIOF->OSPEEDR = 0xFF800FFF;
mbed_official 83:a036322b8637 382 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 383 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 384 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 385 GPIOF->PUPDR = 0x55400555;
mbed_official 83:a036322b8637 386
mbed_official 83:a036322b8637 387 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 388 GPIOG->AFR[0] = 0x00CC00CC;
mbed_official 83:a036322b8637 389 GPIOG->AFR[1] = 0xC00000CC;
mbed_official 83:a036322b8637 390 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 391 GPIOG->MODER = 0x80220AAA;
mbed_official 83:a036322b8637 392 /* Configure PGx pins speed to 50 MHz */
mbed_official 83:a036322b8637 393 GPIOG->OSPEEDR = 0x80320FFF;
mbed_official 83:a036322b8637 394 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 395 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 396 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 397 GPIOG->PUPDR = 0x40110555;
mbed_official 83:a036322b8637 398
mbed_official 83:a036322b8637 399 /* Connect PHx pins to FMC Alternate function */
mbed_official 83:a036322b8637 400 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 83:a036322b8637 401 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 402 /* Configure PHx pins in Alternate function mode */
mbed_official 83:a036322b8637 403 GPIOH->MODER = 0xAAAA08A0;
mbed_official 83:a036322b8637 404 /* Configure PHx pins speed to 50 MHz */
mbed_official 83:a036322b8637 405 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 83:a036322b8637 406 /* Configure PHx pins Output type to push-pull */
mbed_official 83:a036322b8637 407 GPIOH->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 408 /* No pull-up, pull-down for PHx pins */
mbed_official 83:a036322b8637 409 GPIOH->PUPDR = 0x55550450;
mbed_official 83:a036322b8637 410
mbed_official 83:a036322b8637 411 /* Connect PIx pins to FMC Alternate function */
mbed_official 83:a036322b8637 412 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 413 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 83:a036322b8637 414 /* Configure PIx pins in Alternate function mode */
mbed_official 83:a036322b8637 415 GPIOI->MODER = 0x0028AAAA;
mbed_official 83:a036322b8637 416 /* Configure PIx pins speed to 50 MHz */
mbed_official 83:a036322b8637 417 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 83:a036322b8637 418 /* Configure PIx pins Output type to push-pull */
mbed_official 83:a036322b8637 419 GPIOI->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 420 /* No pull-up, pull-down for PIx pins */
mbed_official 83:a036322b8637 421 GPIOI->PUPDR = 0x00145555;
mbed_official 83:a036322b8637 422
mbed_official 83:a036322b8637 423 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 83:a036322b8637 424 /* Enable the FMC interface clock */
mbed_official 83:a036322b8637 425 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 426
mbed_official 83:a036322b8637 427 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 428 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 429
mbed_official 83:a036322b8637 430 /* Configure and enable Bank1_SRAM2 */
mbed_official 83:a036322b8637 431 FMC_Bank1->BTCR[4] = 0x00001091;
mbed_official 83:a036322b8637 432 FMC_Bank1->BTCR[5] = 0x00110212;
mbed_official 83:a036322b8637 433 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official 83:a036322b8637 434
mbed_official 83:a036322b8637 435 /* Configure and enable SDRAM bank1 */
mbed_official 83:a036322b8637 436 FMC_Bank5_6->SDCR[0] = 0x000019E5;
mbed_official 83:a036322b8637 437 FMC_Bank5_6->SDTR[0] = 0x01116361;
mbed_official 83:a036322b8637 438
mbed_official 83:a036322b8637 439 /* SDRAM initialization sequence */
mbed_official 83:a036322b8637 440 /* Clock enable command */
mbed_official 83:a036322b8637 441 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 83:a036322b8637 442 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 443 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 444 {
mbed_official 83:a036322b8637 445 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 446 }
mbed_official 83:a036322b8637 447
mbed_official 83:a036322b8637 448 /* Delay */
mbed_official 83:a036322b8637 449 for (index = 0; index<1000; index++);
mbed_official 83:a036322b8637 450
mbed_official 83:a036322b8637 451 /* PALL command */
mbed_official 83:a036322b8637 452 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 83:a036322b8637 453 timeout = 0xFFFF;
mbed_official 83:a036322b8637 454 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 455 {
mbed_official 83:a036322b8637 456 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 457 }
mbed_official 83:a036322b8637 458
mbed_official 83:a036322b8637 459 /* Auto refresh command */
mbed_official 83:a036322b8637 460 FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official 83:a036322b8637 461 timeout = 0xFFFF;
mbed_official 83:a036322b8637 462 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 463 {
mbed_official 83:a036322b8637 464 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 465 }
mbed_official 83:a036322b8637 466
mbed_official 83:a036322b8637 467 /* MRD register program */
mbed_official 83:a036322b8637 468 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 83:a036322b8637 469 timeout = 0xFFFF;
mbed_official 83:a036322b8637 470 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 471 {
mbed_official 83:a036322b8637 472 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 473 }
mbed_official 83:a036322b8637 474
mbed_official 83:a036322b8637 475 /* Set refresh count */
mbed_official 83:a036322b8637 476 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 83:a036322b8637 477 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
mbed_official 83:a036322b8637 478
mbed_official 83:a036322b8637 479 /* Disable write protection */
mbed_official 83:a036322b8637 480 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 83:a036322b8637 481 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 83:a036322b8637 482
mbed_official 83:a036322b8637 483 #elif defined (DATA_IN_ExtSDRAM)
mbed_official 83:a036322b8637 484 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 83:a036322b8637 485 register uint32_t index;
mbed_official 83:a036322b8637 486
mbed_official 83:a036322b8637 487 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 83:a036322b8637 488 clock */
mbed_official 83:a036322b8637 489 RCC->AHB1ENR |= 0x000001F8;
mbed_official 83:a036322b8637 490
mbed_official 83:a036322b8637 491 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 492 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 493
mbed_official 83:a036322b8637 494 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 495 GPIOD->AFR[0] = 0x000000CC;
mbed_official 83:a036322b8637 496 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 83:a036322b8637 497 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 498 GPIOD->MODER = 0xA02A000A;
mbed_official 83:a036322b8637 499 /* Configure PDx pins speed to 50 MHz */
mbed_official 83:a036322b8637 500 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 83:a036322b8637 501 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 502 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 503 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 504 GPIOD->PUPDR = 0x50150005;
mbed_official 83:a036322b8637 505
mbed_official 83:a036322b8637 506 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 507 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 83:a036322b8637 508 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 509 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 510 GPIOE->MODER = 0xAAAA800A;
mbed_official 83:a036322b8637 511 /* Configure PEx pins speed to 50 MHz */
mbed_official 83:a036322b8637 512 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 83:a036322b8637 513 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 514 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 515 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 516 GPIOE->PUPDR = 0x55554005;
mbed_official 83:a036322b8637 517
mbed_official 83:a036322b8637 518 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 519 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 520 GPIOF->AFR[1] = 0xCCCCC000;
mbed_official 83:a036322b8637 521 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 522 GPIOF->MODER = 0xAA800AAA;
mbed_official 83:a036322b8637 523 /* Configure PFx pins speed to 50 MHz */
mbed_official 83:a036322b8637 524 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 83:a036322b8637 525 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 526 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 527 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 528 GPIOF->PUPDR = 0x55400555;
mbed_official 83:a036322b8637 529
mbed_official 83:a036322b8637 530 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 531 GPIOG->AFR[0] = 0x00CC00CC;
mbed_official 83:a036322b8637 532 GPIOG->AFR[1] = 0xC000000C;
mbed_official 83:a036322b8637 533 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 534 GPIOG->MODER = 0x80020A0A;
mbed_official 83:a036322b8637 535 /* Configure PGx pins speed to 50 MHz */
mbed_official 83:a036322b8637 536 GPIOG->OSPEEDR = 0x80020A0A;
mbed_official 83:a036322b8637 537 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 538 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 539 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 540 GPIOG->PUPDR = 0x40010505;
mbed_official 83:a036322b8637 541
mbed_official 83:a036322b8637 542 /* Connect PHx pins to FMC Alternate function */
mbed_official 83:a036322b8637 543 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 83:a036322b8637 544 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 545 /* Configure PHx pins in Alternate function mode */
mbed_official 83:a036322b8637 546 GPIOH->MODER = 0xAAAA08A0;
mbed_official 83:a036322b8637 547 /* Configure PHx pins speed to 50 MHz */
mbed_official 83:a036322b8637 548 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 83:a036322b8637 549 /* Configure PHx pins Output type to push-pull */
mbed_official 83:a036322b8637 550 GPIOH->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 551 /* No pull-up, pull-down for PHx pins */
mbed_official 83:a036322b8637 552 GPIOH->PUPDR = 0x55550450;
mbed_official 83:a036322b8637 553
mbed_official 83:a036322b8637 554 /* Connect PIx pins to FMC Alternate function */
mbed_official 83:a036322b8637 555 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 556 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 83:a036322b8637 557 /* Configure PIx pins in Alternate function mode */
mbed_official 83:a036322b8637 558 GPIOI->MODER = 0x0028AAAA;
mbed_official 83:a036322b8637 559 /* Configure PIx pins speed to 50 MHz */
mbed_official 83:a036322b8637 560 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 83:a036322b8637 561 /* Configure PIx pins Output type to push-pull */
mbed_official 83:a036322b8637 562 GPIOI->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 563 /* No pull-up, pull-down for PIx pins */
mbed_official 83:a036322b8637 564 GPIOI->PUPDR = 0x00145555;
mbed_official 83:a036322b8637 565
mbed_official 83:a036322b8637 566 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 83:a036322b8637 567 /* Enable the FMC interface clock */
mbed_official 83:a036322b8637 568 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 569
mbed_official 83:a036322b8637 570 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 571 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 572
mbed_official 83:a036322b8637 573 /* Configure and enable SDRAM bank1 */
mbed_official 83:a036322b8637 574 FMC_Bank5_6->SDCR[0] = 0x000019E5;
mbed_official 83:a036322b8637 575 FMC_Bank5_6->SDTR[0] = 0x01116361;
mbed_official 83:a036322b8637 576
mbed_official 83:a036322b8637 577 /* SDRAM initialization sequence */
mbed_official 83:a036322b8637 578 /* Clock enable command */
mbed_official 83:a036322b8637 579 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 83:a036322b8637 580 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 581 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 582 {
mbed_official 83:a036322b8637 583 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 584 }
mbed_official 83:a036322b8637 585
mbed_official 83:a036322b8637 586 /* Delay */
mbed_official 83:a036322b8637 587 for (index = 0; index<1000; index++);
mbed_official 83:a036322b8637 588
mbed_official 83:a036322b8637 589 /* PALL command */
mbed_official 83:a036322b8637 590 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 83:a036322b8637 591 timeout = 0xFFFF;
mbed_official 83:a036322b8637 592 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 593 {
mbed_official 83:a036322b8637 594 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 595 }
mbed_official 83:a036322b8637 596
mbed_official 83:a036322b8637 597 /* Auto refresh command */
mbed_official 83:a036322b8637 598 FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official 83:a036322b8637 599 timeout = 0xFFFF;
mbed_official 83:a036322b8637 600 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 601 {
mbed_official 83:a036322b8637 602 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 603 }
mbed_official 83:a036322b8637 604
mbed_official 83:a036322b8637 605 /* MRD register program */
mbed_official 83:a036322b8637 606 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 83:a036322b8637 607 timeout = 0xFFFF;
mbed_official 83:a036322b8637 608 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 83:a036322b8637 609 {
mbed_official 83:a036322b8637 610 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 83:a036322b8637 611 }
mbed_official 83:a036322b8637 612
mbed_official 83:a036322b8637 613 /* Set refresh count */
mbed_official 83:a036322b8637 614 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 83:a036322b8637 615 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
mbed_official 83:a036322b8637 616
mbed_official 83:a036322b8637 617 /* Disable write protection */
mbed_official 83:a036322b8637 618 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 83:a036322b8637 619 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 83:a036322b8637 620
mbed_official 83:a036322b8637 621 #elif defined(DATA_IN_ExtSRAM)
mbed_official 83:a036322b8637 622 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 83:a036322b8637 623 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 83:a036322b8637 624 RCC->AHB1ENR |= 0x00000078;
mbed_official 83:a036322b8637 625
mbed_official 83:a036322b8637 626 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 627 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
mbed_official 83:a036322b8637 628
mbed_official 83:a036322b8637 629 /* Connect PDx pins to FMC Alternate function */
mbed_official 83:a036322b8637 630 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 83:a036322b8637 631 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 632 /* Configure PDx pins in Alternate function mode */
mbed_official 83:a036322b8637 633 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 83:a036322b8637 634 /* Configure PDx pins speed to 100 MHz */
mbed_official 83:a036322b8637 635 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 83:a036322b8637 636 /* Configure PDx pins Output type to push-pull */
mbed_official 83:a036322b8637 637 GPIOD->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 638 /* No pull-up, pull-down for PDx pins */
mbed_official 83:a036322b8637 639 GPIOD->PUPDR = 0x55550545;
mbed_official 83:a036322b8637 640
mbed_official 83:a036322b8637 641 /* Connect PEx pins to FMC Alternate function */
mbed_official 83:a036322b8637 642 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 83:a036322b8637 643 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 83:a036322b8637 644 /* Configure PEx pins in Alternate function mode */
mbed_official 83:a036322b8637 645 GPIOE->MODER = 0xAAAA828A;
mbed_official 83:a036322b8637 646 /* Configure PEx pins speed to 100 MHz */
mbed_official 83:a036322b8637 647 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 83:a036322b8637 648 /* Configure PEx pins Output type to push-pull */
mbed_official 83:a036322b8637 649 GPIOE->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 650 /* No pull-up, pull-down for PEx pins */
mbed_official 83:a036322b8637 651 GPIOE->PUPDR = 0x55554145;
mbed_official 83:a036322b8637 652
mbed_official 83:a036322b8637 653 /* Connect PFx pins to FMC Alternate function */
mbed_official 83:a036322b8637 654 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 655 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 83:a036322b8637 656 /* Configure PFx pins in Alternate function mode */
mbed_official 83:a036322b8637 657 GPIOF->MODER = 0xAA000AAA;
mbed_official 83:a036322b8637 658 /* Configure PFx pins speed to 100 MHz */
mbed_official 83:a036322b8637 659 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 83:a036322b8637 660 /* Configure PFx pins Output type to push-pull */
mbed_official 83:a036322b8637 661 GPIOF->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 662 /* No pull-up, pull-down for PFx pins */
mbed_official 83:a036322b8637 663 GPIOF->PUPDR = 0x55000555;
mbed_official 83:a036322b8637 664
mbed_official 83:a036322b8637 665 /* Connect PGx pins to FMC Alternate function */
mbed_official 83:a036322b8637 666 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 83:a036322b8637 667 GPIOG->AFR[1] = 0x000000C0;
mbed_official 83:a036322b8637 668 /* Configure PGx pins in Alternate function mode */
mbed_official 83:a036322b8637 669 GPIOG->MODER = 0x00200AAA;
mbed_official 83:a036322b8637 670 /* Configure PGx pins speed to 100 MHz */
mbed_official 83:a036322b8637 671 GPIOG->OSPEEDR = 0x00300FFF;
mbed_official 83:a036322b8637 672 /* Configure PGx pins Output type to push-pull */
mbed_official 83:a036322b8637 673 GPIOG->OTYPER = 0x00000000;
mbed_official 83:a036322b8637 674 /* No pull-up, pull-down for PGx pins */
mbed_official 83:a036322b8637 675 GPIOG->PUPDR = 0x00100555;
mbed_official 83:a036322b8637 676
mbed_official 83:a036322b8637 677 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 83:a036322b8637 678 /* Enable the FMC/FSMC interface clock */
mbed_official 83:a036322b8637 679 RCC->AHB3ENR |= 0x00000001;
mbed_official 83:a036322b8637 680
mbed_official 83:a036322b8637 681 /* Delay after an RCC peripheral clock enabling */
mbed_official 83:a036322b8637 682 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
mbed_official 83:a036322b8637 683
mbed_official 83:a036322b8637 684 /* Configure and enable Bank1_SRAM2 */
mbed_official 83:a036322b8637 685 FMC_Bank1->BTCR[4] = 0x00001091;
mbed_official 83:a036322b8637 686 FMC_Bank1->BTCR[5] = 0x00110212;
mbed_official 83:a036322b8637 687 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official 83:a036322b8637 688
mbed_official 83:a036322b8637 689 #endif /* DATA_IN_ExtSRAM */
mbed_official 83:a036322b8637 690
mbed_official 83:a036322b8637 691 (void)(tmp);
mbed_official 83:a036322b8637 692 }
mbed_official 83:a036322b8637 693 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 83:a036322b8637 694
mbed_official 74:9322579e4309 695 /**
mbed_official 74:9322579e4309 696 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 74:9322579e4309 697 * AHB/APBx prescalers and Flash settings
mbed_official 74:9322579e4309 698 * @note This function should be called only once the RCC clock configuration
mbed_official 74:9322579e4309 699 * is reset to the default reset state (done in SystemInit() function).
mbed_official 74:9322579e4309 700 * @param None
mbed_official 74:9322579e4309 701 * @retval None
mbed_official 74:9322579e4309 702 */
mbed_official 74:9322579e4309 703 void SetSysClock(void)
mbed_official 74:9322579e4309 704 {
mbed_official 74:9322579e4309 705 /* 1- Try to start with HSE and external clock */
mbed_official 74:9322579e4309 706 #if USE_PLL_HSE_EXTC != 0
mbed_official 74:9322579e4309 707 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 74:9322579e4309 708 #endif
mbed_official 74:9322579e4309 709 {
mbed_official 74:9322579e4309 710 /* 2- If fail try to start with HSE and external xtal */
mbed_official 74:9322579e4309 711 #if USE_PLL_HSE_XTAL != 0
mbed_official 74:9322579e4309 712 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 74:9322579e4309 713 #endif
mbed_official 74:9322579e4309 714 {
mbed_official 74:9322579e4309 715 /* 3- If fail start with HSI clock */
mbed_official 74:9322579e4309 716 if (SetSysClock_PLL_HSI() == 0)
mbed_official 74:9322579e4309 717 {
mbed_official 74:9322579e4309 718 while(1)
mbed_official 74:9322579e4309 719 {
mbed_official 74:9322579e4309 720 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 74:9322579e4309 721 }
mbed_official 74:9322579e4309 722 }
mbed_official 74:9322579e4309 723 }
mbed_official 74:9322579e4309 724 }
mbed_official 74:9322579e4309 725
mbed_official 74:9322579e4309 726 // Output clock on MCO2 pin(PC9) for debugging purpose
mbed_official 74:9322579e4309 727 // Can be visualized on CN8 connector pin 4
mbed_official 74:9322579e4309 728 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
mbed_official 74:9322579e4309 729 }
mbed_official 74:9322579e4309 730
mbed_official 74:9322579e4309 731 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 74:9322579e4309 732 /******************************************************************************/
mbed_official 74:9322579e4309 733 /* PLL (clocked by HSE) used as System clock source */
mbed_official 74:9322579e4309 734 /******************************************************************************/
mbed_official 74:9322579e4309 735 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 74:9322579e4309 736 {
mbed_official 74:9322579e4309 737 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 74:9322579e4309 738 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 74:9322579e4309 739
mbed_official 74:9322579e4309 740 // Enable power clock
mbed_official 74:9322579e4309 741 __PWR_CLK_ENABLE();
mbed_official 74:9322579e4309 742
mbed_official 74:9322579e4309 743 // Enable HSE oscillator and activate PLL with HSE as source
mbed_official 74:9322579e4309 744 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 74:9322579e4309 745 if (bypass == 0)
mbed_official 74:9322579e4309 746 {
mbed_official 74:9322579e4309 747 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
mbed_official 74:9322579e4309 748 }
mbed_official 74:9322579e4309 749 else
mbed_official 74:9322579e4309 750 {
mbed_official 74:9322579e4309 751 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
mbed_official 74:9322579e4309 752 }
mbed_official 74:9322579e4309 753 // Warning: this configuration is for a 8 MHz xtal clock only
mbed_official 74:9322579e4309 754 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 74:9322579e4309 755 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 74:9322579e4309 756 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 74:9322579e4309 757 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 74:9322579e4309 758 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 74:9322579e4309 759 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 74:9322579e4309 760
mbed_official 74:9322579e4309 761 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 74:9322579e4309 762 {
mbed_official 74:9322579e4309 763 return 0; // FAIL
mbed_official 74:9322579e4309 764 }
mbed_official 74:9322579e4309 765
mbed_official 74:9322579e4309 766 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 74:9322579e4309 767 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 74:9322579e4309 768 {
mbed_official 74:9322579e4309 769 return 0; // FAIL
mbed_official 74:9322579e4309 770 }
mbed_official 74:9322579e4309 771
mbed_official 74:9322579e4309 772 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 74:9322579e4309 773 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 74:9322579e4309 774 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 74:9322579e4309 775 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 74:9322579e4309 776 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 74:9322579e4309 777 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 74:9322579e4309 778
mbed_official 74:9322579e4309 779 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 74:9322579e4309 780 {
mbed_official 74:9322579e4309 781 return 0; // FAIL
mbed_official 74:9322579e4309 782 }
mbed_official 74:9322579e4309 783
mbed_official 74:9322579e4309 784 return 1; // OK
mbed_official 74:9322579e4309 785 }
mbed_official 74:9322579e4309 786 #endif
mbed_official 74:9322579e4309 787
mbed_official 74:9322579e4309 788 /******************************************************************************/
mbed_official 74:9322579e4309 789 /* PLL (clocked by HSI) used as System clock source */
mbed_official 74:9322579e4309 790 /******************************************************************************/
mbed_official 74:9322579e4309 791 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 74:9322579e4309 792 {
mbed_official 74:9322579e4309 793 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 74:9322579e4309 794 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 74:9322579e4309 795
mbed_official 74:9322579e4309 796 // Enable CPU L1-Cache
mbed_official 74:9322579e4309 797 SCB_EnableICache();
mbed_official 74:9322579e4309 798 SCB_EnableDCache();
mbed_official 74:9322579e4309 799
mbed_official 74:9322579e4309 800 // Enable power clock
mbed_official 74:9322579e4309 801 __PWR_CLK_ENABLE();
mbed_official 74:9322579e4309 802
mbed_official 74:9322579e4309 803 // Enable HSI oscillator and activate PLL with HSI as source
mbed_official 74:9322579e4309 804 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 74:9322579e4309 805 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 74:9322579e4309 806 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 74:9322579e4309 807 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 74:9322579e4309 808 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 74:9322579e4309 809 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 74:9322579e4309 810 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 74:9322579e4309 811 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 74:9322579e4309 812 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 74:9322579e4309 813 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 74:9322579e4309 814
mbed_official 74:9322579e4309 815 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 74:9322579e4309 816 {
mbed_official 74:9322579e4309 817 return 0; // FAIL
mbed_official 74:9322579e4309 818 }
mbed_official 74:9322579e4309 819
mbed_official 74:9322579e4309 820 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 74:9322579e4309 821 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 74:9322579e4309 822 {
mbed_official 74:9322579e4309 823 return 0; // FAIL
mbed_official 74:9322579e4309 824 }
mbed_official 74:9322579e4309 825
mbed_official 74:9322579e4309 826 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 74:9322579e4309 827 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 74:9322579e4309 828 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 74:9322579e4309 829 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 74:9322579e4309 830 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 74:9322579e4309 831 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 74:9322579e4309 832
mbed_official 74:9322579e4309 833 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 74:9322579e4309 834 {
mbed_official 74:9322579e4309 835 return 0; // FAIL
mbed_official 74:9322579e4309 836 }
mbed_official 74:9322579e4309 837
mbed_official 74:9322579e4309 838 return 1; // OK
mbed_official 74:9322579e4309 839 }
mbed_official 74:9322579e4309 840
mbed_official 74:9322579e4309 841 /**
mbed_official 74:9322579e4309 842 * @}
mbed_official 74:9322579e4309 843 */
mbed_official 74:9322579e4309 844
mbed_official 74:9322579e4309 845 /**
mbed_official 74:9322579e4309 846 * @}
mbed_official 74:9322579e4309 847 */
mbed_official 74:9322579e4309 848
mbed_official 74:9322579e4309 849 /**
mbed_official 74:9322579e4309 850 * @}
mbed_official 74:9322579e4309 851 */
mbed_official 74:9322579e4309 852 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/