Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F746ZG/stm32f746xx.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 74:9322579e4309 1 /**
mbed_official 74:9322579e4309 2 ******************************************************************************
mbed_official 74:9322579e4309 3 * @file stm32f746xx.h
mbed_official 74:9322579e4309 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
mbed_official 74:9322579e4309 8 *
mbed_official 74:9322579e4309 9 * This file contains:
mbed_official 74:9322579e4309 10 * - Data structures and the address mapping for all peripherals
mbed_official 74:9322579e4309 11 * - Peripheral's registers declarations and bits definition
mbed_official 74:9322579e4309 12 * - Macros to access peripheral’s registers hardware
mbed_official 74:9322579e4309 13 *
mbed_official 74:9322579e4309 14 ******************************************************************************
mbed_official 74:9322579e4309 15 * @attention
mbed_official 74:9322579e4309 16 *
mbed_official 83:a036322b8637 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official 74:9322579e4309 18 *
mbed_official 74:9322579e4309 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 74:9322579e4309 20 * are permitted provided that the following conditions are met:
mbed_official 74:9322579e4309 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 74:9322579e4309 22 * this list of conditions and the following disclaimer.
mbed_official 74:9322579e4309 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 74:9322579e4309 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 74:9322579e4309 25 * and/or other materials provided with the distribution.
mbed_official 74:9322579e4309 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 74:9322579e4309 27 * may be used to endorse or promote products derived from this software
mbed_official 74:9322579e4309 28 * without specific prior written permission.
mbed_official 74:9322579e4309 29 *
mbed_official 74:9322579e4309 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 74:9322579e4309 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 74:9322579e4309 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 74:9322579e4309 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 74:9322579e4309 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 74:9322579e4309 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 74:9322579e4309 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 74:9322579e4309 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 74:9322579e4309 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 74:9322579e4309 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 74:9322579e4309 40 *
mbed_official 74:9322579e4309 41 ******************************************************************************
mbed_official 74:9322579e4309 42 */
mbed_official 74:9322579e4309 43
mbed_official 74:9322579e4309 44 /** @addtogroup CMSIS_Device
mbed_official 74:9322579e4309 45 * @{
mbed_official 74:9322579e4309 46 */
mbed_official 74:9322579e4309 47
mbed_official 74:9322579e4309 48 /** @addtogroup stm32f746xx
mbed_official 74:9322579e4309 49 * @{
mbed_official 74:9322579e4309 50 */
mbed_official 74:9322579e4309 51
mbed_official 74:9322579e4309 52 #ifndef __STM32F746xx_H
mbed_official 74:9322579e4309 53 #define __STM32F746xx_H
mbed_official 74:9322579e4309 54
mbed_official 74:9322579e4309 55 #ifdef __cplusplus
mbed_official 74:9322579e4309 56 extern "C" {
mbed_official 74:9322579e4309 57 #endif /* __cplusplus */
mbed_official 74:9322579e4309 58
mbed_official 74:9322579e4309 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 74:9322579e4309 60 * @{
mbed_official 74:9322579e4309 61 */
mbed_official 74:9322579e4309 62
mbed_official 74:9322579e4309 63 /**
mbed_official 74:9322579e4309 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
mbed_official 74:9322579e4309 65 * in @ref Library_configuration_section
mbed_official 74:9322579e4309 66 */
mbed_official 83:a036322b8637 67 typedef enum
mbed_official 74:9322579e4309 68 {
mbed_official 74:9322579e4309 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
mbed_official 74:9322579e4309 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 74:9322579e4309 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
mbed_official 74:9322579e4309 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
mbed_official 74:9322579e4309 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
mbed_official 74:9322579e4309 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
mbed_official 74:9322579e4309 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
mbed_official 74:9322579e4309 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
mbed_official 74:9322579e4309 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
mbed_official 74:9322579e4309 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 74:9322579e4309 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 74:9322579e4309 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 74:9322579e4309 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 74:9322579e4309 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 74:9322579e4309 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 74:9322579e4309 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 74:9322579e4309 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 74:9322579e4309 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 74:9322579e4309 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 74:9322579e4309 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 74:9322579e4309 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 74:9322579e4309 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 74:9322579e4309 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 74:9322579e4309 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 74:9322579e4309 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 74:9322579e4309 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 74:9322579e4309 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 74:9322579e4309 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 74:9322579e4309 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 74:9322579e4309 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 74:9322579e4309 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 74:9322579e4309 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 74:9322579e4309 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 74:9322579e4309 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 74:9322579e4309 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 74:9322579e4309 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 74:9322579e4309 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 74:9322579e4309 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 74:9322579e4309 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 74:9322579e4309 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 74:9322579e4309 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 74:9322579e4309 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 74:9322579e4309 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 74:9322579e4309 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 74:9322579e4309 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 74:9322579e4309 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 74:9322579e4309 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 74:9322579e4309 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 74:9322579e4309 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 74:9322579e4309 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 74:9322579e4309 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 74:9322579e4309 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 74:9322579e4309 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 74:9322579e4309 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 74:9322579e4309 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 74:9322579e4309 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 74:9322579e4309 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 74:9322579e4309 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 74:9322579e4309 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
mbed_official 83:a036322b8637 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
mbed_official 74:9322579e4309 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 74:9322579e4309 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 74:9322579e4309 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 74:9322579e4309 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 74:9322579e4309 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 74:9322579e4309 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 74:9322579e4309 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 74:9322579e4309 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 74:9322579e4309 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 74:9322579e4309 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 74:9322579e4309 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 74:9322579e4309 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
mbed_official 74:9322579e4309 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
mbed_official 74:9322579e4309 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 74:9322579e4309 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 74:9322579e4309 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 74:9322579e4309 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 74:9322579e4309 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 74:9322579e4309 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 74:9322579e4309 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 74:9322579e4309 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 74:9322579e4309 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 74:9322579e4309 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 74:9322579e4309 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 74:9322579e4309 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 74:9322579e4309 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 74:9322579e4309 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 74:9322579e4309 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 74:9322579e4309 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
mbed_official 74:9322579e4309 158 RNG_IRQn = 80, /*!< RNG global interrupt */
mbed_official 74:9322579e4309 159 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 74:9322579e4309 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
mbed_official 74:9322579e4309 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
mbed_official 74:9322579e4309 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 74:9322579e4309 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
mbed_official 74:9322579e4309 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
mbed_official 74:9322579e4309 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
mbed_official 74:9322579e4309 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
mbed_official 74:9322579e4309 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
mbed_official 74:9322579e4309 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
mbed_official 74:9322579e4309 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
mbed_official 74:9322579e4309 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
mbed_official 74:9322579e4309 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
mbed_official 74:9322579e4309 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
mbed_official 74:9322579e4309 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
mbed_official 74:9322579e4309 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
<> 144:ef7eb2e8f9f7 175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
mbed_official 74:9322579e4309 176 } IRQn_Type;
mbed_official 74:9322579e4309 177
mbed_official 74:9322579e4309 178 /**
mbed_official 74:9322579e4309 179 * @}
mbed_official 74:9322579e4309 180 */
mbed_official 74:9322579e4309 181
mbed_official 74:9322579e4309 182 /**
mbed_official 74:9322579e4309 183 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
mbed_official 74:9322579e4309 184 */
<> 144:ef7eb2e8f9f7 185 #define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */
mbed_official 74:9322579e4309 186 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
mbed_official 74:9322579e4309 187 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
mbed_official 74:9322579e4309 188 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 74:9322579e4309 189 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 74:9322579e4309 190 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
mbed_official 74:9322579e4309 191 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
mbed_official 83:a036322b8637 192 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
mbed_official 74:9322579e4309 193
mbed_official 74:9322579e4309 194
mbed_official 74:9322579e4309 195 #include "system_stm32f7xx.h"
mbed_official 74:9322579e4309 196 #include <stdint.h>
mbed_official 74:9322579e4309 197
mbed_official 74:9322579e4309 198 /** @addtogroup Peripheral_registers_structures
mbed_official 74:9322579e4309 199 * @{
mbed_official 74:9322579e4309 200 */
mbed_official 74:9322579e4309 201
mbed_official 74:9322579e4309 202 /**
mbed_official 74:9322579e4309 203 * @brief Analog to Digital Converter
mbed_official 74:9322579e4309 204 */
mbed_official 74:9322579e4309 205
mbed_official 74:9322579e4309 206 typedef struct
mbed_official 74:9322579e4309 207 {
mbed_official 74:9322579e4309 208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 74:9322579e4309 209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 74:9322579e4309 210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 74:9322579e4309 211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 74:9322579e4309 212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 74:9322579e4309 213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 74:9322579e4309 214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 74:9322579e4309 215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 74:9322579e4309 216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 74:9322579e4309 217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 74:9322579e4309 218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 74:9322579e4309 219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 74:9322579e4309 220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 74:9322579e4309 221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 74:9322579e4309 222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 74:9322579e4309 223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 74:9322579e4309 224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 74:9322579e4309 225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 74:9322579e4309 226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 74:9322579e4309 227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 74:9322579e4309 228 } ADC_TypeDef;
mbed_official 74:9322579e4309 229
mbed_official 74:9322579e4309 230 typedef struct
mbed_official 74:9322579e4309 231 {
mbed_official 74:9322579e4309 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 74:9322579e4309 233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 74:9322579e4309 234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 74:9322579e4309 235 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 74:9322579e4309 236 } ADC_Common_TypeDef;
mbed_official 74:9322579e4309 237
mbed_official 74:9322579e4309 238
mbed_official 74:9322579e4309 239 /**
mbed_official 74:9322579e4309 240 * @brief Controller Area Network TxMailBox
mbed_official 74:9322579e4309 241 */
mbed_official 74:9322579e4309 242
mbed_official 74:9322579e4309 243 typedef struct
mbed_official 74:9322579e4309 244 {
mbed_official 74:9322579e4309 245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 74:9322579e4309 246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 74:9322579e4309 247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 74:9322579e4309 248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 74:9322579e4309 249 } CAN_TxMailBox_TypeDef;
mbed_official 74:9322579e4309 250
mbed_official 74:9322579e4309 251 /**
mbed_official 74:9322579e4309 252 * @brief Controller Area Network FIFOMailBox
mbed_official 74:9322579e4309 253 */
mbed_official 74:9322579e4309 254
mbed_official 74:9322579e4309 255 typedef struct
mbed_official 74:9322579e4309 256 {
mbed_official 74:9322579e4309 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 74:9322579e4309 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 74:9322579e4309 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 74:9322579e4309 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 74:9322579e4309 261 } CAN_FIFOMailBox_TypeDef;
mbed_official 74:9322579e4309 262
mbed_official 74:9322579e4309 263 /**
mbed_official 74:9322579e4309 264 * @brief Controller Area Network FilterRegister
mbed_official 74:9322579e4309 265 */
mbed_official 74:9322579e4309 266
mbed_official 74:9322579e4309 267 typedef struct
mbed_official 74:9322579e4309 268 {
mbed_official 74:9322579e4309 269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 74:9322579e4309 270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 74:9322579e4309 271 } CAN_FilterRegister_TypeDef;
mbed_official 74:9322579e4309 272
mbed_official 74:9322579e4309 273 /**
mbed_official 74:9322579e4309 274 * @brief Controller Area Network
mbed_official 74:9322579e4309 275 */
mbed_official 74:9322579e4309 276
mbed_official 74:9322579e4309 277 typedef struct
mbed_official 74:9322579e4309 278 {
mbed_official 74:9322579e4309 279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 74:9322579e4309 281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 74:9322579e4309 283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 74:9322579e4309 284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 74:9322579e4309 285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 74:9322579e4309 286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 74:9322579e4309 287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 74:9322579e4309 288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 74:9322579e4309 289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 74:9322579e4309 290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 74:9322579e4309 291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 74:9322579e4309 292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 74:9322579e4309 293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 74:9322579e4309 294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 74:9322579e4309 295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 74:9322579e4309 296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 74:9322579e4309 297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 74:9322579e4309 298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 74:9322579e4309 299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 74:9322579e4309 300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 74:9322579e4309 301 } CAN_TypeDef;
mbed_official 74:9322579e4309 302
mbed_official 74:9322579e4309 303 /**
mbed_official 74:9322579e4309 304 * @brief HDMI-CEC
mbed_official 74:9322579e4309 305 */
mbed_official 74:9322579e4309 306
mbed_official 74:9322579e4309 307 typedef struct
mbed_official 74:9322579e4309 308 {
mbed_official 74:9322579e4309 309 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 74:9322579e4309 310 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 74:9322579e4309 311 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 74:9322579e4309 312 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 74:9322579e4309 313 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 74:9322579e4309 314 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 74:9322579e4309 315 }CEC_TypeDef;
mbed_official 74:9322579e4309 316
mbed_official 74:9322579e4309 317
mbed_official 74:9322579e4309 318 /**
mbed_official 74:9322579e4309 319 * @brief CRC calculation unit
mbed_official 74:9322579e4309 320 */
mbed_official 74:9322579e4309 321
mbed_official 74:9322579e4309 322 typedef struct
mbed_official 74:9322579e4309 323 {
mbed_official 74:9322579e4309 324 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 74:9322579e4309 325 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 74:9322579e4309 326 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 74:9322579e4309 327 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 74:9322579e4309 328 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 74:9322579e4309 329 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 74:9322579e4309 330 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 74:9322579e4309 331 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 74:9322579e4309 332 } CRC_TypeDef;
mbed_official 74:9322579e4309 333
mbed_official 74:9322579e4309 334 /**
mbed_official 74:9322579e4309 335 * @brief Digital to Analog Converter
mbed_official 74:9322579e4309 336 */
mbed_official 74:9322579e4309 337
mbed_official 74:9322579e4309 338 typedef struct
mbed_official 74:9322579e4309 339 {
mbed_official 74:9322579e4309 340 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 341 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 74:9322579e4309 342 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 74:9322579e4309 343 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 74:9322579e4309 344 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 74:9322579e4309 345 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 74:9322579e4309 346 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 74:9322579e4309 347 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 74:9322579e4309 348 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 74:9322579e4309 349 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 74:9322579e4309 350 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 74:9322579e4309 351 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 74:9322579e4309 352 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 74:9322579e4309 353 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 74:9322579e4309 354 } DAC_TypeDef;
mbed_official 74:9322579e4309 355
mbed_official 83:a036322b8637 356
mbed_official 74:9322579e4309 357 /**
mbed_official 74:9322579e4309 358 * @brief Debug MCU
mbed_official 74:9322579e4309 359 */
mbed_official 74:9322579e4309 360
mbed_official 74:9322579e4309 361 typedef struct
mbed_official 74:9322579e4309 362 {
mbed_official 74:9322579e4309 363 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 74:9322579e4309 364 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 74:9322579e4309 365 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 74:9322579e4309 366 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 74:9322579e4309 367 }DBGMCU_TypeDef;
mbed_official 74:9322579e4309 368
mbed_official 74:9322579e4309 369 /**
mbed_official 74:9322579e4309 370 * @brief DCMI
mbed_official 74:9322579e4309 371 */
mbed_official 74:9322579e4309 372
mbed_official 74:9322579e4309 373 typedef struct
mbed_official 74:9322579e4309 374 {
mbed_official 74:9322579e4309 375 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
mbed_official 74:9322579e4309 376 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
mbed_official 74:9322579e4309 377 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 378 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
mbed_official 74:9322579e4309 379 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
mbed_official 74:9322579e4309 380 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
mbed_official 74:9322579e4309 381 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
mbed_official 74:9322579e4309 382 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
mbed_official 74:9322579e4309 383 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
mbed_official 74:9322579e4309 384 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
mbed_official 74:9322579e4309 385 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
mbed_official 74:9322579e4309 386 } DCMI_TypeDef;
mbed_official 74:9322579e4309 387
mbed_official 74:9322579e4309 388 /**
mbed_official 74:9322579e4309 389 * @brief DMA Controller
mbed_official 74:9322579e4309 390 */
mbed_official 74:9322579e4309 391
mbed_official 74:9322579e4309 392 typedef struct
mbed_official 74:9322579e4309 393 {
mbed_official 74:9322579e4309 394 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 74:9322579e4309 395 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 74:9322579e4309 396 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 74:9322579e4309 397 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 74:9322579e4309 398 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 74:9322579e4309 399 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 74:9322579e4309 400 } DMA_Stream_TypeDef;
mbed_official 74:9322579e4309 401
mbed_official 74:9322579e4309 402 typedef struct
mbed_official 74:9322579e4309 403 {
mbed_official 74:9322579e4309 404 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 74:9322579e4309 405 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 74:9322579e4309 406 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 74:9322579e4309 407 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 74:9322579e4309 408 } DMA_TypeDef;
mbed_official 74:9322579e4309 409
mbed_official 74:9322579e4309 410
mbed_official 74:9322579e4309 411 /**
mbed_official 74:9322579e4309 412 * @brief DMA2D Controller
mbed_official 74:9322579e4309 413 */
mbed_official 74:9322579e4309 414
mbed_official 74:9322579e4309 415 typedef struct
mbed_official 74:9322579e4309 416 {
mbed_official 74:9322579e4309 417 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
mbed_official 74:9322579e4309 418 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
mbed_official 74:9322579e4309 419 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
mbed_official 74:9322579e4309 420 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
mbed_official 74:9322579e4309 421 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
mbed_official 74:9322579e4309 422 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
mbed_official 74:9322579e4309 423 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
mbed_official 74:9322579e4309 424 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
mbed_official 74:9322579e4309 425 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
mbed_official 74:9322579e4309 426 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
mbed_official 74:9322579e4309 427 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
mbed_official 74:9322579e4309 428 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
mbed_official 74:9322579e4309 429 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
mbed_official 74:9322579e4309 430 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
mbed_official 74:9322579e4309 431 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
mbed_official 74:9322579e4309 432 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
mbed_official 74:9322579e4309 433 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
mbed_official 74:9322579e4309 434 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
mbed_official 74:9322579e4309 435 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
mbed_official 74:9322579e4309 436 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
mbed_official 74:9322579e4309 437 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
mbed_official 74:9322579e4309 438 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
mbed_official 74:9322579e4309 439 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
mbed_official 74:9322579e4309 440 } DMA2D_TypeDef;
mbed_official 74:9322579e4309 441
mbed_official 74:9322579e4309 442
mbed_official 74:9322579e4309 443 /**
mbed_official 74:9322579e4309 444 * @brief Ethernet MAC
mbed_official 74:9322579e4309 445 */
mbed_official 74:9322579e4309 446
mbed_official 74:9322579e4309 447 typedef struct
mbed_official 74:9322579e4309 448 {
mbed_official 74:9322579e4309 449 __IO uint32_t MACCR;
mbed_official 74:9322579e4309 450 __IO uint32_t MACFFR;
mbed_official 74:9322579e4309 451 __IO uint32_t MACHTHR;
mbed_official 74:9322579e4309 452 __IO uint32_t MACHTLR;
mbed_official 74:9322579e4309 453 __IO uint32_t MACMIIAR;
mbed_official 74:9322579e4309 454 __IO uint32_t MACMIIDR;
mbed_official 74:9322579e4309 455 __IO uint32_t MACFCR;
mbed_official 74:9322579e4309 456 __IO uint32_t MACVLANTR; /* 8 */
mbed_official 74:9322579e4309 457 uint32_t RESERVED0[2];
mbed_official 74:9322579e4309 458 __IO uint32_t MACRWUFFR; /* 11 */
mbed_official 74:9322579e4309 459 __IO uint32_t MACPMTCSR;
mbed_official 74:9322579e4309 460 uint32_t RESERVED1[2];
mbed_official 74:9322579e4309 461 __IO uint32_t MACSR; /* 15 */
mbed_official 74:9322579e4309 462 __IO uint32_t MACIMR;
mbed_official 74:9322579e4309 463 __IO uint32_t MACA0HR;
mbed_official 74:9322579e4309 464 __IO uint32_t MACA0LR;
mbed_official 74:9322579e4309 465 __IO uint32_t MACA1HR;
mbed_official 74:9322579e4309 466 __IO uint32_t MACA1LR;
mbed_official 74:9322579e4309 467 __IO uint32_t MACA2HR;
mbed_official 74:9322579e4309 468 __IO uint32_t MACA2LR;
mbed_official 74:9322579e4309 469 __IO uint32_t MACA3HR;
mbed_official 74:9322579e4309 470 __IO uint32_t MACA3LR; /* 24 */
mbed_official 74:9322579e4309 471 uint32_t RESERVED2[40];
mbed_official 74:9322579e4309 472 __IO uint32_t MMCCR; /* 65 */
mbed_official 74:9322579e4309 473 __IO uint32_t MMCRIR;
mbed_official 74:9322579e4309 474 __IO uint32_t MMCTIR;
mbed_official 74:9322579e4309 475 __IO uint32_t MMCRIMR;
mbed_official 74:9322579e4309 476 __IO uint32_t MMCTIMR; /* 69 */
mbed_official 74:9322579e4309 477 uint32_t RESERVED3[14];
mbed_official 74:9322579e4309 478 __IO uint32_t MMCTGFSCCR; /* 84 */
mbed_official 74:9322579e4309 479 __IO uint32_t MMCTGFMSCCR;
mbed_official 74:9322579e4309 480 uint32_t RESERVED4[5];
mbed_official 74:9322579e4309 481 __IO uint32_t MMCTGFCR;
mbed_official 74:9322579e4309 482 uint32_t RESERVED5[10];
mbed_official 74:9322579e4309 483 __IO uint32_t MMCRFCECR;
mbed_official 74:9322579e4309 484 __IO uint32_t MMCRFAECR;
mbed_official 74:9322579e4309 485 uint32_t RESERVED6[10];
mbed_official 74:9322579e4309 486 __IO uint32_t MMCRGUFCR;
mbed_official 74:9322579e4309 487 uint32_t RESERVED7[334];
mbed_official 74:9322579e4309 488 __IO uint32_t PTPTSCR;
mbed_official 74:9322579e4309 489 __IO uint32_t PTPSSIR;
mbed_official 74:9322579e4309 490 __IO uint32_t PTPTSHR;
mbed_official 74:9322579e4309 491 __IO uint32_t PTPTSLR;
mbed_official 74:9322579e4309 492 __IO uint32_t PTPTSHUR;
mbed_official 74:9322579e4309 493 __IO uint32_t PTPTSLUR;
mbed_official 74:9322579e4309 494 __IO uint32_t PTPTSAR;
mbed_official 74:9322579e4309 495 __IO uint32_t PTPTTHR;
mbed_official 74:9322579e4309 496 __IO uint32_t PTPTTLR;
mbed_official 74:9322579e4309 497 __IO uint32_t RESERVED8;
mbed_official 74:9322579e4309 498 __IO uint32_t PTPTSSR;
mbed_official 74:9322579e4309 499 uint32_t RESERVED9[565];
mbed_official 74:9322579e4309 500 __IO uint32_t DMABMR;
mbed_official 74:9322579e4309 501 __IO uint32_t DMATPDR;
mbed_official 74:9322579e4309 502 __IO uint32_t DMARPDR;
mbed_official 74:9322579e4309 503 __IO uint32_t DMARDLAR;
mbed_official 74:9322579e4309 504 __IO uint32_t DMATDLAR;
mbed_official 74:9322579e4309 505 __IO uint32_t DMASR;
mbed_official 74:9322579e4309 506 __IO uint32_t DMAOMR;
mbed_official 74:9322579e4309 507 __IO uint32_t DMAIER;
mbed_official 74:9322579e4309 508 __IO uint32_t DMAMFBOCR;
mbed_official 74:9322579e4309 509 __IO uint32_t DMARSWTR;
mbed_official 74:9322579e4309 510 uint32_t RESERVED10[8];
mbed_official 74:9322579e4309 511 __IO uint32_t DMACHTDR;
mbed_official 74:9322579e4309 512 __IO uint32_t DMACHRDR;
mbed_official 74:9322579e4309 513 __IO uint32_t DMACHTBAR;
mbed_official 74:9322579e4309 514 __IO uint32_t DMACHRBAR;
mbed_official 74:9322579e4309 515 } ETH_TypeDef;
mbed_official 74:9322579e4309 516
mbed_official 74:9322579e4309 517 /**
mbed_official 74:9322579e4309 518 * @brief External Interrupt/Event Controller
mbed_official 74:9322579e4309 519 */
mbed_official 74:9322579e4309 520
mbed_official 74:9322579e4309 521 typedef struct
mbed_official 74:9322579e4309 522 {
mbed_official 74:9322579e4309 523 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 74:9322579e4309 524 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 74:9322579e4309 525 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 74:9322579e4309 526 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 74:9322579e4309 527 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 74:9322579e4309 528 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 74:9322579e4309 529 } EXTI_TypeDef;
mbed_official 74:9322579e4309 530
mbed_official 74:9322579e4309 531 /**
mbed_official 74:9322579e4309 532 * @brief FLASH Registers
mbed_official 74:9322579e4309 533 */
mbed_official 74:9322579e4309 534
mbed_official 74:9322579e4309 535 typedef struct
mbed_official 74:9322579e4309 536 {
mbed_official 74:9322579e4309 537 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 538 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 74:9322579e4309 539 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 74:9322579e4309 540 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 74:9322579e4309 541 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 74:9322579e4309 542 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 74:9322579e4309 543 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
mbed_official 74:9322579e4309 544 } FLASH_TypeDef;
mbed_official 74:9322579e4309 545
mbed_official 74:9322579e4309 546
mbed_official 74:9322579e4309 547
mbed_official 74:9322579e4309 548 /**
mbed_official 74:9322579e4309 549 * @brief Flexible Memory Controller
mbed_official 74:9322579e4309 550 */
mbed_official 74:9322579e4309 551
mbed_official 74:9322579e4309 552 typedef struct
mbed_official 74:9322579e4309 553 {
mbed_official 74:9322579e4309 554 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 74:9322579e4309 555 } FMC_Bank1_TypeDef;
mbed_official 74:9322579e4309 556
mbed_official 74:9322579e4309 557 /**
mbed_official 74:9322579e4309 558 * @brief Flexible Memory Controller Bank1E
mbed_official 74:9322579e4309 559 */
mbed_official 74:9322579e4309 560
mbed_official 74:9322579e4309 561 typedef struct
mbed_official 74:9322579e4309 562 {
mbed_official 74:9322579e4309 563 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 74:9322579e4309 564 } FMC_Bank1E_TypeDef;
mbed_official 74:9322579e4309 565
mbed_official 74:9322579e4309 566 /**
mbed_official 74:9322579e4309 567 * @brief Flexible Memory Controller Bank3
mbed_official 74:9322579e4309 568 */
mbed_official 74:9322579e4309 569
mbed_official 74:9322579e4309 570 typedef struct
mbed_official 74:9322579e4309 571 {
mbed_official 74:9322579e4309 572 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
mbed_official 74:9322579e4309 573 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
mbed_official 74:9322579e4309 574 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
mbed_official 74:9322579e4309 575 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
mbed_official 74:9322579e4309 576 uint32_t RESERVED0; /*!< Reserved, 0x90 */
mbed_official 74:9322579e4309 577 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
mbed_official 74:9322579e4309 578 } FMC_Bank3_TypeDef;
mbed_official 74:9322579e4309 579
mbed_official 74:9322579e4309 580 /**
mbed_official 74:9322579e4309 581 * @brief Flexible Memory Controller Bank5_6
mbed_official 74:9322579e4309 582 */
mbed_official 74:9322579e4309 583
mbed_official 74:9322579e4309 584 typedef struct
mbed_official 74:9322579e4309 585 {
mbed_official 74:9322579e4309 586 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
mbed_official 74:9322579e4309 587 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
mbed_official 74:9322579e4309 588 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
mbed_official 74:9322579e4309 589 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
mbed_official 74:9322579e4309 590 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
mbed_official 74:9322579e4309 591 } FMC_Bank5_6_TypeDef;
mbed_official 74:9322579e4309 592
mbed_official 74:9322579e4309 593
mbed_official 74:9322579e4309 594 /**
mbed_official 74:9322579e4309 595 * @brief General Purpose I/O
mbed_official 74:9322579e4309 596 */
mbed_official 74:9322579e4309 597
mbed_official 74:9322579e4309 598 typedef struct
mbed_official 74:9322579e4309 599 {
mbed_official 74:9322579e4309 600 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 74:9322579e4309 601 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 74:9322579e4309 602 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 74:9322579e4309 603 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 74:9322579e4309 604 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 74:9322579e4309 605 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 74:9322579e4309 606 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 74:9322579e4309 607 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 74:9322579e4309 608 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 74:9322579e4309 609 } GPIO_TypeDef;
mbed_official 74:9322579e4309 610
mbed_official 74:9322579e4309 611 /**
mbed_official 74:9322579e4309 612 * @brief System configuration controller
mbed_official 74:9322579e4309 613 */
mbed_official 74:9322579e4309 614
mbed_official 74:9322579e4309 615 typedef struct
mbed_official 74:9322579e4309 616 {
mbed_official 74:9322579e4309 617 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 74:9322579e4309 618 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 74:9322579e4309 619 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 144:ef7eb2e8f9f7 620 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 74:9322579e4309 621 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 74:9322579e4309 622 } SYSCFG_TypeDef;
mbed_official 74:9322579e4309 623
mbed_official 74:9322579e4309 624 /**
mbed_official 74:9322579e4309 625 * @brief Inter-integrated Circuit Interface
mbed_official 74:9322579e4309 626 */
mbed_official 74:9322579e4309 627
mbed_official 74:9322579e4309 628 typedef struct
mbed_official 74:9322579e4309 629 {
mbed_official 74:9322579e4309 630 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 74:9322579e4309 631 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 74:9322579e4309 632 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 74:9322579e4309 633 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 74:9322579e4309 634 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 74:9322579e4309 635 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 74:9322579e4309 636 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 74:9322579e4309 637 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 74:9322579e4309 638 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 74:9322579e4309 639 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 74:9322579e4309 640 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 74:9322579e4309 641 } I2C_TypeDef;
mbed_official 74:9322579e4309 642
mbed_official 74:9322579e4309 643 /**
mbed_official 74:9322579e4309 644 * @brief Independent WATCHDOG
mbed_official 74:9322579e4309 645 */
mbed_official 74:9322579e4309 646
mbed_official 74:9322579e4309 647 typedef struct
mbed_official 74:9322579e4309 648 {
mbed_official 74:9322579e4309 649 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 74:9322579e4309 650 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 74:9322579e4309 651 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 74:9322579e4309 652 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 74:9322579e4309 653 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 74:9322579e4309 654 } IWDG_TypeDef;
mbed_official 74:9322579e4309 655
mbed_official 74:9322579e4309 656
mbed_official 74:9322579e4309 657 /**
mbed_official 74:9322579e4309 658 * @brief LCD-TFT Display Controller
mbed_official 74:9322579e4309 659 */
mbed_official 74:9322579e4309 660
mbed_official 74:9322579e4309 661 typedef struct
mbed_official 74:9322579e4309 662 {
mbed_official 74:9322579e4309 663 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
mbed_official 74:9322579e4309 664 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
mbed_official 74:9322579e4309 665 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
mbed_official 74:9322579e4309 666 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
mbed_official 74:9322579e4309 667 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
mbed_official 74:9322579e4309 668 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
mbed_official 74:9322579e4309 669 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
mbed_official 74:9322579e4309 670 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
mbed_official 74:9322579e4309 671 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
mbed_official 74:9322579e4309 672 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
mbed_official 74:9322579e4309 673 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
mbed_official 74:9322579e4309 674 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
mbed_official 74:9322579e4309 675 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
mbed_official 74:9322579e4309 676 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
mbed_official 74:9322579e4309 677 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
mbed_official 74:9322579e4309 678 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
mbed_official 74:9322579e4309 679 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
mbed_official 74:9322579e4309 680 } LTDC_TypeDef;
mbed_official 74:9322579e4309 681
mbed_official 74:9322579e4309 682 /**
mbed_official 74:9322579e4309 683 * @brief LCD-TFT Display layer x Controller
mbed_official 74:9322579e4309 684 */
mbed_official 74:9322579e4309 685
mbed_official 74:9322579e4309 686 typedef struct
mbed_official 74:9322579e4309 687 {
mbed_official 74:9322579e4309 688 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
mbed_official 74:9322579e4309 689 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
mbed_official 74:9322579e4309 690 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
mbed_official 74:9322579e4309 691 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
mbed_official 74:9322579e4309 692 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
mbed_official 74:9322579e4309 693 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
mbed_official 74:9322579e4309 694 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
mbed_official 74:9322579e4309 695 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
mbed_official 74:9322579e4309 696 uint32_t RESERVED0[2]; /*!< Reserved */
mbed_official 74:9322579e4309 697 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
mbed_official 74:9322579e4309 698 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
mbed_official 74:9322579e4309 699 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
mbed_official 74:9322579e4309 700 uint32_t RESERVED1[3]; /*!< Reserved */
mbed_official 83:a036322b8637 701 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
mbed_official 74:9322579e4309 702
mbed_official 74:9322579e4309 703 } LTDC_Layer_TypeDef;
mbed_official 74:9322579e4309 704
mbed_official 74:9322579e4309 705 /**
mbed_official 74:9322579e4309 706 * @brief Power Control
mbed_official 74:9322579e4309 707 */
mbed_official 74:9322579e4309 708
mbed_official 74:9322579e4309 709 typedef struct
mbed_official 74:9322579e4309 710 {
mbed_official 74:9322579e4309 711 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
mbed_official 74:9322579e4309 712 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
mbed_official 74:9322579e4309 713 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
mbed_official 74:9322579e4309 714 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
mbed_official 74:9322579e4309 715 } PWR_TypeDef;
mbed_official 74:9322579e4309 716
mbed_official 74:9322579e4309 717
mbed_official 74:9322579e4309 718 /**
mbed_official 74:9322579e4309 719 * @brief Reset and Clock Control
mbed_official 74:9322579e4309 720 */
mbed_official 74:9322579e4309 721
mbed_official 74:9322579e4309 722 typedef struct
mbed_official 74:9322579e4309 723 {
mbed_official 74:9322579e4309 724 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 725 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 74:9322579e4309 726 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 74:9322579e4309 727 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 74:9322579e4309 728 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 74:9322579e4309 729 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 74:9322579e4309 730 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 74:9322579e4309 731 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 74:9322579e4309 732 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 74:9322579e4309 733 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 74:9322579e4309 734 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 74:9322579e4309 735 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 74:9322579e4309 736 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 74:9322579e4309 737 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 74:9322579e4309 738 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 74:9322579e4309 739 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 74:9322579e4309 740 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 74:9322579e4309 741 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 74:9322579e4309 742 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 74:9322579e4309 743 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 74:9322579e4309 744 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 74:9322579e4309 745 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 74:9322579e4309 746 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 74:9322579e4309 747 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 74:9322579e4309 748 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 74:9322579e4309 749 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 74:9322579e4309 750 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 74:9322579e4309 751 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 74:9322579e4309 752 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 74:9322579e4309 753 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 74:9322579e4309 754 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
mbed_official 74:9322579e4309 755 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
mbed_official 74:9322579e4309 756 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
mbed_official 74:9322579e4309 757
mbed_official 74:9322579e4309 758 } RCC_TypeDef;
mbed_official 74:9322579e4309 759
mbed_official 74:9322579e4309 760 /**
mbed_official 74:9322579e4309 761 * @brief Real-Time Clock
mbed_official 74:9322579e4309 762 */
mbed_official 74:9322579e4309 763
mbed_official 74:9322579e4309 764 typedef struct
mbed_official 74:9322579e4309 765 {
mbed_official 74:9322579e4309 766 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 74:9322579e4309 767 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 74:9322579e4309 768 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 74:9322579e4309 769 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 74:9322579e4309 770 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 74:9322579e4309 771 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 74:9322579e4309 772 uint32_t reserved; /*!< Reserved */
mbed_official 74:9322579e4309 773 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 74:9322579e4309 774 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 74:9322579e4309 775 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 74:9322579e4309 776 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 74:9322579e4309 777 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 74:9322579e4309 778 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 74:9322579e4309 779 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 74:9322579e4309 780 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 74:9322579e4309 781 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 74:9322579e4309 782 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
mbed_official 74:9322579e4309 783 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 74:9322579e4309 784 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 74:9322579e4309 785 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
mbed_official 74:9322579e4309 786 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 74:9322579e4309 787 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 74:9322579e4309 788 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 74:9322579e4309 789 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 74:9322579e4309 790 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 74:9322579e4309 791 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 74:9322579e4309 792 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 74:9322579e4309 793 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 74:9322579e4309 794 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 74:9322579e4309 795 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 74:9322579e4309 796 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 74:9322579e4309 797 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 74:9322579e4309 798 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 74:9322579e4309 799 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 74:9322579e4309 800 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 74:9322579e4309 801 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 74:9322579e4309 802 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 74:9322579e4309 803 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 74:9322579e4309 804 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 74:9322579e4309 805 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 74:9322579e4309 806 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
mbed_official 74:9322579e4309 807 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
mbed_official 74:9322579e4309 808 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
mbed_official 74:9322579e4309 809 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
mbed_official 74:9322579e4309 810 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
mbed_official 74:9322579e4309 811 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
mbed_official 74:9322579e4309 812 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
mbed_official 74:9322579e4309 813 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
mbed_official 74:9322579e4309 814 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
mbed_official 74:9322579e4309 815 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
mbed_official 74:9322579e4309 816 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
mbed_official 74:9322579e4309 817 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
mbed_official 74:9322579e4309 818 } RTC_TypeDef;
mbed_official 74:9322579e4309 819
mbed_official 74:9322579e4309 820
mbed_official 74:9322579e4309 821 /**
mbed_official 74:9322579e4309 822 * @brief Serial Audio Interface
mbed_official 74:9322579e4309 823 */
mbed_official 74:9322579e4309 824
mbed_official 74:9322579e4309 825 typedef struct
mbed_official 74:9322579e4309 826 {
mbed_official 74:9322579e4309 827 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
mbed_official 74:9322579e4309 828 } SAI_TypeDef;
mbed_official 74:9322579e4309 829
mbed_official 74:9322579e4309 830 typedef struct
mbed_official 74:9322579e4309 831 {
mbed_official 74:9322579e4309 832 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
mbed_official 74:9322579e4309 833 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
mbed_official 74:9322579e4309 834 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
mbed_official 74:9322579e4309 835 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
mbed_official 74:9322579e4309 836 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
mbed_official 74:9322579e4309 837 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
mbed_official 74:9322579e4309 838 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
mbed_official 74:9322579e4309 839 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
mbed_official 74:9322579e4309 840 } SAI_Block_TypeDef;
mbed_official 74:9322579e4309 841
mbed_official 74:9322579e4309 842 /**
mbed_official 74:9322579e4309 843 * @brief SPDIF-RX Interface
mbed_official 74:9322579e4309 844 */
mbed_official 74:9322579e4309 845
mbed_official 74:9322579e4309 846 typedef struct
mbed_official 74:9322579e4309 847 {
mbed_official 74:9322579e4309 848 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 849 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
mbed_official 74:9322579e4309 850 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 851 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
mbed_official 74:9322579e4309 852 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
mbed_official 74:9322579e4309 853 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
mbed_official 74:9322579e4309 854 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
mbed_official 74:9322579e4309 855 } SPDIFRX_TypeDef;
mbed_official 74:9322579e4309 856
mbed_official 74:9322579e4309 857
mbed_official 74:9322579e4309 858 /**
mbed_official 74:9322579e4309 859 * @brief SD host Interface
mbed_official 74:9322579e4309 860 */
mbed_official 74:9322579e4309 861
mbed_official 74:9322579e4309 862 typedef struct
mbed_official 74:9322579e4309 863 {
mbed_official 74:9322579e4309 864 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 865 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
mbed_official 74:9322579e4309 866 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
mbed_official 74:9322579e4309 867 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
mbed_official 74:9322579e4309 868 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
mbed_official 74:9322579e4309 869 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
mbed_official 74:9322579e4309 870 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
mbed_official 74:9322579e4309 871 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
mbed_official 74:9322579e4309 872 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
mbed_official 74:9322579e4309 873 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
mbed_official 74:9322579e4309 874 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
mbed_official 74:9322579e4309 875 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
mbed_official 74:9322579e4309 876 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
mbed_official 74:9322579e4309 877 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
mbed_official 74:9322579e4309 878 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
mbed_official 74:9322579e4309 879 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
mbed_official 74:9322579e4309 880 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 74:9322579e4309 881 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
mbed_official 74:9322579e4309 882 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 74:9322579e4309 883 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
mbed_official 74:9322579e4309 884 } SDMMC_TypeDef;
mbed_official 74:9322579e4309 885
mbed_official 74:9322579e4309 886 /**
mbed_official 74:9322579e4309 887 * @brief Serial Peripheral Interface
mbed_official 74:9322579e4309 888 */
mbed_official 74:9322579e4309 889
mbed_official 74:9322579e4309 890 typedef struct
mbed_official 74:9322579e4309 891 {
mbed_official 74:9322579e4309 892 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 74:9322579e4309 893 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 74:9322579e4309 894 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 895 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 74:9322579e4309 896 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 74:9322579e4309 897 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 74:9322579e4309 898 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 74:9322579e4309 899 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 74:9322579e4309 900 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 74:9322579e4309 901 } SPI_TypeDef;
mbed_official 74:9322579e4309 902
mbed_official 74:9322579e4309 903 /**
mbed_official 74:9322579e4309 904 * @brief QUAD Serial Peripheral Interface
mbed_official 74:9322579e4309 905 */
mbed_official 74:9322579e4309 906
mbed_official 74:9322579e4309 907 typedef struct
mbed_official 74:9322579e4309 908 {
mbed_official 74:9322579e4309 909 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 910 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
mbed_official 74:9322579e4309 911 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 912 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
mbed_official 74:9322579e4309 913 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
mbed_official 74:9322579e4309 914 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
mbed_official 74:9322579e4309 915 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
mbed_official 74:9322579e4309 916 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
mbed_official 74:9322579e4309 917 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
mbed_official 74:9322579e4309 918 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
mbed_official 74:9322579e4309 919 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
mbed_official 74:9322579e4309 920 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
mbed_official 74:9322579e4309 921 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
mbed_official 74:9322579e4309 922 } QUADSPI_TypeDef;
mbed_official 74:9322579e4309 923
mbed_official 74:9322579e4309 924 /**
mbed_official 74:9322579e4309 925 * @brief TIM
mbed_official 74:9322579e4309 926 */
mbed_official 74:9322579e4309 927
mbed_official 74:9322579e4309 928 typedef struct
mbed_official 74:9322579e4309 929 {
mbed_official 74:9322579e4309 930 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 74:9322579e4309 931 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 74:9322579e4309 932 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 74:9322579e4309 933 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 74:9322579e4309 934 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 74:9322579e4309 935 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 74:9322579e4309 936 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 74:9322579e4309 937 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 74:9322579e4309 938 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 74:9322579e4309 939 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 74:9322579e4309 940 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 74:9322579e4309 941 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 74:9322579e4309 942 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 74:9322579e4309 943 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 74:9322579e4309 944 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 74:9322579e4309 945 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 74:9322579e4309 946 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 74:9322579e4309 947 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 74:9322579e4309 948 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 74:9322579e4309 949 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 74:9322579e4309 950 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 74:9322579e4309 951 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 74:9322579e4309 952 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
mbed_official 74:9322579e4309 953 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
mbed_official 74:9322579e4309 954
mbed_official 74:9322579e4309 955 } TIM_TypeDef;
mbed_official 74:9322579e4309 956
mbed_official 74:9322579e4309 957 /**
mbed_official 74:9322579e4309 958 * @brief LPTIMIMER
mbed_official 74:9322579e4309 959 */
mbed_official 74:9322579e4309 960 typedef struct
mbed_official 74:9322579e4309 961 {
mbed_official 74:9322579e4309 962 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
mbed_official 74:9322579e4309 963 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
mbed_official 74:9322579e4309 964 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
mbed_official 74:9322579e4309 965 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
mbed_official 74:9322579e4309 966 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
mbed_official 74:9322579e4309 967 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
mbed_official 74:9322579e4309 968 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
mbed_official 74:9322579e4309 969 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
mbed_official 74:9322579e4309 970 } LPTIM_TypeDef;
mbed_official 74:9322579e4309 971
mbed_official 74:9322579e4309 972
mbed_official 74:9322579e4309 973 /**
mbed_official 74:9322579e4309 974 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 74:9322579e4309 975 */
mbed_official 74:9322579e4309 976
mbed_official 74:9322579e4309 977 typedef struct
mbed_official 74:9322579e4309 978 {
mbed_official 74:9322579e4309 979 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 74:9322579e4309 980 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 74:9322579e4309 981 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 74:9322579e4309 982 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 74:9322579e4309 983 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 74:9322579e4309 984 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 74:9322579e4309 985 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 74:9322579e4309 986 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 74:9322579e4309 987 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 74:9322579e4309 988 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 74:9322579e4309 989 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 74:9322579e4309 990 } USART_TypeDef;
mbed_official 74:9322579e4309 991
mbed_official 74:9322579e4309 992
mbed_official 74:9322579e4309 993 /**
mbed_official 74:9322579e4309 994 * @brief Window WATCHDOG
mbed_official 74:9322579e4309 995 */
mbed_official 74:9322579e4309 996
mbed_official 74:9322579e4309 997 typedef struct
mbed_official 74:9322579e4309 998 {
mbed_official 74:9322579e4309 999 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 1000 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 74:9322579e4309 1001 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 74:9322579e4309 1002 } WWDG_TypeDef;
mbed_official 74:9322579e4309 1003
mbed_official 83:a036322b8637 1004
mbed_official 74:9322579e4309 1005 /**
mbed_official 74:9322579e4309 1006 * @brief RNG
mbed_official 74:9322579e4309 1007 */
mbed_official 74:9322579e4309 1008
mbed_official 74:9322579e4309 1009 typedef struct
mbed_official 74:9322579e4309 1010 {
mbed_official 74:9322579e4309 1011 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 74:9322579e4309 1012 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 74:9322579e4309 1013 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 74:9322579e4309 1014 } RNG_TypeDef;
mbed_official 74:9322579e4309 1015
mbed_official 74:9322579e4309 1016 /**
mbed_official 74:9322579e4309 1017 * @}
mbed_official 74:9322579e4309 1018 */
mbed_official 74:9322579e4309 1019
mbed_official 74:9322579e4309 1020 /**
mbed_official 74:9322579e4309 1021 * @brief USB_OTG_Core_Registers
mbed_official 74:9322579e4309 1022 */
mbed_official 74:9322579e4309 1023 typedef struct
mbed_official 74:9322579e4309 1024 {
mbed_official 74:9322579e4309 1025 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
mbed_official 74:9322579e4309 1026 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
mbed_official 74:9322579e4309 1027 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
mbed_official 74:9322579e4309 1028 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
mbed_official 74:9322579e4309 1029 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
mbed_official 74:9322579e4309 1030 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
mbed_official 74:9322579e4309 1031 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
mbed_official 74:9322579e4309 1032 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
mbed_official 74:9322579e4309 1033 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
mbed_official 74:9322579e4309 1034 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
mbed_official 74:9322579e4309 1035 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
mbed_official 74:9322579e4309 1036 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
mbed_official 74:9322579e4309 1037 uint32_t Reserved30[2]; /*!< Reserved 030h */
mbed_official 74:9322579e4309 1038 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
mbed_official 74:9322579e4309 1039 __IO uint32_t CID; /*!< User ID Register 03Ch */
mbed_official 74:9322579e4309 1040 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
mbed_official 74:9322579e4309 1041 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
mbed_official 74:9322579e4309 1042 uint32_t Reserved6; /*!< Reserved 050h */
mbed_official 74:9322579e4309 1043 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
mbed_official 74:9322579e4309 1044 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
mbed_official 74:9322579e4309 1045 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
mbed_official 74:9322579e4309 1046 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
mbed_official 74:9322579e4309 1047 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
mbed_official 74:9322579e4309 1048 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
mbed_official 74:9322579e4309 1049 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
mbed_official 74:9322579e4309 1050 } USB_OTG_GlobalTypeDef;
mbed_official 74:9322579e4309 1051
mbed_official 74:9322579e4309 1052
mbed_official 74:9322579e4309 1053 /**
mbed_official 74:9322579e4309 1054 * @brief USB_OTG_device_Registers
mbed_official 74:9322579e4309 1055 */
mbed_official 74:9322579e4309 1056 typedef struct
mbed_official 74:9322579e4309 1057 {
mbed_official 74:9322579e4309 1058 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
mbed_official 74:9322579e4309 1059 __IO uint32_t DCTL; /*!< dev Control Register 804h */
mbed_official 74:9322579e4309 1060 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
mbed_official 74:9322579e4309 1061 uint32_t Reserved0C; /*!< Reserved 80Ch */
mbed_official 74:9322579e4309 1062 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
mbed_official 74:9322579e4309 1063 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
mbed_official 74:9322579e4309 1064 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
mbed_official 74:9322579e4309 1065 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
mbed_official 74:9322579e4309 1066 uint32_t Reserved20; /*!< Reserved 820h */
mbed_official 74:9322579e4309 1067 uint32_t Reserved9; /*!< Reserved 824h */
mbed_official 74:9322579e4309 1068 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
mbed_official 74:9322579e4309 1069 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
mbed_official 74:9322579e4309 1070 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
mbed_official 74:9322579e4309 1071 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
mbed_official 74:9322579e4309 1072 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
mbed_official 74:9322579e4309 1073 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
mbed_official 74:9322579e4309 1074 uint32_t Reserved40; /*!< dedicated EP mask 840h */
mbed_official 74:9322579e4309 1075 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
mbed_official 74:9322579e4309 1076 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
mbed_official 74:9322579e4309 1077 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
mbed_official 74:9322579e4309 1078 } USB_OTG_DeviceTypeDef;
mbed_official 74:9322579e4309 1079
mbed_official 74:9322579e4309 1080
mbed_official 74:9322579e4309 1081 /**
mbed_official 74:9322579e4309 1082 * @brief USB_OTG_IN_Endpoint-Specific_Register
mbed_official 74:9322579e4309 1083 */
mbed_official 74:9322579e4309 1084 typedef struct
mbed_official 74:9322579e4309 1085 {
mbed_official 74:9322579e4309 1086 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
mbed_official 74:9322579e4309 1087 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
mbed_official 74:9322579e4309 1088 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
mbed_official 74:9322579e4309 1089 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
mbed_official 74:9322579e4309 1090 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
mbed_official 74:9322579e4309 1091 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
mbed_official 74:9322579e4309 1092 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
mbed_official 74:9322579e4309 1093 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
mbed_official 74:9322579e4309 1094 } USB_OTG_INEndpointTypeDef;
mbed_official 74:9322579e4309 1095
mbed_official 74:9322579e4309 1096
mbed_official 74:9322579e4309 1097 /**
mbed_official 74:9322579e4309 1098 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
mbed_official 74:9322579e4309 1099 */
mbed_official 74:9322579e4309 1100 typedef struct
mbed_official 74:9322579e4309 1101 {
mbed_official 74:9322579e4309 1102 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
mbed_official 74:9322579e4309 1103 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
mbed_official 74:9322579e4309 1104 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
mbed_official 74:9322579e4309 1105 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
mbed_official 74:9322579e4309 1106 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
mbed_official 74:9322579e4309 1107 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
mbed_official 74:9322579e4309 1108 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
mbed_official 74:9322579e4309 1109 } USB_OTG_OUTEndpointTypeDef;
mbed_official 74:9322579e4309 1110
mbed_official 74:9322579e4309 1111
mbed_official 74:9322579e4309 1112 /**
mbed_official 74:9322579e4309 1113 * @brief USB_OTG_Host_Mode_Register_Structures
mbed_official 74:9322579e4309 1114 */
mbed_official 74:9322579e4309 1115 typedef struct
mbed_official 74:9322579e4309 1116 {
mbed_official 74:9322579e4309 1117 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
mbed_official 74:9322579e4309 1118 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
mbed_official 74:9322579e4309 1119 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
mbed_official 74:9322579e4309 1120 uint32_t Reserved40C; /*!< Reserved 40Ch */
mbed_official 74:9322579e4309 1121 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
mbed_official 74:9322579e4309 1122 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
mbed_official 74:9322579e4309 1123 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
mbed_official 74:9322579e4309 1124 } USB_OTG_HostTypeDef;
mbed_official 74:9322579e4309 1125
mbed_official 74:9322579e4309 1126 /**
mbed_official 74:9322579e4309 1127 * @brief USB_OTG_Host_Channel_Specific_Registers
mbed_official 74:9322579e4309 1128 */
mbed_official 74:9322579e4309 1129 typedef struct
mbed_official 74:9322579e4309 1130 {
mbed_official 74:9322579e4309 1131 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
mbed_official 74:9322579e4309 1132 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
mbed_official 74:9322579e4309 1133 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
mbed_official 74:9322579e4309 1134 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
mbed_official 74:9322579e4309 1135 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
mbed_official 74:9322579e4309 1136 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
mbed_official 74:9322579e4309 1137 uint32_t Reserved[2]; /*!< Reserved */
mbed_official 74:9322579e4309 1138 } USB_OTG_HostChannelTypeDef;
mbed_official 74:9322579e4309 1139 /**
mbed_official 74:9322579e4309 1140 * @}
mbed_official 74:9322579e4309 1141 */
mbed_official 74:9322579e4309 1142
mbed_official 83:a036322b8637 1143
mbed_official 83:a036322b8637 1144
<> 144:ef7eb2e8f9f7 1145
mbed_official 74:9322579e4309 1146 /** @addtogroup Peripheral_memory_map
mbed_official 74:9322579e4309 1147 * @{
mbed_official 74:9322579e4309 1148 */
<> 144:ef7eb2e8f9f7 1149 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
<> 144:ef7eb2e8f9f7 1150 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */
<> 144:ef7eb2e8f9f7 1151 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
<> 144:ef7eb2e8f9f7 1152 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
<> 144:ef7eb2e8f9f7 1153 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
<> 144:ef7eb2e8f9f7 1154 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
<> 144:ef7eb2e8f9f7 1155 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
<> 144:ef7eb2e8f9f7 1156 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
<> 144:ef7eb2e8f9f7 1157 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
<> 144:ef7eb2e8f9f7 1158 #define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
<> 144:ef7eb2e8f9f7 1159 #define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
<> 144:ef7eb2e8f9f7 1160 #define FLASH_END 0x080FFFFFU /*!< FLASH end address */
mbed_official 74:9322579e4309 1161
mbed_official 74:9322579e4309 1162 /* Legacy define */
mbed_official 74:9322579e4309 1163 #define FLASH_BASE FLASHAXI_BASE
mbed_official 74:9322579e4309 1164
mbed_official 74:9322579e4309 1165 /*!< Peripheral memory map */
mbed_official 74:9322579e4309 1166 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 1167 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 1168 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 144:ef7eb2e8f9f7 1169 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
mbed_official 74:9322579e4309 1170
mbed_official 74:9322579e4309 1171 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 1172 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1173 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1174 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1175 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1176 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1177 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1178 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1179 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1180 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1181 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 1182 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1183 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1184 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1185 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1186 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1187 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1188 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1189 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1190 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 144:ef7eb2e8f9f7 1191 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1192 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1193 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1194 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 1195 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 1196 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1197 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1198 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
<> 144:ef7eb2e8f9f7 1199 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 1200 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 144:ef7eb2e8f9f7 1201 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
<> 144:ef7eb2e8f9f7 1202 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
mbed_official 74:9322579e4309 1203
mbed_official 74:9322579e4309 1204 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 1205 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1206 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1207 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1208 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1209 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1210 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
<> 144:ef7eb2e8f9f7 1211 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
<> 144:ef7eb2e8f9f7 1212 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 144:ef7eb2e8f9f7 1213 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1214 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1215 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 1216 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1217 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1218 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1219 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1220 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1221 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1222 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1223 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1224 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 1225 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
<> 144:ef7eb2e8f9f7 1226 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
<> 144:ef7eb2e8f9f7 1227 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
<> 144:ef7eb2e8f9f7 1228 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
<> 144:ef7eb2e8f9f7 1229 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1230 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
<> 144:ef7eb2e8f9f7 1231 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
mbed_official 74:9322579e4309 1232 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 1233 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1234 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1235 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1236 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1237 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1238 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1239 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1240 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1241 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1242 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 1243 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1244 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1245 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1246 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1247 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
<> 144:ef7eb2e8f9f7 1248 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
<> 144:ef7eb2e8f9f7 1249 #define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
<> 144:ef7eb2e8f9f7 1250 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 1251 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1252 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1253 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1254 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1255 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1256 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1257 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1258 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1259 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1260 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1261 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1262 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1263 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1264 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1265 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1266 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1267 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1268 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
mbed_official 74:9322579e4309 1269 #define ETH_MAC_BASE (ETH_BASE)
<> 144:ef7eb2e8f9f7 1270 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
<> 144:ef7eb2e8f9f7 1271 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
<> 144:ef7eb2e8f9f7 1272 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1273 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
mbed_official 74:9322579e4309 1274 /*!< AHB2 peripherals */
<> 144:ef7eb2e8f9f7 1275 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
<> 144:ef7eb2e8f9f7 1276 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
mbed_official 74:9322579e4309 1277 /*!< FMC Bankx registers base address */
<> 144:ef7eb2e8f9f7 1278 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1279 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 144:ef7eb2e8f9f7 1280 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
<> 144:ef7eb2e8f9f7 1281 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
mbed_official 74:9322579e4309 1282
mbed_official 74:9322579e4309 1283 /* Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 1284 #define DBGMCU_BASE 0xE0042000U
mbed_official 74:9322579e4309 1285
mbed_official 74:9322579e4309 1286 /*!< USB registers base address */
<> 144:ef7eb2e8f9f7 1287 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
<> 144:ef7eb2e8f9f7 1288 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 #define USB_OTG_GLOBAL_BASE 0x000U
<> 144:ef7eb2e8f9f7 1291 #define USB_OTG_DEVICE_BASE 0x800U
<> 144:ef7eb2e8f9f7 1292 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 144:ef7eb2e8f9f7 1293 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 144:ef7eb2e8f9f7 1294 #define USB_OTG_EP_REG_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1295 #define USB_OTG_HOST_BASE 0x400U
<> 144:ef7eb2e8f9f7 1296 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 144:ef7eb2e8f9f7 1297 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 144:ef7eb2e8f9f7 1298 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1299 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 144:ef7eb2e8f9f7 1300 #define USB_OTG_FIFO_BASE 0x1000U
<> 144:ef7eb2e8f9f7 1301 #define USB_OTG_FIFO_SIZE 0x1000U
mbed_official 74:9322579e4309 1302
mbed_official 74:9322579e4309 1303 /**
mbed_official 74:9322579e4309 1304 * @}
mbed_official 74:9322579e4309 1305 */
mbed_official 74:9322579e4309 1306
mbed_official 74:9322579e4309 1307 /** @addtogroup Peripheral_declaration
mbed_official 74:9322579e4309 1308 * @{
mbed_official 74:9322579e4309 1309 */
mbed_official 74:9322579e4309 1310 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 74:9322579e4309 1311 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 74:9322579e4309 1312 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 74:9322579e4309 1313 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 74:9322579e4309 1314 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 74:9322579e4309 1315 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 74:9322579e4309 1316 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 74:9322579e4309 1317 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 74:9322579e4309 1318 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 74:9322579e4309 1319 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official 74:9322579e4309 1320 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 74:9322579e4309 1321 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 74:9322579e4309 1322 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 74:9322579e4309 1323 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 74:9322579e4309 1324 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 74:9322579e4309 1325 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
mbed_official 74:9322579e4309 1326 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 74:9322579e4309 1327 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 74:9322579e4309 1328 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 74:9322579e4309 1329 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 74:9322579e4309 1330 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 74:9322579e4309 1331 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 74:9322579e4309 1332 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 74:9322579e4309 1333 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
mbed_official 74:9322579e4309 1334 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 74:9322579e4309 1335 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 74:9322579e4309 1336 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 74:9322579e4309 1337 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 74:9322579e4309 1338 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 74:9322579e4309 1339 #define UART7 ((USART_TypeDef *) UART7_BASE)
mbed_official 74:9322579e4309 1340 #define UART8 ((USART_TypeDef *) UART8_BASE)
mbed_official 74:9322579e4309 1341 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 74:9322579e4309 1342 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 74:9322579e4309 1343 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 74:9322579e4309 1344 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 74:9322579e4309 1345 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 74:9322579e4309 1346 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 74:9322579e4309 1347 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 74:9322579e4309 1348 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 74:9322579e4309 1349 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
mbed_official 74:9322579e4309 1350 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 74:9322579e4309 1351 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 74:9322579e4309 1352 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 74:9322579e4309 1353 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 74:9322579e4309 1354 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 74:9322579e4309 1355 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 74:9322579e4309 1356 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 74:9322579e4309 1357 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 74:9322579e4309 1358 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
mbed_official 74:9322579e4309 1359 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
mbed_official 74:9322579e4309 1360 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
mbed_official 74:9322579e4309 1361 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
mbed_official 74:9322579e4309 1362 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
mbed_official 74:9322579e4309 1363 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
mbed_official 74:9322579e4309 1364 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
mbed_official 74:9322579e4309 1365 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
mbed_official 74:9322579e4309 1366 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
mbed_official 74:9322579e4309 1367 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
mbed_official 74:9322579e4309 1368 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 74:9322579e4309 1369 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 74:9322579e4309 1370 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 74:9322579e4309 1371 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 74:9322579e4309 1372 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 74:9322579e4309 1373 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 74:9322579e4309 1374 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 74:9322579e4309 1375 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 74:9322579e4309 1376 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
mbed_official 74:9322579e4309 1377 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
mbed_official 74:9322579e4309 1378 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
mbed_official 74:9322579e4309 1379 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 74:9322579e4309 1380 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 74:9322579e4309 1381 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 74:9322579e4309 1382 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 74:9322579e4309 1383 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 74:9322579e4309 1384 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 74:9322579e4309 1385 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 74:9322579e4309 1386 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 74:9322579e4309 1387 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 74:9322579e4309 1388 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 74:9322579e4309 1389 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 74:9322579e4309 1390 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 74:9322579e4309 1391 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 74:9322579e4309 1392 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 74:9322579e4309 1393 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 74:9322579e4309 1394 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 74:9322579e4309 1395 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 74:9322579e4309 1396 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 74:9322579e4309 1397 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 74:9322579e4309 1398 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 74:9322579e4309 1399 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 74:9322579e4309 1400 #define ETH ((ETH_TypeDef *) ETH_BASE)
mbed_official 74:9322579e4309 1401 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
mbed_official 74:9322579e4309 1402 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
mbed_official 74:9322579e4309 1403 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 74:9322579e4309 1404 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
mbed_official 74:9322579e4309 1405 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
mbed_official 74:9322579e4309 1406 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
mbed_official 74:9322579e4309 1407 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
mbed_official 74:9322579e4309 1408 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
mbed_official 74:9322579e4309 1409 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 74:9322579e4309 1410 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 74:9322579e4309 1411 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 74:9322579e4309 1412
mbed_official 74:9322579e4309 1413 /**
mbed_official 74:9322579e4309 1414 * @}
mbed_official 74:9322579e4309 1415 */
mbed_official 74:9322579e4309 1416
mbed_official 74:9322579e4309 1417 /** @addtogroup Exported_constants
mbed_official 74:9322579e4309 1418 * @{
mbed_official 74:9322579e4309 1419 */
mbed_official 74:9322579e4309 1420
mbed_official 74:9322579e4309 1421 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 74:9322579e4309 1422 * @{
mbed_official 74:9322579e4309 1423 */
mbed_official 74:9322579e4309 1424
mbed_official 74:9322579e4309 1425 /******************************************************************************/
mbed_official 74:9322579e4309 1426 /* Peripheral Registers_Bits_Definition */
mbed_official 74:9322579e4309 1427 /******************************************************************************/
mbed_official 74:9322579e4309 1428
mbed_official 74:9322579e4309 1429 /******************************************************************************/
mbed_official 74:9322579e4309 1430 /* */
mbed_official 74:9322579e4309 1431 /* Analog to Digital Converter */
mbed_official 74:9322579e4309 1432 /* */
mbed_official 74:9322579e4309 1433 /******************************************************************************/
mbed_official 74:9322579e4309 1434 /******************** Bit definition for ADC_SR register ********************/
<> 144:ef7eb2e8f9f7 1435 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1436 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 144:ef7eb2e8f9f7 1437 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1438 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1439 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1440 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
mbed_official 74:9322579e4309 1441
mbed_official 74:9322579e4309 1442 /******************* Bit definition for ADC_CR1 register ********************/
<> 144:ef7eb2e8f9f7 1443 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 144:ef7eb2e8f9f7 1444 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1445 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1446 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1447 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1448 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1449 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 144:ef7eb2e8f9f7 1450 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 144:ef7eb2e8f9f7 1451 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 144:ef7eb2e8f9f7 1452 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 144:ef7eb2e8f9f7 1453 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 144:ef7eb2e8f9f7 1454 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 144:ef7eb2e8f9f7 1455 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 144:ef7eb2e8f9f7 1456 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 144:ef7eb2e8f9f7 1457 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 144:ef7eb2e8f9f7 1458 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1459 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1460 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1461 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 144:ef7eb2e8f9f7 1462 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 144:ef7eb2e8f9f7 1463 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 144:ef7eb2e8f9f7 1464 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1465 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1466 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
mbed_official 74:9322579e4309 1467
mbed_official 74:9322579e4309 1468 /******************* Bit definition for ADC_CR2 register ********************/
<> 144:ef7eb2e8f9f7 1469 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 144:ef7eb2e8f9f7 1470 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 144:ef7eb2e8f9f7 1471 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 144:ef7eb2e8f9f7 1472 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 144:ef7eb2e8f9f7 1473 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 144:ef7eb2e8f9f7 1474 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 144:ef7eb2e8f9f7 1475 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 144:ef7eb2e8f9f7 1476 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1477 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1478 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1479 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1480 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 144:ef7eb2e8f9f7 1481 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1482 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1483 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 144:ef7eb2e8f9f7 1484 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 144:ef7eb2e8f9f7 1485 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1486 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1487 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1488 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1489 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 144:ef7eb2e8f9f7 1490 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1491 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1492 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
mbed_official 74:9322579e4309 1493
mbed_official 74:9322579e4309 1494 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 144:ef7eb2e8f9f7 1495 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 144:ef7eb2e8f9f7 1496 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1497 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1498 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1499 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 144:ef7eb2e8f9f7 1500 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1501 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1502 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1503 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 144:ef7eb2e8f9f7 1504 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1505 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1506 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1507 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 144:ef7eb2e8f9f7 1508 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1509 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1510 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1511 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 144:ef7eb2e8f9f7 1512 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1513 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1514 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1515 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 144:ef7eb2e8f9f7 1516 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1517 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1518 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1519 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 144:ef7eb2e8f9f7 1520 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1521 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1522 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1523 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 144:ef7eb2e8f9f7 1524 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1525 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1526 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1527 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 144:ef7eb2e8f9f7 1528 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1529 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1530 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
mbed_official 74:9322579e4309 1531
mbed_official 74:9322579e4309 1532 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 144:ef7eb2e8f9f7 1533 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 144:ef7eb2e8f9f7 1534 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1535 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1536 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1537 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 144:ef7eb2e8f9f7 1538 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1539 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1540 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1541 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 144:ef7eb2e8f9f7 1542 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1543 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1544 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1545 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 144:ef7eb2e8f9f7 1546 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1547 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1548 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1549 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 144:ef7eb2e8f9f7 1550 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1551 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1552 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1553 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 144:ef7eb2e8f9f7 1554 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1555 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1556 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1557 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 144:ef7eb2e8f9f7 1558 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1559 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1560 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1561 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 144:ef7eb2e8f9f7 1562 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1563 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1564 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1565 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 144:ef7eb2e8f9f7 1566 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1567 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1568 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1569 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 144:ef7eb2e8f9f7 1570 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1571 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1572 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
mbed_official 74:9322579e4309 1573
mbed_official 74:9322579e4309 1574 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 144:ef7eb2e8f9f7 1575 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
mbed_official 74:9322579e4309 1576
mbed_official 74:9322579e4309 1577 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 144:ef7eb2e8f9f7 1578 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
mbed_official 74:9322579e4309 1579
mbed_official 74:9322579e4309 1580 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 144:ef7eb2e8f9f7 1581 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
mbed_official 74:9322579e4309 1582
mbed_official 74:9322579e4309 1583 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 144:ef7eb2e8f9f7 1584 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
mbed_official 74:9322579e4309 1585
mbed_official 74:9322579e4309 1586 /******************* Bit definition for ADC_HTR register ********************/
<> 144:ef7eb2e8f9f7 1587 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
mbed_official 74:9322579e4309 1588
mbed_official 74:9322579e4309 1589 /******************* Bit definition for ADC_LTR register ********************/
<> 144:ef7eb2e8f9f7 1590 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
mbed_official 74:9322579e4309 1591
mbed_official 74:9322579e4309 1592 /******************* Bit definition for ADC_SQR1 register *******************/
<> 144:ef7eb2e8f9f7 1593 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1594 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1595 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1596 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1597 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1598 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1599 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1600 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1601 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1602 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1603 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1604 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1605 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1606 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1607 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1608 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1609 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1610 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1611 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1612 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1613 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1614 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1615 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1616 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1617 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 144:ef7eb2e8f9f7 1618 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1619 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1620 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1621 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
mbed_official 74:9322579e4309 1622
mbed_official 74:9322579e4309 1623 /******************* Bit definition for ADC_SQR2 register *******************/
<> 144:ef7eb2e8f9f7 1624 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1625 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1626 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1627 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1628 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1629 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1630 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1631 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1632 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1633 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1634 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1635 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1636 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1637 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1638 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1639 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1640 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1641 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1642 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1643 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1644 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1645 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1646 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1647 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1648 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1649 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1650 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1651 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1652 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1653 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1654 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1655 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1656 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1657 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1658 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1659 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
mbed_official 74:9322579e4309 1660
mbed_official 74:9322579e4309 1661 /******************* Bit definition for ADC_SQR3 register *******************/
<> 144:ef7eb2e8f9f7 1662 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1663 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1664 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1665 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1666 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1667 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1668 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1669 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1670 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1671 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1672 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1673 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1674 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1675 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1676 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1677 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1678 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1679 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1680 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1681 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1682 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1683 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1684 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1685 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1686 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1687 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1688 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1689 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1690 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1691 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1692 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 144:ef7eb2e8f9f7 1693 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1694 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1695 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1696 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1697 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
mbed_official 74:9322579e4309 1698
mbed_official 74:9322579e4309 1699 /******************* Bit definition for ADC_JSQR register *******************/
<> 144:ef7eb2e8f9f7 1700 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1701 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1702 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1703 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1704 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1705 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1706 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1707 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1708 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1709 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1710 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1711 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1712 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1713 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1714 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1715 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1716 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1717 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1718 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 144:ef7eb2e8f9f7 1719 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1720 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1721 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1722 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1723 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1724 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 144:ef7eb2e8f9f7 1725 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1726 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
mbed_official 74:9322579e4309 1727
mbed_official 74:9322579e4309 1728 /******************* Bit definition for ADC_JDR1 register *******************/
<> 144:ef7eb2e8f9f7 1729 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
mbed_official 74:9322579e4309 1730
mbed_official 74:9322579e4309 1731 /******************* Bit definition for ADC_JDR2 register *******************/
<> 144:ef7eb2e8f9f7 1732 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
mbed_official 74:9322579e4309 1733
mbed_official 74:9322579e4309 1734 /******************* Bit definition for ADC_JDR3 register *******************/
<> 144:ef7eb2e8f9f7 1735 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
mbed_official 74:9322579e4309 1736
mbed_official 74:9322579e4309 1737 /******************* Bit definition for ADC_JDR4 register *******************/
<> 144:ef7eb2e8f9f7 1738 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
mbed_official 74:9322579e4309 1739
mbed_official 74:9322579e4309 1740 /******************** Bit definition for ADC_DR register ********************/
<> 144:ef7eb2e8f9f7 1741 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 144:ef7eb2e8f9f7 1742 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
mbed_official 74:9322579e4309 1743
mbed_official 74:9322579e4309 1744 /******************* Bit definition for ADC_CSR register ********************/
<> 144:ef7eb2e8f9f7 1745 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1746 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 144:ef7eb2e8f9f7 1747 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1748 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1749 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1750 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
<> 144:ef7eb2e8f9f7 1751 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1752 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 144:ef7eb2e8f9f7 1753 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1754 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1755 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1756 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
<> 144:ef7eb2e8f9f7 1757 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 144:ef7eb2e8f9f7 1758 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 144:ef7eb2e8f9f7 1759 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 144:ef7eb2e8f9f7 1760 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 144:ef7eb2e8f9f7 1761 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 144:ef7eb2e8f9f7 1762 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1765 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 1766 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 1767 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 144:ef7eb2e8f9f7 1768
mbed_official 74:9322579e4309 1769
mbed_official 74:9322579e4309 1770 /******************* Bit definition for ADC_CCR register ********************/
<> 144:ef7eb2e8f9f7 1771 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 144:ef7eb2e8f9f7 1772 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1773 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1774 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1775 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1776 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 1777 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 144:ef7eb2e8f9f7 1778 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1779 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1780 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1781 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1782 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 144:ef7eb2e8f9f7 1783 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 144:ef7eb2e8f9f7 1784 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1785 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1786 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 144:ef7eb2e8f9f7 1787 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1788 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1789 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 144:ef7eb2e8f9f7 1790 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
mbed_official 74:9322579e4309 1791
mbed_official 74:9322579e4309 1792 /******************* Bit definition for ADC_CDR register ********************/
<> 144:ef7eb2e8f9f7 1793 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 144:ef7eb2e8f9f7 1794 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
mbed_official 74:9322579e4309 1795
mbed_official 74:9322579e4309 1796 /******************************************************************************/
mbed_official 74:9322579e4309 1797 /* */
mbed_official 74:9322579e4309 1798 /* Controller Area Network */
mbed_official 74:9322579e4309 1799 /* */
mbed_official 74:9322579e4309 1800 /******************************************************************************/
mbed_official 74:9322579e4309 1801 /*!<CAN control and status registers */
mbed_official 74:9322579e4309 1802 /******************* Bit definition for CAN_MCR register ********************/
<> 144:ef7eb2e8f9f7 1803 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
<> 144:ef7eb2e8f9f7 1804 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
<> 144:ef7eb2e8f9f7 1805 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
<> 144:ef7eb2e8f9f7 1806 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
<> 144:ef7eb2e8f9f7 1807 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
<> 144:ef7eb2e8f9f7 1808 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
<> 144:ef7eb2e8f9f7 1809 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
<> 144:ef7eb2e8f9f7 1810 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
<> 144:ef7eb2e8f9f7 1811 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
mbed_official 74:9322579e4309 1812
mbed_official 74:9322579e4309 1813 /******************* Bit definition for CAN_MSR register ********************/
<> 144:ef7eb2e8f9f7 1814 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
<> 144:ef7eb2e8f9f7 1815 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
<> 144:ef7eb2e8f9f7 1816 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
<> 144:ef7eb2e8f9f7 1817 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 1818 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
<> 144:ef7eb2e8f9f7 1819 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
<> 144:ef7eb2e8f9f7 1820 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
<> 144:ef7eb2e8f9f7 1821 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
<> 144:ef7eb2e8f9f7 1822 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
mbed_official 74:9322579e4309 1823
mbed_official 74:9322579e4309 1824 /******************* Bit definition for CAN_TSR register ********************/
<> 144:ef7eb2e8f9f7 1825 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
<> 144:ef7eb2e8f9f7 1826 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
<> 144:ef7eb2e8f9f7 1827 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
<> 144:ef7eb2e8f9f7 1828 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
<> 144:ef7eb2e8f9f7 1829 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
<> 144:ef7eb2e8f9f7 1830 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
<> 144:ef7eb2e8f9f7 1831 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
<> 144:ef7eb2e8f9f7 1832 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
<> 144:ef7eb2e8f9f7 1833 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
<> 144:ef7eb2e8f9f7 1834 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1835 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
<> 144:ef7eb2e8f9f7 1836 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1837 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
<> 144:ef7eb2e8f9f7 1838 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
<> 144:ef7eb2e8f9f7 1839 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
<> 144:ef7eb2e8f9f7 1840 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
<> 144:ef7eb2e8f9f7 1841
<> 144:ef7eb2e8f9f7 1842 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
<> 144:ef7eb2e8f9f7 1843 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
<> 144:ef7eb2e8f9f7 1844 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
<> 144:ef7eb2e8f9f7 1845 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
<> 144:ef7eb2e8f9f7 1848 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
<> 144:ef7eb2e8f9f7 1849 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
<> 144:ef7eb2e8f9f7 1850 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 74:9322579e4309 1851
mbed_official 74:9322579e4309 1852 /******************* Bit definition for CAN_RF0R register *******************/
<> 144:ef7eb2e8f9f7 1853 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
<> 144:ef7eb2e8f9f7 1854 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
<> 144:ef7eb2e8f9f7 1855 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
<> 144:ef7eb2e8f9f7 1856 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
mbed_official 74:9322579e4309 1857
mbed_official 74:9322579e4309 1858 /******************* Bit definition for CAN_RF1R register *******************/
<> 144:ef7eb2e8f9f7 1859 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
<> 144:ef7eb2e8f9f7 1860 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
<> 144:ef7eb2e8f9f7 1861 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
<> 144:ef7eb2e8f9f7 1862 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
mbed_official 74:9322579e4309 1863
mbed_official 74:9322579e4309 1864 /******************** Bit definition for CAN_IER register *******************/
<> 144:ef7eb2e8f9f7 1865 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 1866 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1867 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1868 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1869 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
<> 144:ef7eb2e8f9f7 1870 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
<> 144:ef7eb2e8f9f7 1871 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 1872 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
<> 144:ef7eb2e8f9f7 1873 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
<> 144:ef7eb2e8f9f7 1874 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
<> 144:ef7eb2e8f9f7 1875 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
<> 144:ef7eb2e8f9f7 1876 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 1877 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
<> 144:ef7eb2e8f9f7 1878 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
mbed_official 74:9322579e4309 1879
mbed_official 74:9322579e4309 1880 /******************** Bit definition for CAN_ESR register *******************/
<> 144:ef7eb2e8f9f7 1881 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
<> 144:ef7eb2e8f9f7 1882 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
<> 144:ef7eb2e8f9f7 1883 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
<> 144:ef7eb2e8f9f7 1886 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1887 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1888 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1889
<> 144:ef7eb2e8f9f7 1890 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 144:ef7eb2e8f9f7 1891 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
mbed_official 74:9322579e4309 1892
mbed_official 74:9322579e4309 1893 /******************* Bit definition for CAN_BTR register ********************/
<> 144:ef7eb2e8f9f7 1894 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
<> 144:ef7eb2e8f9f7 1895 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
<> 144:ef7eb2e8f9f7 1896 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1897 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1898 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1899 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 1900 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
<> 144:ef7eb2e8f9f7 1901 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1902 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1903 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 1904 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
<> 144:ef7eb2e8f9f7 1905 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 1906 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 1907 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
<> 144:ef7eb2e8f9f7 1908 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
mbed_official 74:9322579e4309 1909
mbed_official 74:9322579e4309 1910 /*!<Mailbox registers */
mbed_official 74:9322579e4309 1911 /****************** Bit definition for CAN_TI0R register ********************/
<> 144:ef7eb2e8f9f7 1912 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1913 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1914 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1915 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1916 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
mbed_official 74:9322579e4309 1917
mbed_official 74:9322579e4309 1918 /****************** Bit definition for CAN_TDT0R register *******************/
<> 144:ef7eb2e8f9f7 1919 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1920 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1921 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
mbed_official 74:9322579e4309 1922
mbed_official 74:9322579e4309 1923 /****************** Bit definition for CAN_TDL0R register *******************/
<> 144:ef7eb2e8f9f7 1924 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1925 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1926 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1927 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
mbed_official 74:9322579e4309 1928
mbed_official 74:9322579e4309 1929 /****************** Bit definition for CAN_TDH0R register *******************/
<> 144:ef7eb2e8f9f7 1930 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1931 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1932 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1933 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
mbed_official 74:9322579e4309 1934
mbed_official 74:9322579e4309 1935 /******************* Bit definition for CAN_TI1R register *******************/
<> 144:ef7eb2e8f9f7 1936 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1937 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1938 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1939 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1940 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
mbed_official 74:9322579e4309 1941
mbed_official 74:9322579e4309 1942 /******************* Bit definition for CAN_TDT1R register ******************/
<> 144:ef7eb2e8f9f7 1943 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1944 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1945 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
mbed_official 74:9322579e4309 1946
mbed_official 74:9322579e4309 1947 /******************* Bit definition for CAN_TDL1R register ******************/
<> 144:ef7eb2e8f9f7 1948 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1949 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1950 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1951 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
mbed_official 74:9322579e4309 1952
mbed_official 74:9322579e4309 1953 /******************* Bit definition for CAN_TDH1R register ******************/
<> 144:ef7eb2e8f9f7 1954 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1955 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1956 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1957 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
mbed_official 74:9322579e4309 1958
mbed_official 74:9322579e4309 1959 /******************* Bit definition for CAN_TI2R register *******************/
<> 144:ef7eb2e8f9f7 1960 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 144:ef7eb2e8f9f7 1961 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1962 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1963 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 1964 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
mbed_official 74:9322579e4309 1965
mbed_official 74:9322579e4309 1966 /******************* Bit definition for CAN_TDT2R register ******************/
<> 144:ef7eb2e8f9f7 1967 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1968 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
<> 144:ef7eb2e8f9f7 1969 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
mbed_official 74:9322579e4309 1970
mbed_official 74:9322579e4309 1971 /******************* Bit definition for CAN_TDL2R register ******************/
<> 144:ef7eb2e8f9f7 1972 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1973 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1974 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1975 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
mbed_official 74:9322579e4309 1976
mbed_official 74:9322579e4309 1977 /******************* Bit definition for CAN_TDH2R register ******************/
<> 144:ef7eb2e8f9f7 1978 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 1979 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 1980 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 1981 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
mbed_official 74:9322579e4309 1982
mbed_official 74:9322579e4309 1983 /******************* Bit definition for CAN_RI0R register *******************/
<> 144:ef7eb2e8f9f7 1984 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 1985 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 1986 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 144:ef7eb2e8f9f7 1987 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
mbed_official 74:9322579e4309 1988
mbed_official 74:9322579e4309 1989 /******************* Bit definition for CAN_RDT0R register ******************/
<> 144:ef7eb2e8f9f7 1990 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 1991 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 1992 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
mbed_official 74:9322579e4309 1993
mbed_official 74:9322579e4309 1994 /******************* Bit definition for CAN_RDL0R register ******************/
<> 144:ef7eb2e8f9f7 1995 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 1996 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 1997 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 1998 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
mbed_official 74:9322579e4309 1999
mbed_official 74:9322579e4309 2000 /******************* Bit definition for CAN_RDH0R register ******************/
<> 144:ef7eb2e8f9f7 2001 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 2002 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 2003 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 2004 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
mbed_official 74:9322579e4309 2005
mbed_official 74:9322579e4309 2006 /******************* Bit definition for CAN_RI1R register *******************/
<> 144:ef7eb2e8f9f7 2007 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 144:ef7eb2e8f9f7 2008 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 144:ef7eb2e8f9f7 2009 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 144:ef7eb2e8f9f7 2010 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
mbed_official 74:9322579e4309 2011
mbed_official 74:9322579e4309 2012 /******************* Bit definition for CAN_RDT1R register ******************/
<> 144:ef7eb2e8f9f7 2013 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 144:ef7eb2e8f9f7 2014 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 144:ef7eb2e8f9f7 2015 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
mbed_official 74:9322579e4309 2016
mbed_official 74:9322579e4309 2017 /******************* Bit definition for CAN_RDL1R register ******************/
<> 144:ef7eb2e8f9f7 2018 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 144:ef7eb2e8f9f7 2019 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 144:ef7eb2e8f9f7 2020 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 144:ef7eb2e8f9f7 2021 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
mbed_official 74:9322579e4309 2022
mbed_official 74:9322579e4309 2023 /******************* Bit definition for CAN_RDH1R register ******************/
<> 144:ef7eb2e8f9f7 2024 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 144:ef7eb2e8f9f7 2025 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 144:ef7eb2e8f9f7 2026 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 144:ef7eb2e8f9f7 2027 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
mbed_official 74:9322579e4309 2028
mbed_official 74:9322579e4309 2029 /*!<CAN filter registers */
mbed_official 74:9322579e4309 2030 /******************* Bit definition for CAN_FMR register ********************/
<> 144:ef7eb2e8f9f7 2031 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
<> 144:ef7eb2e8f9f7 2032 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
mbed_official 74:9322579e4309 2033
mbed_official 74:9322579e4309 2034 /******************* Bit definition for CAN_FM1R register *******************/
<> 144:ef7eb2e8f9f7 2035 #define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
<> 144:ef7eb2e8f9f7 2036 #define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
<> 144:ef7eb2e8f9f7 2037 #define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
<> 144:ef7eb2e8f9f7 2038 #define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
<> 144:ef7eb2e8f9f7 2039 #define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
<> 144:ef7eb2e8f9f7 2040 #define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
<> 144:ef7eb2e8f9f7 2041 #define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
<> 144:ef7eb2e8f9f7 2042 #define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
<> 144:ef7eb2e8f9f7 2043 #define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
<> 144:ef7eb2e8f9f7 2044 #define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
<> 144:ef7eb2e8f9f7 2045 #define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
<> 144:ef7eb2e8f9f7 2046 #define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
<> 144:ef7eb2e8f9f7 2047 #define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
<> 144:ef7eb2e8f9f7 2048 #define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
<> 144:ef7eb2e8f9f7 2049 #define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
mbed_official 74:9322579e4309 2050
mbed_official 74:9322579e4309 2051 /******************* Bit definition for CAN_FS1R register *******************/
<> 144:ef7eb2e8f9f7 2052 #define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
<> 144:ef7eb2e8f9f7 2053 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
<> 144:ef7eb2e8f9f7 2054 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
<> 144:ef7eb2e8f9f7 2055 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
<> 144:ef7eb2e8f9f7 2056 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
<> 144:ef7eb2e8f9f7 2057 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
<> 144:ef7eb2e8f9f7 2058 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
<> 144:ef7eb2e8f9f7 2059 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
<> 144:ef7eb2e8f9f7 2060 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
<> 144:ef7eb2e8f9f7 2061 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
<> 144:ef7eb2e8f9f7 2062 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
<> 144:ef7eb2e8f9f7 2063 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
<> 144:ef7eb2e8f9f7 2064 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
<> 144:ef7eb2e8f9f7 2065 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
<> 144:ef7eb2e8f9f7 2066 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
mbed_official 74:9322579e4309 2067
mbed_official 74:9322579e4309 2068 /****************** Bit definition for CAN_FFA1R register *******************/
<> 144:ef7eb2e8f9f7 2069 #define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
<> 144:ef7eb2e8f9f7 2070 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
<> 144:ef7eb2e8f9f7 2071 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
<> 144:ef7eb2e8f9f7 2072 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
<> 144:ef7eb2e8f9f7 2073 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
<> 144:ef7eb2e8f9f7 2074 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
<> 144:ef7eb2e8f9f7 2075 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
<> 144:ef7eb2e8f9f7 2076 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
<> 144:ef7eb2e8f9f7 2077 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
<> 144:ef7eb2e8f9f7 2078 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
<> 144:ef7eb2e8f9f7 2079 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
<> 144:ef7eb2e8f9f7 2080 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
<> 144:ef7eb2e8f9f7 2081 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
<> 144:ef7eb2e8f9f7 2082 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
<> 144:ef7eb2e8f9f7 2083 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 74:9322579e4309 2084
mbed_official 74:9322579e4309 2085 /******************* Bit definition for CAN_FA1R register *******************/
<> 144:ef7eb2e8f9f7 2086 #define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
<> 144:ef7eb2e8f9f7 2087 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
<> 144:ef7eb2e8f9f7 2088 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
<> 144:ef7eb2e8f9f7 2089 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
<> 144:ef7eb2e8f9f7 2090 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
<> 144:ef7eb2e8f9f7 2091 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
<> 144:ef7eb2e8f9f7 2092 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
<> 144:ef7eb2e8f9f7 2093 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
<> 144:ef7eb2e8f9f7 2094 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
<> 144:ef7eb2e8f9f7 2095 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
<> 144:ef7eb2e8f9f7 2096 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
<> 144:ef7eb2e8f9f7 2097 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
<> 144:ef7eb2e8f9f7 2098 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
<> 144:ef7eb2e8f9f7 2099 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
<> 144:ef7eb2e8f9f7 2100 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
mbed_official 74:9322579e4309 2101
mbed_official 74:9322579e4309 2102 /******************* Bit definition for CAN_F0R1 register *******************/
<> 144:ef7eb2e8f9f7 2103 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2104 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2105 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2106 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2107 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2108 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2109 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2110 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2111 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2112 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2113 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2114 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2115 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2116 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2117 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2118 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2119 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2120 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2121 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2122 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2123 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2124 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2125 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2126 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2127 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2128 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2129 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2130 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2131 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2132 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2133 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2134 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2135
mbed_official 74:9322579e4309 2136 /******************* Bit definition for CAN_F1R1 register *******************/
<> 144:ef7eb2e8f9f7 2137 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2138 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2139 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2140 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2141 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2142 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2143 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2144 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2145 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2146 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2147 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2148 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2149 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2150 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2151 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2152 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2153 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2154 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2155 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2156 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2157 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2158 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2159 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2160 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2161 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2162 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2163 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2164 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2165 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2166 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2167 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2168 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2169
mbed_official 74:9322579e4309 2170 /******************* Bit definition for CAN_F2R1 register *******************/
<> 144:ef7eb2e8f9f7 2171 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2172 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2173 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2174 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2175 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2176 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2177 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2178 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2179 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2180 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2181 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2182 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2183 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2184 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2185 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2186 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2187 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2188 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2189 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2190 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2191 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2192 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2193 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2194 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2195 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2196 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2197 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2198 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2199 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2200 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2201 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2202 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2203
mbed_official 74:9322579e4309 2204 /******************* Bit definition for CAN_F3R1 register *******************/
<> 144:ef7eb2e8f9f7 2205 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2206 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2207 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2208 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2209 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2210 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2211 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2212 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2213 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2214 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2215 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2216 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2217 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2218 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2219 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2220 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2221 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2222 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2223 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2224 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2225 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2226 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2227 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2228 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2229 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2230 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2231 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2232 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2233 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2234 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2235 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2236 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2237
mbed_official 74:9322579e4309 2238 /******************* Bit definition for CAN_F4R1 register *******************/
<> 144:ef7eb2e8f9f7 2239 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2240 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2241 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2242 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2243 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2244 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2245 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2246 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2247 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2248 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2249 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2250 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2251 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2252 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2253 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2254 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2255 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2256 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2257 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2258 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2259 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2260 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2261 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2262 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2263 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2264 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2265 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2266 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2267 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2268 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2269 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2270 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2271
mbed_official 74:9322579e4309 2272 /******************* Bit definition for CAN_F5R1 register *******************/
<> 144:ef7eb2e8f9f7 2273 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2274 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2275 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2276 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2277 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2278 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2279 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2280 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2281 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2282 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2283 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2284 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2285 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2286 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2287 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2288 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2289 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2290 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2291 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2292 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2293 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2294 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2295 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2296 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2297 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2298 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2299 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2300 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2301 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2302 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2303 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2304 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2305
mbed_official 74:9322579e4309 2306 /******************* Bit definition for CAN_F6R1 register *******************/
<> 144:ef7eb2e8f9f7 2307 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2308 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2309 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2310 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2311 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2312 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2313 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2314 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2315 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2316 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2317 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2318 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2319 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2320 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2321 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2322 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2323 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2324 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2325 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2326 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2327 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2328 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2329 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2330 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2331 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2332 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2333 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2334 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2335 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2336 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2337 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2338 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2339
mbed_official 74:9322579e4309 2340 /******************* Bit definition for CAN_F7R1 register *******************/
<> 144:ef7eb2e8f9f7 2341 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2342 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2343 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2344 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2345 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2346 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2347 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2348 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2349 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2350 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2351 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2352 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2353 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2354 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2355 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2356 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2357 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2358 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2359 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2360 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2361 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2362 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2363 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2364 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2365 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2366 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2367 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2368 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2369 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2370 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2371 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2372 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2373
mbed_official 74:9322579e4309 2374 /******************* Bit definition for CAN_F8R1 register *******************/
<> 144:ef7eb2e8f9f7 2375 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2376 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2377 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2378 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2379 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2380 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2381 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2382 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2383 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2384 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2385 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2386 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2387 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2388 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2389 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2390 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2391 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2392 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2393 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2394 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2395 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2396 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2397 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2398 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2399 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2400 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2401 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2402 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2403 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2404 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2405 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2406 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2407
mbed_official 74:9322579e4309 2408 /******************* Bit definition for CAN_F9R1 register *******************/
<> 144:ef7eb2e8f9f7 2409 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2410 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2411 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2412 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2413 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2414 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2415 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2416 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2417 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2418 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2419 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2420 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2421 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2422 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2423 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2424 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2425 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2426 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2427 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2428 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2429 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2430 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2431 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2432 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2433 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2434 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2435 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2436 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2437 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2438 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2439 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2440 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2441
mbed_official 74:9322579e4309 2442 /******************* Bit definition for CAN_F10R1 register ******************/
<> 144:ef7eb2e8f9f7 2443 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2444 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2445 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2446 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2447 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2448 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2449 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2450 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2451 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2452 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2453 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2454 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2455 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2456 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2457 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2458 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2459 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2460 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2461 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2462 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2463 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2464 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2465 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2466 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2467 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2468 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2469 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2470 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2471 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2472 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2473 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2474 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2475
mbed_official 74:9322579e4309 2476 /******************* Bit definition for CAN_F11R1 register ******************/
<> 144:ef7eb2e8f9f7 2477 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2478 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2479 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2480 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2481 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2482 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2483 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2484 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2485 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2486 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2487 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2488 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2489 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2490 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2491 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2492 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2493 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2494 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2495 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2496 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2497 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2498 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2499 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2500 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2501 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2502 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2503 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2504 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2505 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2506 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2507 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2508 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2509
mbed_official 74:9322579e4309 2510 /******************* Bit definition for CAN_F12R1 register ******************/
<> 144:ef7eb2e8f9f7 2511 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2512 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2513 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2514 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2515 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2516 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2517 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2518 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2519 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2520 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2521 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2522 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2523 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2524 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2525 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2526 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2527 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2528 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2529 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2530 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2531 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2532 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2533 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2534 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2535 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2536 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2537 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2538 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2539 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2540 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2541 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2542 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2543
mbed_official 74:9322579e4309 2544 /******************* Bit definition for CAN_F13R1 register ******************/
<> 144:ef7eb2e8f9f7 2545 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2546 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2547 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2548 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2549 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2550 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2551 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2552 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2553 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2554 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2555 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2556 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2557 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2558 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2559 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2560 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2561 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2562 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2563 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2564 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2565 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2566 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2567 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2568 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2569 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2570 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2571 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2572 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2573 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2574 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2575 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2576 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2577
mbed_official 74:9322579e4309 2578 /******************* Bit definition for CAN_F0R2 register *******************/
<> 144:ef7eb2e8f9f7 2579 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2580 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2581 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2582 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2583 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2584 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2585 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2586 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2587 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2588 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2589 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2590 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2591 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2592 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2593 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2594 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2595 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2596 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2597 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2598 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2599 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2600 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2601 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2602 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2603 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2604 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2605 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2606 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2607 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2608 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2609 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2610 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2611
mbed_official 74:9322579e4309 2612 /******************* Bit definition for CAN_F1R2 register *******************/
<> 144:ef7eb2e8f9f7 2613 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2614 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2615 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2616 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2617 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2618 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2619 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2620 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2621 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2622 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2623 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2624 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2625 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2626 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2627 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2628 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2629 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2630 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2631 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2632 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2633 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2634 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2635 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2636 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2637 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2638 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2639 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2640 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2641 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2642 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2643 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2644 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2645
mbed_official 74:9322579e4309 2646 /******************* Bit definition for CAN_F2R2 register *******************/
<> 144:ef7eb2e8f9f7 2647 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2648 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2649 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2650 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2651 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2652 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2653 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2654 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2655 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2656 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2657 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2658 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2659 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2660 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2661 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2662 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2663 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2664 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2665 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2666 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2667 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2668 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2669 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2670 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2671 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2672 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2673 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2674 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2675 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2676 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2677 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2678 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2679
mbed_official 74:9322579e4309 2680 /******************* Bit definition for CAN_F3R2 register *******************/
<> 144:ef7eb2e8f9f7 2681 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2682 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2683 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2684 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2685 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2686 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2687 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2688 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2689 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2690 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2691 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2692 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2693 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2694 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2695 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2696 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2697 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2698 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2699 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2700 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2701 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2702 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2703 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2704 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2705 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2706 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2707 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2708 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2709 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2710 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2711 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2712 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2713
mbed_official 74:9322579e4309 2714 /******************* Bit definition for CAN_F4R2 register *******************/
<> 144:ef7eb2e8f9f7 2715 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2716 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2717 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2718 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2719 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2720 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2721 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2722 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2723 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2724 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2725 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2726 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2727 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2728 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2729 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2730 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2731 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2732 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2733 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2734 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2735 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2736 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2737 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2738 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2739 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2740 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2741 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2742 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2743 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2744 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2745 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2746 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2747
mbed_official 74:9322579e4309 2748 /******************* Bit definition for CAN_F5R2 register *******************/
<> 144:ef7eb2e8f9f7 2749 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2750 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2751 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2752 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2753 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2754 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2755 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2756 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2757 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2758 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2759 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2760 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2761 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2762 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2763 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2764 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2765 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2766 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2767 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2768 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2769 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2770 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2771 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2772 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2773 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2774 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2775 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2776 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2777 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2778 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2779 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2780 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2781
mbed_official 74:9322579e4309 2782 /******************* Bit definition for CAN_F6R2 register *******************/
<> 144:ef7eb2e8f9f7 2783 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2784 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2785 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2786 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2787 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2788 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2789 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2790 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2791 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2792 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2793 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2794 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2795 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2796 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2797 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2798 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2799 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2800 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2801 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2802 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2803 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2804 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2805 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2806 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2807 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2808 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2809 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2810 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2811 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2812 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2813 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2814 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2815
mbed_official 74:9322579e4309 2816 /******************* Bit definition for CAN_F7R2 register *******************/
<> 144:ef7eb2e8f9f7 2817 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2818 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2819 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2820 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2821 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2822 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2823 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2824 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2825 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2826 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2827 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2828 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2829 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2830 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2831 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2832 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2833 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2834 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2835 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2836 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2837 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2838 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2839 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2840 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2841 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2842 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2843 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2844 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2845 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2846 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2847 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2848 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2849
mbed_official 74:9322579e4309 2850 /******************* Bit definition for CAN_F8R2 register *******************/
<> 144:ef7eb2e8f9f7 2851 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2852 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2853 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2854 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2855 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2856 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2857 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2858 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2859 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2860 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2861 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2862 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2863 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2864 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2865 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2866 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2867 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2868 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2869 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2870 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2871 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2872 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2873 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2874 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2875 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2876 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2877 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2878 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2879 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2880 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2881 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2882 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2883
mbed_official 74:9322579e4309 2884 /******************* Bit definition for CAN_F9R2 register *******************/
<> 144:ef7eb2e8f9f7 2885 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2886 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2887 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2888 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2889 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2890 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2891 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2892 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2893 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2894 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2895 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2896 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2897 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2898 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2899 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2900 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2901 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2902 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2903 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2904 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2905 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2906 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2907 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2908 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2909 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2910 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2911 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2912 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2913 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2914 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2915 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2916 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2917
mbed_official 74:9322579e4309 2918 /******************* Bit definition for CAN_F10R2 register ******************/
<> 144:ef7eb2e8f9f7 2919 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2920 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2921 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2922 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2923 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2924 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2925 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2926 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2927 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2928 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2929 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2930 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2931 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2932 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2933 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2934 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2935 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2936 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2937 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2938 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2939 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2940 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2941 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2942 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2943 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2944 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2945 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2946 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2947 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2948 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2949 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2950 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2951
mbed_official 74:9322579e4309 2952 /******************* Bit definition for CAN_F11R2 register ******************/
<> 144:ef7eb2e8f9f7 2953 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2954 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2955 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2956 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2957 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2958 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2959 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2960 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2961 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2962 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2963 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2964 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2965 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 2966 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 2967 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 2968 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 2969 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 2970 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 2971 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 2972 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 2973 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 2974 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 2975 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 2976 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 2977 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 2978 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 2979 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 2980 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 2981 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 2982 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 2983 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 2984 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 2985
mbed_official 74:9322579e4309 2986 /******************* Bit definition for CAN_F12R2 register ******************/
<> 144:ef7eb2e8f9f7 2987 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 2988 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 2989 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 2990 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 2991 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 2992 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 2993 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 2994 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 2995 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 2996 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 2997 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 2998 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 2999 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3000 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3001 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3002 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3003 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3004 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3005 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3006 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3007 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3008 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3009 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3010 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3011 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3012 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3013 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3014 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3015 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3016 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3017 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3018 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 3019
mbed_official 74:9322579e4309 3020 /******************* Bit definition for CAN_F13R2 register ******************/
<> 144:ef7eb2e8f9f7 3021 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 144:ef7eb2e8f9f7 3022 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 144:ef7eb2e8f9f7 3023 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 144:ef7eb2e8f9f7 3024 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 144:ef7eb2e8f9f7 3025 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 144:ef7eb2e8f9f7 3026 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 144:ef7eb2e8f9f7 3027 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 144:ef7eb2e8f9f7 3028 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 144:ef7eb2e8f9f7 3029 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 144:ef7eb2e8f9f7 3030 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 144:ef7eb2e8f9f7 3031 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 144:ef7eb2e8f9f7 3032 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 144:ef7eb2e8f9f7 3033 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 144:ef7eb2e8f9f7 3034 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 144:ef7eb2e8f9f7 3035 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 144:ef7eb2e8f9f7 3036 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 144:ef7eb2e8f9f7 3037 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 144:ef7eb2e8f9f7 3038 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 144:ef7eb2e8f9f7 3039 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 144:ef7eb2e8f9f7 3040 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 144:ef7eb2e8f9f7 3041 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 144:ef7eb2e8f9f7 3042 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 144:ef7eb2e8f9f7 3043 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 144:ef7eb2e8f9f7 3044 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 144:ef7eb2e8f9f7 3045 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 144:ef7eb2e8f9f7 3046 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 144:ef7eb2e8f9f7 3047 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 144:ef7eb2e8f9f7 3048 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 144:ef7eb2e8f9f7 3049 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 144:ef7eb2e8f9f7 3050 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 144:ef7eb2e8f9f7 3051 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 144:ef7eb2e8f9f7 3052 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
mbed_official 74:9322579e4309 3053
mbed_official 74:9322579e4309 3054 /******************************************************************************/
mbed_official 74:9322579e4309 3055 /* */
mbed_official 74:9322579e4309 3056 /* HDMI-CEC (CEC) */
mbed_official 74:9322579e4309 3057 /* */
mbed_official 74:9322579e4309 3058 /******************************************************************************/
mbed_official 74:9322579e4309 3059
mbed_official 74:9322579e4309 3060 /******************* Bit definition for CEC_CR register *********************/
<> 144:ef7eb2e8f9f7 3061 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
<> 144:ef7eb2e8f9f7 3062 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
<> 144:ef7eb2e8f9f7 3063 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
mbed_official 74:9322579e4309 3064
mbed_official 74:9322579e4309 3065 /******************* Bit definition for CEC_CFGR register *******************/
<> 144:ef7eb2e8f9f7 3066 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
<> 144:ef7eb2e8f9f7 3067 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
<> 144:ef7eb2e8f9f7 3068 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
<> 144:ef7eb2e8f9f7 3069 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
<> 144:ef7eb2e8f9f7 3070 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
<> 144:ef7eb2e8f9f7 3071 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
<> 144:ef7eb2e8f9f7 3072 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
<> 144:ef7eb2e8f9f7 3073 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
<> 144:ef7eb2e8f9f7 3074 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
mbed_official 74:9322579e4309 3075
mbed_official 74:9322579e4309 3076 /******************* Bit definition for CEC_TXDR register *******************/
<> 144:ef7eb2e8f9f7 3077 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
mbed_official 74:9322579e4309 3078
mbed_official 74:9322579e4309 3079 /******************* Bit definition for CEC_RXDR register *******************/
<> 144:ef7eb2e8f9f7 3080 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
mbed_official 74:9322579e4309 3081
mbed_official 74:9322579e4309 3082 /******************* Bit definition for CEC_ISR register ********************/
<> 144:ef7eb2e8f9f7 3083 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
<> 144:ef7eb2e8f9f7 3084 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
<> 144:ef7eb2e8f9f7 3085 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
<> 144:ef7eb2e8f9f7 3086 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
<> 144:ef7eb2e8f9f7 3087 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
<> 144:ef7eb2e8f9f7 3088 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
<> 144:ef7eb2e8f9f7 3089 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
<> 144:ef7eb2e8f9f7 3090 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
<> 144:ef7eb2e8f9f7 3091 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
<> 144:ef7eb2e8f9f7 3092 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
<> 144:ef7eb2e8f9f7 3093 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
<> 144:ef7eb2e8f9f7 3094 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
<> 144:ef7eb2e8f9f7 3095 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
mbed_official 74:9322579e4309 3096
mbed_official 74:9322579e4309 3097 /******************* Bit definition for CEC_IER register ********************/
<> 144:ef7eb2e8f9f7 3098 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
<> 144:ef7eb2e8f9f7 3099 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
<> 144:ef7eb2e8f9f7 3100 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
<> 144:ef7eb2e8f9f7 3101 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
<> 144:ef7eb2e8f9f7 3102 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
<> 144:ef7eb2e8f9f7 3103 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
<> 144:ef7eb2e8f9f7 3104 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
<> 144:ef7eb2e8f9f7 3105 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
<> 144:ef7eb2e8f9f7 3106 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
<> 144:ef7eb2e8f9f7 3107 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
<> 144:ef7eb2e8f9f7 3108 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
<> 144:ef7eb2e8f9f7 3109 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
<> 144:ef7eb2e8f9f7 3110 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 74:9322579e4309 3111
mbed_official 74:9322579e4309 3112 /******************************************************************************/
mbed_official 74:9322579e4309 3113 /* */
mbed_official 74:9322579e4309 3114 /* CRC calculation unit */
mbed_official 74:9322579e4309 3115 /* */
mbed_official 74:9322579e4309 3116 /******************************************************************************/
mbed_official 74:9322579e4309 3117 /******************* Bit definition for CRC_DR register *********************/
<> 144:ef7eb2e8f9f7 3118 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
mbed_official 74:9322579e4309 3119
mbed_official 74:9322579e4309 3120 /******************* Bit definition for CRC_IDR register ********************/
<> 144:ef7eb2e8f9f7 3121 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
mbed_official 74:9322579e4309 3122
mbed_official 74:9322579e4309 3123 /******************** Bit definition for CRC_CR register ********************/
<> 144:ef7eb2e8f9f7 3124 #define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
<> 144:ef7eb2e8f9f7 3125 #define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
<> 144:ef7eb2e8f9f7 3126 #define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
<> 144:ef7eb2e8f9f7 3127 #define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
<> 144:ef7eb2e8f9f7 3128 #define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
<> 144:ef7eb2e8f9f7 3129 #define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 3130 #define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 3131 #define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
mbed_official 74:9322579e4309 3132
mbed_official 74:9322579e4309 3133 /******************* Bit definition for CRC_INIT register *******************/
<> 144:ef7eb2e8f9f7 3134 #define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
mbed_official 74:9322579e4309 3135
mbed_official 74:9322579e4309 3136 /******************* Bit definition for CRC_POL register ********************/
<> 144:ef7eb2e8f9f7 3137 #define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
mbed_official 74:9322579e4309 3138
mbed_official 83:a036322b8637 3139
mbed_official 74:9322579e4309 3140 /******************************************************************************/
mbed_official 74:9322579e4309 3141 /* */
mbed_official 74:9322579e4309 3142 /* Digital to Analog Converter */
mbed_official 74:9322579e4309 3143 /* */
mbed_official 74:9322579e4309 3144 /******************************************************************************/
mbed_official 74:9322579e4309 3145 /******************** Bit definition for DAC_CR register ********************/
<> 144:ef7eb2e8f9f7 3146 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
<> 144:ef7eb2e8f9f7 3147 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
<> 144:ef7eb2e8f9f7 3148 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
<> 144:ef7eb2e8f9f7 3149 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 144:ef7eb2e8f9f7 3150 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3151 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3152 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3153 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
<> 144:ef7eb2e8f9f7 3154 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3155 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3156 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 3157 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3158 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3159 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3160 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3161 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
<> 144:ef7eb2e8f9f7 3162 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
<> 144:ef7eb2e8f9f7 3163 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
<> 144:ef7eb2e8f9f7 3164 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
<> 144:ef7eb2e8f9f7 3165 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
<> 144:ef7eb2e8f9f7 3166 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 144:ef7eb2e8f9f7 3167 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3168 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3169 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3170 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 144:ef7eb2e8f9f7 3171 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3172 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3173 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 144:ef7eb2e8f9f7 3174 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3175 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3176 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 3177 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 3178 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
<> 144:ef7eb2e8f9f7 3179 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
mbed_official 74:9322579e4309 3180
mbed_official 74:9322579e4309 3181 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 144:ef7eb2e8f9f7 3182 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
<> 144:ef7eb2e8f9f7 3183 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
mbed_official 74:9322579e4309 3184
mbed_official 74:9322579e4309 3185 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 144:ef7eb2e8f9f7 3186 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
mbed_official 74:9322579e4309 3187
mbed_official 74:9322579e4309 3188 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 144:ef7eb2e8f9f7 3189 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
mbed_official 74:9322579e4309 3190
mbed_official 74:9322579e4309 3191 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 144:ef7eb2e8f9f7 3192 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
mbed_official 74:9322579e4309 3193
mbed_official 74:9322579e4309 3194 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 144:ef7eb2e8f9f7 3195 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
mbed_official 74:9322579e4309 3196
mbed_official 74:9322579e4309 3197 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 144:ef7eb2e8f9f7 3198 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
mbed_official 74:9322579e4309 3199
mbed_official 74:9322579e4309 3200 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 144:ef7eb2e8f9f7 3201 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
mbed_official 74:9322579e4309 3202
mbed_official 74:9322579e4309 3203 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 144:ef7eb2e8f9f7 3204 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 3205 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
mbed_official 74:9322579e4309 3206
mbed_official 74:9322579e4309 3207 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 144:ef7eb2e8f9f7 3208 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 3209 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
mbed_official 74:9322579e4309 3210
mbed_official 74:9322579e4309 3211 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 144:ef7eb2e8f9f7 3212 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 3213 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
mbed_official 74:9322579e4309 3214
mbed_official 74:9322579e4309 3215 /******************* Bit definition for DAC_DOR1 register *******************/
<> 144:ef7eb2e8f9f7 3216 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
mbed_official 74:9322579e4309 3217
mbed_official 74:9322579e4309 3218 /******************* Bit definition for DAC_DOR2 register *******************/
<> 144:ef7eb2e8f9f7 3219 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
mbed_official 74:9322579e4309 3220
mbed_official 74:9322579e4309 3221 /******************** Bit definition for DAC_SR register ********************/
<> 144:ef7eb2e8f9f7 3222 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
<> 144:ef7eb2e8f9f7 3223 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
mbed_official 74:9322579e4309 3224
mbed_official 83:a036322b8637 3225
mbed_official 74:9322579e4309 3226 /******************************************************************************/
mbed_official 74:9322579e4309 3227 /* */
mbed_official 74:9322579e4309 3228 /* Debug MCU */
mbed_official 74:9322579e4309 3229 /* */
mbed_official 74:9322579e4309 3230 /******************************************************************************/
mbed_official 74:9322579e4309 3231
mbed_official 74:9322579e4309 3232 /******************************************************************************/
mbed_official 74:9322579e4309 3233 /* */
mbed_official 74:9322579e4309 3234 /* DCMI */
mbed_official 74:9322579e4309 3235 /* */
mbed_official 74:9322579e4309 3236 /******************************************************************************/
mbed_official 74:9322579e4309 3237 /******************** Bits definition for DCMI_CR register ******************/
<> 144:ef7eb2e8f9f7 3238 #define DCMI_CR_CAPTURE 0x00000001U
<> 144:ef7eb2e8f9f7 3239 #define DCMI_CR_CM 0x00000002U
<> 144:ef7eb2e8f9f7 3240 #define DCMI_CR_CROP 0x00000004U
<> 144:ef7eb2e8f9f7 3241 #define DCMI_CR_JPEG 0x00000008U
<> 144:ef7eb2e8f9f7 3242 #define DCMI_CR_ESS 0x00000010U
<> 144:ef7eb2e8f9f7 3243 #define DCMI_CR_PCKPOL 0x00000020U
<> 144:ef7eb2e8f9f7 3244 #define DCMI_CR_HSPOL 0x00000040U
<> 144:ef7eb2e8f9f7 3245 #define DCMI_CR_VSPOL 0x00000080U
<> 144:ef7eb2e8f9f7 3246 #define DCMI_CR_FCRC_0 0x00000100U
<> 144:ef7eb2e8f9f7 3247 #define DCMI_CR_FCRC_1 0x00000200U
<> 144:ef7eb2e8f9f7 3248 #define DCMI_CR_EDM_0 0x00000400U
<> 144:ef7eb2e8f9f7 3249 #define DCMI_CR_EDM_1 0x00000800U
<> 144:ef7eb2e8f9f7 3250 #define DCMI_CR_CRE 0x00001000U
<> 144:ef7eb2e8f9f7 3251 #define DCMI_CR_ENABLE 0x00004000U
<> 144:ef7eb2e8f9f7 3252 #define DCMI_CR_BSM 0x00030000U
<> 144:ef7eb2e8f9f7 3253 #define DCMI_CR_BSM_0 0x00010000U
<> 144:ef7eb2e8f9f7 3254 #define DCMI_CR_BSM_1 0x00020000U
<> 144:ef7eb2e8f9f7 3255 #define DCMI_CR_OEBS 0x00040000U
<> 144:ef7eb2e8f9f7 3256 #define DCMI_CR_LSM 0x00080000U
<> 144:ef7eb2e8f9f7 3257 #define DCMI_CR_OELS 0x00100000U
mbed_official 74:9322579e4309 3258
mbed_official 74:9322579e4309 3259 /******************** Bits definition for DCMI_SR register ******************/
<> 144:ef7eb2e8f9f7 3260 #define DCMI_SR_HSYNC 0x00000001U
<> 144:ef7eb2e8f9f7 3261 #define DCMI_SR_VSYNC 0x00000002U
<> 144:ef7eb2e8f9f7 3262 #define DCMI_SR_FNE 0x00000004U
<> 144:ef7eb2e8f9f7 3263
<> 144:ef7eb2e8f9f7 3264 /******************** Bits definition for DCMI_RIS register ****************/
<> 144:ef7eb2e8f9f7 3265 #define DCMI_RIS_FRAME_RIS 0x00000001U
<> 144:ef7eb2e8f9f7 3266 #define DCMI_RIS_OVR_RIS 0x00000002U
<> 144:ef7eb2e8f9f7 3267 #define DCMI_RIS_ERR_RIS 0x00000004U
<> 144:ef7eb2e8f9f7 3268 #define DCMI_RIS_VSYNC_RIS 0x00000008U
<> 144:ef7eb2e8f9f7 3269 #define DCMI_RIS_LINE_RIS 0x00000010U
<> 144:ef7eb2e8f9f7 3270
<> 144:ef7eb2e8f9f7 3271 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3272 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
<> 144:ef7eb2e8f9f7 3273 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
<> 144:ef7eb2e8f9f7 3274 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
<> 144:ef7eb2e8f9f7 3275 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
<> 144:ef7eb2e8f9f7 3276 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
mbed_official 74:9322579e4309 3277
mbed_official 74:9322579e4309 3278 /******************** Bits definition for DCMI_IER register *****************/
<> 144:ef7eb2e8f9f7 3279 #define DCMI_IER_FRAME_IE 0x00000001U
<> 144:ef7eb2e8f9f7 3280 #define DCMI_IER_OVR_IE 0x00000002U
<> 144:ef7eb2e8f9f7 3281 #define DCMI_IER_ERR_IE 0x00000004U
<> 144:ef7eb2e8f9f7 3282 #define DCMI_IER_VSYNC_IE 0x00000008U
<> 144:ef7eb2e8f9f7 3283 #define DCMI_IER_LINE_IE 0x00000010U
<> 144:ef7eb2e8f9f7 3284
<> 144:ef7eb2e8f9f7 3285 /* Legacy define */
<> 144:ef7eb2e8f9f7 3286 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
<> 144:ef7eb2e8f9f7 3287
<> 144:ef7eb2e8f9f7 3288 /******************** Bits definition for DCMI_MIS register *****************/
<> 144:ef7eb2e8f9f7 3289 #define DCMI_MIS_FRAME_MIS 0x00000001U
<> 144:ef7eb2e8f9f7 3290 #define DCMI_MIS_OVR_MIS 0x00000002U
<> 144:ef7eb2e8f9f7 3291 #define DCMI_MIS_ERR_MIS 0x00000004U
<> 144:ef7eb2e8f9f7 3292 #define DCMI_MIS_VSYNC_MIS 0x00000008U
<> 144:ef7eb2e8f9f7 3293 #define DCMI_MIS_LINE_MIS 0x00000010U
<> 144:ef7eb2e8f9f7 3294
<> 144:ef7eb2e8f9f7 3295 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3296 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
<> 144:ef7eb2e8f9f7 3297 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
<> 144:ef7eb2e8f9f7 3298 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
<> 144:ef7eb2e8f9f7 3299 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
<> 144:ef7eb2e8f9f7 3300 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
mbed_official 74:9322579e4309 3301
mbed_official 74:9322579e4309 3302 /******************** Bits definition for DCMI_ICR register *****************/
<> 144:ef7eb2e8f9f7 3303 #define DCMI_ICR_FRAME_ISC 0x00000001U
<> 144:ef7eb2e8f9f7 3304 #define DCMI_ICR_OVR_ISC 0x00000002U
<> 144:ef7eb2e8f9f7 3305 #define DCMI_ICR_ERR_ISC 0x00000004U
<> 144:ef7eb2e8f9f7 3306 #define DCMI_ICR_VSYNC_ISC 0x00000008U
<> 144:ef7eb2e8f9f7 3307 #define DCMI_ICR_LINE_ISC 0x00000010U
<> 144:ef7eb2e8f9f7 3308
<> 144:ef7eb2e8f9f7 3309 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3310 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
<> 144:ef7eb2e8f9f7 3311
<> 144:ef7eb2e8f9f7 3312 /******************** Bits definition for DCMI_ESCR register ******************/
<> 144:ef7eb2e8f9f7 3313 #define DCMI_ESCR_FSC 0x000000FFU
<> 144:ef7eb2e8f9f7 3314 #define DCMI_ESCR_LSC 0x0000FF00U
<> 144:ef7eb2e8f9f7 3315 #define DCMI_ESCR_LEC 0x00FF0000U
<> 144:ef7eb2e8f9f7 3316 #define DCMI_ESCR_FEC 0xFF000000U
<> 144:ef7eb2e8f9f7 3317
<> 144:ef7eb2e8f9f7 3318 /******************** Bits definition for DCMI_ESUR register ******************/
<> 144:ef7eb2e8f9f7 3319 #define DCMI_ESUR_FSU 0x000000FFU
<> 144:ef7eb2e8f9f7 3320 #define DCMI_ESUR_LSU 0x0000FF00U
<> 144:ef7eb2e8f9f7 3321 #define DCMI_ESUR_LEU 0x00FF0000U
<> 144:ef7eb2e8f9f7 3322 #define DCMI_ESUR_FEU 0xFF000000U
<> 144:ef7eb2e8f9f7 3323
<> 144:ef7eb2e8f9f7 3324 /******************** Bits definition for DCMI_CWSTRT register ******************/
<> 144:ef7eb2e8f9f7 3325 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
<> 144:ef7eb2e8f9f7 3326 #define DCMI_CWSTRT_VST 0x1FFF0000U
<> 144:ef7eb2e8f9f7 3327
<> 144:ef7eb2e8f9f7 3328 /******************** Bits definition for DCMI_CWSIZE register ******************/
<> 144:ef7eb2e8f9f7 3329 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
<> 144:ef7eb2e8f9f7 3330 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
<> 144:ef7eb2e8f9f7 3331
<> 144:ef7eb2e8f9f7 3332 /******************** Bits definition for DCMI_DR register ******************/
<> 144:ef7eb2e8f9f7 3333 #define DCMI_DR_BYTE0 0x000000FFU
<> 144:ef7eb2e8f9f7 3334 #define DCMI_DR_BYTE1 0x0000FF00U
<> 144:ef7eb2e8f9f7 3335 #define DCMI_DR_BYTE2 0x00FF0000U
<> 144:ef7eb2e8f9f7 3336 #define DCMI_DR_BYTE3 0xFF000000U
mbed_official 74:9322579e4309 3337
mbed_official 74:9322579e4309 3338 /******************************************************************************/
mbed_official 74:9322579e4309 3339 /* */
mbed_official 74:9322579e4309 3340 /* DMA Controller */
mbed_official 74:9322579e4309 3341 /* */
mbed_official 74:9322579e4309 3342 /******************************************************************************/
mbed_official 74:9322579e4309 3343 /******************** Bits definition for DMA_SxCR register *****************/
<> 144:ef7eb2e8f9f7 3344 #define DMA_SxCR_CHSEL 0x0E000000U
<> 144:ef7eb2e8f9f7 3345 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 144:ef7eb2e8f9f7 3346 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 144:ef7eb2e8f9f7 3347 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 144:ef7eb2e8f9f7 3348 #define DMA_SxCR_MBURST 0x01800000U
<> 144:ef7eb2e8f9f7 3349 #define DMA_SxCR_MBURST_0 0x00800000U
<> 144:ef7eb2e8f9f7 3350 #define DMA_SxCR_MBURST_1 0x01000000U
<> 144:ef7eb2e8f9f7 3351 #define DMA_SxCR_PBURST 0x00600000U
<> 144:ef7eb2e8f9f7 3352 #define DMA_SxCR_PBURST_0 0x00200000U
<> 144:ef7eb2e8f9f7 3353 #define DMA_SxCR_PBURST_1 0x00400000U
<> 144:ef7eb2e8f9f7 3354 #define DMA_SxCR_CT 0x00080000U
<> 144:ef7eb2e8f9f7 3355 #define DMA_SxCR_DBM 0x00040000U
<> 144:ef7eb2e8f9f7 3356 #define DMA_SxCR_PL 0x00030000U
<> 144:ef7eb2e8f9f7 3357 #define DMA_SxCR_PL_0 0x00010000U
<> 144:ef7eb2e8f9f7 3358 #define DMA_SxCR_PL_1 0x00020000U
<> 144:ef7eb2e8f9f7 3359 #define DMA_SxCR_PINCOS 0x00008000U
<> 144:ef7eb2e8f9f7 3360 #define DMA_SxCR_MSIZE 0x00006000U
<> 144:ef7eb2e8f9f7 3361 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 144:ef7eb2e8f9f7 3362 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 144:ef7eb2e8f9f7 3363 #define DMA_SxCR_PSIZE 0x00001800U
<> 144:ef7eb2e8f9f7 3364 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 144:ef7eb2e8f9f7 3365 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 144:ef7eb2e8f9f7 3366 #define DMA_SxCR_MINC 0x00000400U
<> 144:ef7eb2e8f9f7 3367 #define DMA_SxCR_PINC 0x00000200U
<> 144:ef7eb2e8f9f7 3368 #define DMA_SxCR_CIRC 0x00000100U
<> 144:ef7eb2e8f9f7 3369 #define DMA_SxCR_DIR 0x000000C0U
<> 144:ef7eb2e8f9f7 3370 #define DMA_SxCR_DIR_0 0x00000040U
<> 144:ef7eb2e8f9f7 3371 #define DMA_SxCR_DIR_1 0x00000080U
<> 144:ef7eb2e8f9f7 3372 #define DMA_SxCR_PFCTRL 0x00000020U
<> 144:ef7eb2e8f9f7 3373 #define DMA_SxCR_TCIE 0x00000010U
<> 144:ef7eb2e8f9f7 3374 #define DMA_SxCR_HTIE 0x00000008U
<> 144:ef7eb2e8f9f7 3375 #define DMA_SxCR_TEIE 0x00000004U
<> 144:ef7eb2e8f9f7 3376 #define DMA_SxCR_DMEIE 0x00000002U
<> 144:ef7eb2e8f9f7 3377 #define DMA_SxCR_EN 0x00000001U
mbed_official 74:9322579e4309 3378
mbed_official 74:9322579e4309 3379 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 144:ef7eb2e8f9f7 3380 #define DMA_SxNDT 0x0000FFFFU
<> 144:ef7eb2e8f9f7 3381 #define DMA_SxNDT_0 0x00000001U
<> 144:ef7eb2e8f9f7 3382 #define DMA_SxNDT_1 0x00000002U
<> 144:ef7eb2e8f9f7 3383 #define DMA_SxNDT_2 0x00000004U
<> 144:ef7eb2e8f9f7 3384 #define DMA_SxNDT_3 0x00000008U
<> 144:ef7eb2e8f9f7 3385 #define DMA_SxNDT_4 0x00000010U
<> 144:ef7eb2e8f9f7 3386 #define DMA_SxNDT_5 0x00000020U
<> 144:ef7eb2e8f9f7 3387 #define DMA_SxNDT_6 0x00000040U
<> 144:ef7eb2e8f9f7 3388 #define DMA_SxNDT_7 0x00000080U
<> 144:ef7eb2e8f9f7 3389 #define DMA_SxNDT_8 0x00000100U
<> 144:ef7eb2e8f9f7 3390 #define DMA_SxNDT_9 0x00000200U
<> 144:ef7eb2e8f9f7 3391 #define DMA_SxNDT_10 0x00000400U
<> 144:ef7eb2e8f9f7 3392 #define DMA_SxNDT_11 0x00000800U
<> 144:ef7eb2e8f9f7 3393 #define DMA_SxNDT_12 0x00001000U
<> 144:ef7eb2e8f9f7 3394 #define DMA_SxNDT_13 0x00002000U
<> 144:ef7eb2e8f9f7 3395 #define DMA_SxNDT_14 0x00004000U
<> 144:ef7eb2e8f9f7 3396 #define DMA_SxNDT_15 0x00008000U
mbed_official 74:9322579e4309 3397
mbed_official 74:9322579e4309 3398 /******************** Bits definition for DMA_SxFCR register ****************/
<> 144:ef7eb2e8f9f7 3399 #define DMA_SxFCR_FEIE 0x00000080U
<> 144:ef7eb2e8f9f7 3400 #define DMA_SxFCR_FS 0x00000038U
<> 144:ef7eb2e8f9f7 3401 #define DMA_SxFCR_FS_0 0x00000008U
<> 144:ef7eb2e8f9f7 3402 #define DMA_SxFCR_FS_1 0x00000010U
<> 144:ef7eb2e8f9f7 3403 #define DMA_SxFCR_FS_2 0x00000020U
<> 144:ef7eb2e8f9f7 3404 #define DMA_SxFCR_DMDIS 0x00000004U
<> 144:ef7eb2e8f9f7 3405 #define DMA_SxFCR_FTH 0x00000003U
<> 144:ef7eb2e8f9f7 3406 #define DMA_SxFCR_FTH_0 0x00000001U
<> 144:ef7eb2e8f9f7 3407 #define DMA_SxFCR_FTH_1 0x00000002U
mbed_official 74:9322579e4309 3408
mbed_official 74:9322579e4309 3409 /******************** Bits definition for DMA_LISR register *****************/
<> 144:ef7eb2e8f9f7 3410 #define DMA_LISR_TCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 3411 #define DMA_LISR_HTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 3412 #define DMA_LISR_TEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 3413 #define DMA_LISR_DMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 3414 #define DMA_LISR_FEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 3415 #define DMA_LISR_TCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 3416 #define DMA_LISR_HTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 3417 #define DMA_LISR_TEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 3418 #define DMA_LISR_DMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 3419 #define DMA_LISR_FEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 3420 #define DMA_LISR_TCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 3421 #define DMA_LISR_HTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 3422 #define DMA_LISR_TEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 3423 #define DMA_LISR_DMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 3424 #define DMA_LISR_FEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 3425 #define DMA_LISR_TCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 3426 #define DMA_LISR_HTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 3427 #define DMA_LISR_TEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 3428 #define DMA_LISR_DMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 3429 #define DMA_LISR_FEIF0 0x00000001U
mbed_official 74:9322579e4309 3430
mbed_official 74:9322579e4309 3431 /******************** Bits definition for DMA_HISR register *****************/
<> 144:ef7eb2e8f9f7 3432 #define DMA_HISR_TCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 3433 #define DMA_HISR_HTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 3434 #define DMA_HISR_TEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 3435 #define DMA_HISR_DMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 3436 #define DMA_HISR_FEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 3437 #define DMA_HISR_TCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 3438 #define DMA_HISR_HTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 3439 #define DMA_HISR_TEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 3440 #define DMA_HISR_DMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 3441 #define DMA_HISR_FEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 3442 #define DMA_HISR_TCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 3443 #define DMA_HISR_HTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 3444 #define DMA_HISR_TEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 3445 #define DMA_HISR_DMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 3446 #define DMA_HISR_FEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 3447 #define DMA_HISR_TCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 3448 #define DMA_HISR_HTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 3449 #define DMA_HISR_TEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 3450 #define DMA_HISR_DMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 3451 #define DMA_HISR_FEIF4 0x00000001U
mbed_official 74:9322579e4309 3452
mbed_official 74:9322579e4309 3453 /******************** Bits definition for DMA_LIFCR register ****************/
<> 144:ef7eb2e8f9f7 3454 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 144:ef7eb2e8f9f7 3455 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 144:ef7eb2e8f9f7 3456 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 144:ef7eb2e8f9f7 3457 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 144:ef7eb2e8f9f7 3458 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 144:ef7eb2e8f9f7 3459 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 144:ef7eb2e8f9f7 3460 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 144:ef7eb2e8f9f7 3461 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 144:ef7eb2e8f9f7 3462 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 144:ef7eb2e8f9f7 3463 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 144:ef7eb2e8f9f7 3464 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 144:ef7eb2e8f9f7 3465 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 144:ef7eb2e8f9f7 3466 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 144:ef7eb2e8f9f7 3467 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 144:ef7eb2e8f9f7 3468 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 144:ef7eb2e8f9f7 3469 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 144:ef7eb2e8f9f7 3470 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 144:ef7eb2e8f9f7 3471 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 144:ef7eb2e8f9f7 3472 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 144:ef7eb2e8f9f7 3473 #define DMA_LIFCR_CFEIF0 0x00000001U
mbed_official 74:9322579e4309 3474
mbed_official 74:9322579e4309 3475 /******************** Bits definition for DMA_HIFCR register ****************/
<> 144:ef7eb2e8f9f7 3476 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 144:ef7eb2e8f9f7 3477 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 144:ef7eb2e8f9f7 3478 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 144:ef7eb2e8f9f7 3479 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 144:ef7eb2e8f9f7 3480 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 144:ef7eb2e8f9f7 3481 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 144:ef7eb2e8f9f7 3482 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 144:ef7eb2e8f9f7 3483 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 144:ef7eb2e8f9f7 3484 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 144:ef7eb2e8f9f7 3485 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 144:ef7eb2e8f9f7 3486 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 144:ef7eb2e8f9f7 3487 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 144:ef7eb2e8f9f7 3488 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 144:ef7eb2e8f9f7 3489 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 144:ef7eb2e8f9f7 3490 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 144:ef7eb2e8f9f7 3491 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 144:ef7eb2e8f9f7 3492 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 144:ef7eb2e8f9f7 3493 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 144:ef7eb2e8f9f7 3494 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 144:ef7eb2e8f9f7 3495 #define DMA_HIFCR_CFEIF4 0x00000001U
mbed_official 74:9322579e4309 3496
mbed_official 74:9322579e4309 3497 /******************************************************************************/
mbed_official 74:9322579e4309 3498 /* */
mbed_official 74:9322579e4309 3499 /* AHB Master DMA2D Controller (DMA2D) */
mbed_official 74:9322579e4309 3500 /* */
mbed_official 74:9322579e4309 3501 /******************************************************************************/
mbed_official 74:9322579e4309 3502
mbed_official 74:9322579e4309 3503 /******************** Bit definition for DMA2D_CR register ******************/
mbed_official 74:9322579e4309 3504
<> 144:ef7eb2e8f9f7 3505 #define DMA2D_CR_START 0x00000001U /*!< Start transfer */
<> 144:ef7eb2e8f9f7 3506 #define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
<> 144:ef7eb2e8f9f7 3507 #define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
<> 144:ef7eb2e8f9f7 3508 #define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3509 #define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 3510 #define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
<> 144:ef7eb2e8f9f7 3511 #define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3512 #define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 3513 #define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 3514 #define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
<> 144:ef7eb2e8f9f7 3515 #define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
<> 144:ef7eb2e8f9f7 3516 #define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
mbed_official 74:9322579e4309 3517
mbed_official 74:9322579e4309 3518 /******************** Bit definition for DMA2D_ISR register *****************/
mbed_official 74:9322579e4309 3519
<> 144:ef7eb2e8f9f7 3520 #define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3521 #define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3522 #define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 3523 #define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3524 #define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3525 #define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3526
<> 144:ef7eb2e8f9f7 3527 /******************** Bit definition for DMA2D_IFCR register ****************/
<> 144:ef7eb2e8f9f7 3528
<> 144:ef7eb2e8f9f7 3529 #define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3530 #define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3531 #define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 3532 #define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3533 #define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3534 #define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3535
<> 144:ef7eb2e8f9f7 3536 /* Legacy defines */
<> 144:ef7eb2e8f9f7 3537 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3538 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3539 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 3540 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 3541 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 3542 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
mbed_official 74:9322579e4309 3543
mbed_official 74:9322579e4309 3544 /******************** Bit definition for DMA2D_FGMAR register ***************/
mbed_official 74:9322579e4309 3545
<> 144:ef7eb2e8f9f7 3546 #define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
mbed_official 74:9322579e4309 3547
mbed_official 74:9322579e4309 3548 /******************** Bit definition for DMA2D_FGOR register ****************/
mbed_official 74:9322579e4309 3549
<> 144:ef7eb2e8f9f7 3550 #define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
mbed_official 74:9322579e4309 3551
mbed_official 74:9322579e4309 3552 /******************** Bit definition for DMA2D_BGMAR register ***************/
mbed_official 74:9322579e4309 3553
<> 144:ef7eb2e8f9f7 3554 #define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
mbed_official 74:9322579e4309 3555
mbed_official 74:9322579e4309 3556 /******************** Bit definition for DMA2D_BGOR register ****************/
mbed_official 74:9322579e4309 3557
<> 144:ef7eb2e8f9f7 3558 #define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
mbed_official 74:9322579e4309 3559
mbed_official 74:9322579e4309 3560 /******************** Bit definition for DMA2D_FGPFCCR register *************/
mbed_official 74:9322579e4309 3561
<> 144:ef7eb2e8f9f7 3562 #define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
<> 144:ef7eb2e8f9f7 3563 #define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
<> 144:ef7eb2e8f9f7 3564 #define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
<> 144:ef7eb2e8f9f7 3565 #define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
<> 144:ef7eb2e8f9f7 3566 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
<> 144:ef7eb2e8f9f7 3567 #define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
<> 144:ef7eb2e8f9f7 3568 #define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
<> 144:ef7eb2e8f9f7 3569 #define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
<> 144:ef7eb2e8f9f7 3570 #define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
<> 144:ef7eb2e8f9f7 3571 #define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
<> 144:ef7eb2e8f9f7 3572 #define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
<> 144:ef7eb2e8f9f7 3573 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
mbed_official 74:9322579e4309 3574
mbed_official 74:9322579e4309 3575 /******************** Bit definition for DMA2D_FGCOLR register **************/
mbed_official 74:9322579e4309 3576
<> 144:ef7eb2e8f9f7 3577 #define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
<> 144:ef7eb2e8f9f7 3578 #define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
<> 144:ef7eb2e8f9f7 3579 #define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
mbed_official 74:9322579e4309 3580
mbed_official 74:9322579e4309 3581 /******************** Bit definition for DMA2D_BGPFCCR register *************/
mbed_official 74:9322579e4309 3582
<> 144:ef7eb2e8f9f7 3583 #define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
<> 144:ef7eb2e8f9f7 3584 #define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
<> 144:ef7eb2e8f9f7 3585 #define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
<> 144:ef7eb2e8f9f7 3586 #define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
<> 144:ef7eb2e8f9f7 3587 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
<> 144:ef7eb2e8f9f7 3588 #define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
<> 144:ef7eb2e8f9f7 3589 #define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
<> 144:ef7eb2e8f9f7 3590 #define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
<> 144:ef7eb2e8f9f7 3591 #define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
<> 144:ef7eb2e8f9f7 3592 #define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
<> 144:ef7eb2e8f9f7 3593 #define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
<> 144:ef7eb2e8f9f7 3594 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
mbed_official 74:9322579e4309 3595
mbed_official 74:9322579e4309 3596 /******************** Bit definition for DMA2D_BGCOLR register **************/
mbed_official 74:9322579e4309 3597
<> 144:ef7eb2e8f9f7 3598 #define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
<> 144:ef7eb2e8f9f7 3599 #define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
<> 144:ef7eb2e8f9f7 3600 #define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
mbed_official 74:9322579e4309 3601
mbed_official 74:9322579e4309 3602 /******************** Bit definition for DMA2D_FGCMAR register **************/
mbed_official 74:9322579e4309 3603
<> 144:ef7eb2e8f9f7 3604 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
mbed_official 74:9322579e4309 3605
mbed_official 74:9322579e4309 3606 /******************** Bit definition for DMA2D_BGCMAR register **************/
mbed_official 74:9322579e4309 3607
<> 144:ef7eb2e8f9f7 3608 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
mbed_official 74:9322579e4309 3609
mbed_official 74:9322579e4309 3610 /******************** Bit definition for DMA2D_OPFCCR register **************/
mbed_official 74:9322579e4309 3611
<> 144:ef7eb2e8f9f7 3612 #define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
<> 144:ef7eb2e8f9f7 3613 #define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
<> 144:ef7eb2e8f9f7 3614 #define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
<> 144:ef7eb2e8f9f7 3615 #define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
mbed_official 74:9322579e4309 3616
mbed_official 74:9322579e4309 3617 /******************** Bit definition for DMA2D_OCOLR register ***************/
mbed_official 74:9322579e4309 3618
mbed_official 74:9322579e4309 3619 /*!<Mode_ARGB8888/RGB888 */
mbed_official 74:9322579e4309 3620
<> 144:ef7eb2e8f9f7 3621 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
<> 144:ef7eb2e8f9f7 3622 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
<> 144:ef7eb2e8f9f7 3623 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
<> 144:ef7eb2e8f9f7 3624 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
mbed_official 74:9322579e4309 3625
mbed_official 74:9322579e4309 3626 /*!<Mode_RGB565 */
<> 144:ef7eb2e8f9f7 3627 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
<> 144:ef7eb2e8f9f7 3628 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
<> 144:ef7eb2e8f9f7 3629 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
mbed_official 74:9322579e4309 3630
mbed_official 74:9322579e4309 3631 /*!<Mode_ARGB1555 */
<> 144:ef7eb2e8f9f7 3632 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
<> 144:ef7eb2e8f9f7 3633 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
<> 144:ef7eb2e8f9f7 3634 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
<> 144:ef7eb2e8f9f7 3635 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
mbed_official 74:9322579e4309 3636
mbed_official 74:9322579e4309 3637 /*!<Mode_ARGB4444 */
<> 144:ef7eb2e8f9f7 3638 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
<> 144:ef7eb2e8f9f7 3639 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
<> 144:ef7eb2e8f9f7 3640 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
<> 144:ef7eb2e8f9f7 3641 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
mbed_official 74:9322579e4309 3642
mbed_official 74:9322579e4309 3643 /******************** Bit definition for DMA2D_OMAR register ****************/
mbed_official 74:9322579e4309 3644
<> 144:ef7eb2e8f9f7 3645 #define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
mbed_official 74:9322579e4309 3646
mbed_official 74:9322579e4309 3647 /******************** Bit definition for DMA2D_OOR register *****************/
mbed_official 74:9322579e4309 3648
<> 144:ef7eb2e8f9f7 3649 #define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
mbed_official 74:9322579e4309 3650
mbed_official 74:9322579e4309 3651 /******************** Bit definition for DMA2D_NLR register *****************/
mbed_official 74:9322579e4309 3652
<> 144:ef7eb2e8f9f7 3653 #define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
<> 144:ef7eb2e8f9f7 3654 #define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
mbed_official 74:9322579e4309 3655
mbed_official 74:9322579e4309 3656 /******************** Bit definition for DMA2D_LWR register *****************/
mbed_official 74:9322579e4309 3657
<> 144:ef7eb2e8f9f7 3658 #define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
mbed_official 74:9322579e4309 3659
mbed_official 74:9322579e4309 3660 /******************** Bit definition for DMA2D_AMTCR register ***************/
mbed_official 74:9322579e4309 3661
<> 144:ef7eb2e8f9f7 3662 #define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
<> 144:ef7eb2e8f9f7 3663 #define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
mbed_official 74:9322579e4309 3664
mbed_official 74:9322579e4309 3665
mbed_official 74:9322579e4309 3666 /******************** Bit definition for DMA2D_FGCLUT register **************/
mbed_official 74:9322579e4309 3667
mbed_official 74:9322579e4309 3668 /******************** Bit definition for DMA2D_BGCLUT register **************/
mbed_official 74:9322579e4309 3669
mbed_official 74:9322579e4309 3670
mbed_official 74:9322579e4309 3671 /******************************************************************************/
mbed_official 74:9322579e4309 3672 /* */
mbed_official 74:9322579e4309 3673 /* External Interrupt/Event Controller */
mbed_official 74:9322579e4309 3674 /* */
mbed_official 74:9322579e4309 3675 /******************************************************************************/
mbed_official 74:9322579e4309 3676 /******************* Bit definition for EXTI_IMR register *******************/
<> 144:ef7eb2e8f9f7 3677 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 144:ef7eb2e8f9f7 3678 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 144:ef7eb2e8f9f7 3679 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 144:ef7eb2e8f9f7 3680 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 144:ef7eb2e8f9f7 3681 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 144:ef7eb2e8f9f7 3682 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 144:ef7eb2e8f9f7 3683 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 144:ef7eb2e8f9f7 3684 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 144:ef7eb2e8f9f7 3685 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 144:ef7eb2e8f9f7 3686 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 144:ef7eb2e8f9f7 3687 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 144:ef7eb2e8f9f7 3688 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 144:ef7eb2e8f9f7 3689 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 144:ef7eb2e8f9f7 3690 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 144:ef7eb2e8f9f7 3691 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 144:ef7eb2e8f9f7 3692 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 144:ef7eb2e8f9f7 3693 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 144:ef7eb2e8f9f7 3694 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 144:ef7eb2e8f9f7 3695 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 144:ef7eb2e8f9f7 3696 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 144:ef7eb2e8f9f7 3697 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 144:ef7eb2e8f9f7 3698 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 144:ef7eb2e8f9f7 3699 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 144:ef7eb2e8f9f7 3700 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
<> 144:ef7eb2e8f9f7 3701
<> 144:ef7eb2e8f9f7 3702 /* Reference Defines */
<> 144:ef7eb2e8f9f7 3703 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 144:ef7eb2e8f9f7 3704 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 144:ef7eb2e8f9f7 3705 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 144:ef7eb2e8f9f7 3706 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 144:ef7eb2e8f9f7 3707 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 144:ef7eb2e8f9f7 3708 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 144:ef7eb2e8f9f7 3709 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 144:ef7eb2e8f9f7 3710 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 144:ef7eb2e8f9f7 3711 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 144:ef7eb2e8f9f7 3712 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 144:ef7eb2e8f9f7 3713 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 144:ef7eb2e8f9f7 3714 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 144:ef7eb2e8f9f7 3715 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 144:ef7eb2e8f9f7 3716 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 144:ef7eb2e8f9f7 3717 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 144:ef7eb2e8f9f7 3718 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 144:ef7eb2e8f9f7 3719 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 144:ef7eb2e8f9f7 3720 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 144:ef7eb2e8f9f7 3721 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 144:ef7eb2e8f9f7 3722 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 144:ef7eb2e8f9f7 3723 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 144:ef7eb2e8f9f7 3724 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 144:ef7eb2e8f9f7 3725 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 144:ef7eb2e8f9f7 3726 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 144:ef7eb2e8f9f7 3727
<> 144:ef7eb2e8f9f7 3728 #define EXTI_IMR_IM 0x00FFFFFFU /*!< Interrupt Mask All */
mbed_official 74:9322579e4309 3729
mbed_official 74:9322579e4309 3730 /******************* Bit definition for EXTI_EMR register *******************/
<> 144:ef7eb2e8f9f7 3731 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 144:ef7eb2e8f9f7 3732 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 144:ef7eb2e8f9f7 3733 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 144:ef7eb2e8f9f7 3734 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 144:ef7eb2e8f9f7 3735 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 144:ef7eb2e8f9f7 3736 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 144:ef7eb2e8f9f7 3737 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 144:ef7eb2e8f9f7 3738 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 144:ef7eb2e8f9f7 3739 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 144:ef7eb2e8f9f7 3740 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 144:ef7eb2e8f9f7 3741 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 144:ef7eb2e8f9f7 3742 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 144:ef7eb2e8f9f7 3743 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 144:ef7eb2e8f9f7 3744 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 144:ef7eb2e8f9f7 3745 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 144:ef7eb2e8f9f7 3746 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 144:ef7eb2e8f9f7 3747 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 144:ef7eb2e8f9f7 3748 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 144:ef7eb2e8f9f7 3749 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 144:ef7eb2e8f9f7 3750 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 144:ef7eb2e8f9f7 3751 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 144:ef7eb2e8f9f7 3752 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 144:ef7eb2e8f9f7 3753 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 144:ef7eb2e8f9f7 3754 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
<> 144:ef7eb2e8f9f7 3755
<> 144:ef7eb2e8f9f7 3756 /* Reference Defines */
<> 144:ef7eb2e8f9f7 3757 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 144:ef7eb2e8f9f7 3758 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 144:ef7eb2e8f9f7 3759 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 144:ef7eb2e8f9f7 3760 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 144:ef7eb2e8f9f7 3761 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 144:ef7eb2e8f9f7 3762 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 144:ef7eb2e8f9f7 3763 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 144:ef7eb2e8f9f7 3764 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 144:ef7eb2e8f9f7 3765 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 144:ef7eb2e8f9f7 3766 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 144:ef7eb2e8f9f7 3767 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 144:ef7eb2e8f9f7 3768 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 144:ef7eb2e8f9f7 3769 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 144:ef7eb2e8f9f7 3770 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 144:ef7eb2e8f9f7 3771 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 144:ef7eb2e8f9f7 3772 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 144:ef7eb2e8f9f7 3773 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 144:ef7eb2e8f9f7 3774 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 144:ef7eb2e8f9f7 3775 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 144:ef7eb2e8f9f7 3776 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 144:ef7eb2e8f9f7 3777 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 144:ef7eb2e8f9f7 3778 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 144:ef7eb2e8f9f7 3779 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 144:ef7eb2e8f9f7 3780 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 144:ef7eb2e8f9f7 3781
mbed_official 74:9322579e4309 3782
mbed_official 74:9322579e4309 3783 /****************** Bit definition for EXTI_RTSR register *******************/
<> 144:ef7eb2e8f9f7 3784 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 3785 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 3786 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 3787 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 3788 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 3789 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 3790 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 3791 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 3792 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 3793 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 3794 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 3795 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 3796 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 3797 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 3798 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 3799 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 3800 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 3801 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 3802 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 3803 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 3804 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 3805 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 3806 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 3807 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
mbed_official 74:9322579e4309 3808
mbed_official 74:9322579e4309 3809 /****************** Bit definition for EXTI_FTSR register *******************/
<> 144:ef7eb2e8f9f7 3810 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 144:ef7eb2e8f9f7 3811 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 144:ef7eb2e8f9f7 3812 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 144:ef7eb2e8f9f7 3813 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 144:ef7eb2e8f9f7 3814 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 144:ef7eb2e8f9f7 3815 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 144:ef7eb2e8f9f7 3816 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 144:ef7eb2e8f9f7 3817 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 144:ef7eb2e8f9f7 3818 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 144:ef7eb2e8f9f7 3819 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 144:ef7eb2e8f9f7 3820 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 144:ef7eb2e8f9f7 3821 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 144:ef7eb2e8f9f7 3822 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 144:ef7eb2e8f9f7 3823 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 144:ef7eb2e8f9f7 3824 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 144:ef7eb2e8f9f7 3825 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 144:ef7eb2e8f9f7 3826 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 144:ef7eb2e8f9f7 3827 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 144:ef7eb2e8f9f7 3828 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 144:ef7eb2e8f9f7 3829 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 144:ef7eb2e8f9f7 3830 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 144:ef7eb2e8f9f7 3831 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 144:ef7eb2e8f9f7 3832 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 3833 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
mbed_official 74:9322579e4309 3834
mbed_official 74:9322579e4309 3835 /****************** Bit definition for EXTI_SWIER register ******************/
<> 144:ef7eb2e8f9f7 3836 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 144:ef7eb2e8f9f7 3837 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 144:ef7eb2e8f9f7 3838 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 144:ef7eb2e8f9f7 3839 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 144:ef7eb2e8f9f7 3840 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 144:ef7eb2e8f9f7 3841 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 144:ef7eb2e8f9f7 3842 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 144:ef7eb2e8f9f7 3843 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 144:ef7eb2e8f9f7 3844 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 144:ef7eb2e8f9f7 3845 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 144:ef7eb2e8f9f7 3846 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 144:ef7eb2e8f9f7 3847 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 144:ef7eb2e8f9f7 3848 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 144:ef7eb2e8f9f7 3849 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 144:ef7eb2e8f9f7 3850 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 144:ef7eb2e8f9f7 3851 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 144:ef7eb2e8f9f7 3852 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 144:ef7eb2e8f9f7 3853 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 144:ef7eb2e8f9f7 3854 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 144:ef7eb2e8f9f7 3855 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 144:ef7eb2e8f9f7 3856 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 144:ef7eb2e8f9f7 3857 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 144:ef7eb2e8f9f7 3858 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 3859 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
mbed_official 74:9322579e4309 3860
mbed_official 74:9322579e4309 3861 /******************* Bit definition for EXTI_PR register ********************/
<> 144:ef7eb2e8f9f7 3862 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 144:ef7eb2e8f9f7 3863 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 144:ef7eb2e8f9f7 3864 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 144:ef7eb2e8f9f7 3865 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 144:ef7eb2e8f9f7 3866 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 144:ef7eb2e8f9f7 3867 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 144:ef7eb2e8f9f7 3868 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 144:ef7eb2e8f9f7 3869 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 144:ef7eb2e8f9f7 3870 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 144:ef7eb2e8f9f7 3871 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 144:ef7eb2e8f9f7 3872 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 144:ef7eb2e8f9f7 3873 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 144:ef7eb2e8f9f7 3874 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 144:ef7eb2e8f9f7 3875 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 144:ef7eb2e8f9f7 3876 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 144:ef7eb2e8f9f7 3877 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 144:ef7eb2e8f9f7 3878 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 144:ef7eb2e8f9f7 3879 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 144:ef7eb2e8f9f7 3880 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 144:ef7eb2e8f9f7 3881 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 144:ef7eb2e8f9f7 3882 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 144:ef7eb2e8f9f7 3883 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 144:ef7eb2e8f9f7 3884 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 3885 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
mbed_official 74:9322579e4309 3886
mbed_official 74:9322579e4309 3887 /******************************************************************************/
mbed_official 74:9322579e4309 3888 /* */
mbed_official 74:9322579e4309 3889 /* FLASH */
mbed_official 74:9322579e4309 3890 /* */
mbed_official 74:9322579e4309 3891 /******************************************************************************/
<> 144:ef7eb2e8f9f7 3892 /*
<> 144:ef7eb2e8f9f7 3893 * @brief FLASH Total Sectors Number
<> 144:ef7eb2e8f9f7 3894 */
<> 144:ef7eb2e8f9f7 3895 #define FLASH_SECTOR_TOTAL 8
<> 144:ef7eb2e8f9f7 3896
mbed_official 74:9322579e4309 3897 /******************* Bits definition for FLASH_ACR register *****************/
<> 144:ef7eb2e8f9f7 3898 #define FLASH_ACR_LATENCY 0x0000000FU
<> 144:ef7eb2e8f9f7 3899 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 144:ef7eb2e8f9f7 3900 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 144:ef7eb2e8f9f7 3901 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 144:ef7eb2e8f9f7 3902 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 144:ef7eb2e8f9f7 3903 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 144:ef7eb2e8f9f7 3904 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 144:ef7eb2e8f9f7 3905 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 144:ef7eb2e8f9f7 3906 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 144:ef7eb2e8f9f7 3907 #define FLASH_ACR_LATENCY_8WS 0x00000008U
<> 144:ef7eb2e8f9f7 3908 #define FLASH_ACR_LATENCY_9WS 0x00000009U
<> 144:ef7eb2e8f9f7 3909 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
<> 144:ef7eb2e8f9f7 3910 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
<> 144:ef7eb2e8f9f7 3911 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
<> 144:ef7eb2e8f9f7 3912 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
<> 144:ef7eb2e8f9f7 3913 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
<> 144:ef7eb2e8f9f7 3914 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
<> 144:ef7eb2e8f9f7 3915 #define FLASH_ACR_PRFTEN 0x00000100U
<> 144:ef7eb2e8f9f7 3916 #define FLASH_ACR_ARTEN 0x00000200U
<> 144:ef7eb2e8f9f7 3917 #define FLASH_ACR_ARTRST 0x00000800U
mbed_official 74:9322579e4309 3918
mbed_official 74:9322579e4309 3919 /******************* Bits definition for FLASH_SR register ******************/
<> 144:ef7eb2e8f9f7 3920 #define FLASH_SR_EOP 0x00000001U
<> 144:ef7eb2e8f9f7 3921 #define FLASH_SR_OPERR 0x00000002U
<> 144:ef7eb2e8f9f7 3922 #define FLASH_SR_WRPERR 0x00000010U
<> 144:ef7eb2e8f9f7 3923 #define FLASH_SR_PGAERR 0x00000020U
<> 144:ef7eb2e8f9f7 3924 #define FLASH_SR_PGPERR 0x00000040U
<> 144:ef7eb2e8f9f7 3925 #define FLASH_SR_ERSERR 0x00000080U
<> 144:ef7eb2e8f9f7 3926 #define FLASH_SR_BSY 0x00010000U
mbed_official 74:9322579e4309 3927
mbed_official 74:9322579e4309 3928 /******************* Bits definition for FLASH_CR register ******************/
<> 144:ef7eb2e8f9f7 3929 #define FLASH_CR_PG 0x00000001U
<> 144:ef7eb2e8f9f7 3930 #define FLASH_CR_SER 0x00000002U
<> 144:ef7eb2e8f9f7 3931 #define FLASH_CR_MER 0x00000004U
<> 144:ef7eb2e8f9f7 3932 #define FLASH_CR_SNB 0x00000078U
<> 144:ef7eb2e8f9f7 3933 #define FLASH_CR_SNB_0 0x00000008U
<> 144:ef7eb2e8f9f7 3934 #define FLASH_CR_SNB_1 0x00000010U
<> 144:ef7eb2e8f9f7 3935 #define FLASH_CR_SNB_2 0x00000020U
<> 144:ef7eb2e8f9f7 3936 #define FLASH_CR_SNB_3 0x00000040U
<> 144:ef7eb2e8f9f7 3937 #define FLASH_CR_PSIZE 0x00000300U
<> 144:ef7eb2e8f9f7 3938 #define FLASH_CR_PSIZE_0 0x00000100U
<> 144:ef7eb2e8f9f7 3939 #define FLASH_CR_PSIZE_1 0x00000200U
<> 144:ef7eb2e8f9f7 3940 #define FLASH_CR_STRT 0x00010000U
<> 144:ef7eb2e8f9f7 3941 #define FLASH_CR_EOPIE 0x01000000U
<> 144:ef7eb2e8f9f7 3942 #define FLASH_CR_ERRIE 0x02000000U
<> 144:ef7eb2e8f9f7 3943 #define FLASH_CR_LOCK 0x80000000U
mbed_official 74:9322579e4309 3944
mbed_official 74:9322579e4309 3945 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 144:ef7eb2e8f9f7 3946 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 144:ef7eb2e8f9f7 3947 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 144:ef7eb2e8f9f7 3948 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 144:ef7eb2e8f9f7 3949 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 144:ef7eb2e8f9f7 3950 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 144:ef7eb2e8f9f7 3951 #define FLASH_OPTCR_WWDG_SW 0x00000010U
<> 144:ef7eb2e8f9f7 3952 #define FLASH_OPTCR_IWDG_SW 0x00000020U
<> 144:ef7eb2e8f9f7 3953 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 3954 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 144:ef7eb2e8f9f7 3955 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 144:ef7eb2e8f9f7 3956 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 144:ef7eb2e8f9f7 3957 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 144:ef7eb2e8f9f7 3958 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 144:ef7eb2e8f9f7 3959 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 144:ef7eb2e8f9f7 3960 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 144:ef7eb2e8f9f7 3961 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 144:ef7eb2e8f9f7 3962 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 144:ef7eb2e8f9f7 3963 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 144:ef7eb2e8f9f7 3964 #define FLASH_OPTCR_nWRP 0x00FF0000U
<> 144:ef7eb2e8f9f7 3965 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 144:ef7eb2e8f9f7 3966 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 144:ef7eb2e8f9f7 3967 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 144:ef7eb2e8f9f7 3968 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 144:ef7eb2e8f9f7 3969 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 144:ef7eb2e8f9f7 3970 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 144:ef7eb2e8f9f7 3971 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 144:ef7eb2e8f9f7 3972 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 144:ef7eb2e8f9f7 3973 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
<> 144:ef7eb2e8f9f7 3974 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
mbed_official 74:9322579e4309 3975
mbed_official 74:9322579e4309 3976 /******************* Bits definition for FLASH_OPTCR1 register ***************/
<> 144:ef7eb2e8f9f7 3977 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
<> 144:ef7eb2e8f9f7 3978 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
mbed_official 74:9322579e4309 3979
mbed_official 74:9322579e4309 3980 /******************************************************************************/
mbed_official 74:9322579e4309 3981 /* */
mbed_official 74:9322579e4309 3982 /* Flexible Memory Controller */
mbed_official 74:9322579e4309 3983 /* */
mbed_official 74:9322579e4309 3984 /******************************************************************************/
mbed_official 74:9322579e4309 3985 /****************** Bit definition for FMC_BCR1 register *******************/
<> 144:ef7eb2e8f9f7 3986 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 3987 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 3988 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 3989 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3990 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3991 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 3992 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 3993 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 3994 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 3995 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 3996 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 3997 #define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 3998 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 3999 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 4000 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 4001 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 4002 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 4003 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
<> 144:ef7eb2e8f9f7 4004 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4005 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4006 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4007 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 4008 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
<> 144:ef7eb2e8f9f7 4009 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
mbed_official 74:9322579e4309 4010
mbed_official 74:9322579e4309 4011 /****************** Bit definition for FMC_BCR2 register *******************/
<> 144:ef7eb2e8f9f7 4012 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 4013 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 4014 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 4015 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4016 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4017 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 4018 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4019 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4020 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 4021 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 4022 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 4023 #define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 4024 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 4025 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 4026 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 4027 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 4028 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 4029 #define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
<> 144:ef7eb2e8f9f7 4030 #define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4031 #define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4032 #define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4033 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
mbed_official 74:9322579e4309 4034
mbed_official 74:9322579e4309 4035 /****************** Bit definition for FMC_BCR3 register *******************/
<> 144:ef7eb2e8f9f7 4036 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 4037 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 4038 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 4039 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4040 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4041 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 4042 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4043 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4044 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 4045 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 4046 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 4047 #define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 4048 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 4049 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 4050 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 4051 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 4052 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 4053 #define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
<> 144:ef7eb2e8f9f7 4054 #define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4055 #define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4056 #define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4057 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
mbed_official 74:9322579e4309 4058
mbed_official 74:9322579e4309 4059 /****************** Bit definition for FMC_BCR4 register *******************/
<> 144:ef7eb2e8f9f7 4060 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 144:ef7eb2e8f9f7 4061 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 144:ef7eb2e8f9f7 4062 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 144:ef7eb2e8f9f7 4063 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4064 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4065 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 144:ef7eb2e8f9f7 4066 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4067 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4068 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
<> 144:ef7eb2e8f9f7 4069 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 144:ef7eb2e8f9f7 4070 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 144:ef7eb2e8f9f7 4071 #define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 144:ef7eb2e8f9f7 4072 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 144:ef7eb2e8f9f7 4073 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
<> 144:ef7eb2e8f9f7 4074 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
<> 144:ef7eb2e8f9f7 4075 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 144:ef7eb2e8f9f7 4076 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 144:ef7eb2e8f9f7 4077 #define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
<> 144:ef7eb2e8f9f7 4078 #define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4079 #define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4080 #define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4081 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
mbed_official 74:9322579e4309 4082
mbed_official 74:9322579e4309 4083 /****************** Bit definition for FMC_BTR1 register ******************/
<> 144:ef7eb2e8f9f7 4084 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4085 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4086 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4087 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4088 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4089 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4090 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4091 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4092 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4093 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4094 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4095 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4096 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4097 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4098 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4099 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4100 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4101 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4102 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4103 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4104 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4105 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4106 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4107 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4108 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 4109 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4110 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4111 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4112 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4113 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 4114 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4115 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4116 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4117 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4118 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4119 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4120 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4121
mbed_official 74:9322579e4309 4122 /****************** Bit definition for FMC_BTR2 register *******************/
<> 144:ef7eb2e8f9f7 4123 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4124 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4125 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4126 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4127 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4128 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4129 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4130 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4131 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4132 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4133 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4134 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4135 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4136 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4137 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4138 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4139 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4140 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4141 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4142 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4143 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4144 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4145 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4146 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4147 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 4148 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4149 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4150 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4151 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4152 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 4153 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4154 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4155 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4156 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4157 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4158 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4159 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4160
mbed_official 74:9322579e4309 4161 /******************* Bit definition for FMC_BTR3 register *******************/
<> 144:ef7eb2e8f9f7 4162 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4163 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4164 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4165 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4166 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4167 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4168 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4169 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4170 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4171 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4172 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4173 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4174 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4175 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4176 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4177 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4178 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4179 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4180 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4181 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4182 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4183 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4184 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4185 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4186 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 4187 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4188 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4189 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4190 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4191 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 4192 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4193 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4194 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4195 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4196 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4197 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4198 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4199
mbed_official 74:9322579e4309 4200 /****************** Bit definition for FMC_BTR4 register *******************/
<> 144:ef7eb2e8f9f7 4201 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4202 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4203 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4204 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4205 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4206 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4207 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4208 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4209 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4210 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4211 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4212 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4213 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4214 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4215 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4216 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4217 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4218 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4219 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4220 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4221 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4222 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4223 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4224 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4225 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 144:ef7eb2e8f9f7 4226 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4227 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4228 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4229 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4230 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 144:ef7eb2e8f9f7 4231 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4232 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4233 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4234 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4235 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4236 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4237 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4238
mbed_official 74:9322579e4309 4239 /****************** Bit definition for FMC_BWTR1 register ******************/
<> 144:ef7eb2e8f9f7 4240 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4241 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4242 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4243 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4244 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4245 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4246 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4247 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4248 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4249 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4250 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4251 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4252 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4253 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4254 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4255 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4256 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4257 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4258 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4259 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4260 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4261 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4262 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4263 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4264 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4265 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4266 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4267
mbed_official 74:9322579e4309 4268 /****************** Bit definition for FMC_BWTR2 register ******************/
<> 144:ef7eb2e8f9f7 4269 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4270 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4271 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4272 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4273 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4274 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4275 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4276 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4277 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4278 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4279 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4280 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4281 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4282 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4283 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4284 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4285 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4286 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4287 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4288 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4289 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4290 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4291 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4292 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4293 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4294 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4295 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4296
mbed_official 74:9322579e4309 4297 /****************** Bit definition for FMC_BWTR3 register ******************/
<> 144:ef7eb2e8f9f7 4298 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4299 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4300 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4301 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4302 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4303 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4304 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4305 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4306 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4307 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4308 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4309 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4310 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4311 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4312 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4313 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4314 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4315 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4316 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4317 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4318 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4319 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4320 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4321 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4322 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4323 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4324 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4325
mbed_official 74:9322579e4309 4326 /****************** Bit definition for FMC_BWTR4 register ******************/
<> 144:ef7eb2e8f9f7 4327 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 144:ef7eb2e8f9f7 4328 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4329 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4330 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4331 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4332 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 144:ef7eb2e8f9f7 4333 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4334 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4335 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4336 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4337 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 144:ef7eb2e8f9f7 4338 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4339 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4340 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4341 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4342 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4343 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4344 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4345 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4346 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 144:ef7eb2e8f9f7 4347 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4348 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4349 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4350 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4351 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 144:ef7eb2e8f9f7 4352 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4353 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4354
mbed_official 74:9322579e4309 4355 /****************** Bit definition for FMC_PCR register *******************/
<> 144:ef7eb2e8f9f7 4356 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
<> 144:ef7eb2e8f9f7 4357 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
<> 144:ef7eb2e8f9f7 4358 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
<> 144:ef7eb2e8f9f7 4359 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 144:ef7eb2e8f9f7 4360 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4361 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4362 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
<> 144:ef7eb2e8f9f7 4363 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 144:ef7eb2e8f9f7 4364 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4365 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4366 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4367 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4368 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
<> 144:ef7eb2e8f9f7 4369 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4370 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4371 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4372 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4373 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
<> 144:ef7eb2e8f9f7 4374 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4375 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4376 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
mbed_official 74:9322579e4309 4377
mbed_official 74:9322579e4309 4378 /******************* Bit definition for FMC_SR register *******************/
<> 144:ef7eb2e8f9f7 4379 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
<> 144:ef7eb2e8f9f7 4380 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
<> 144:ef7eb2e8f9f7 4381 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
<> 144:ef7eb2e8f9f7 4382 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 4383 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
<> 144:ef7eb2e8f9f7 4384 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
<> 144:ef7eb2e8f9f7 4385 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
mbed_official 74:9322579e4309 4386
mbed_official 74:9322579e4309 4387 /****************** Bit definition for FMC_PMEM register ******************/
<> 144:ef7eb2e8f9f7 4388 #define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
<> 144:ef7eb2e8f9f7 4389 #define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4390 #define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4391 #define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4392 #define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4393 #define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4394 #define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4395 #define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4396 #define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4397 #define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
<> 144:ef7eb2e8f9f7 4398 #define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4399 #define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4400 #define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4401 #define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4402 #define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4403 #define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4404 #define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4405 #define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4406 #define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
<> 144:ef7eb2e8f9f7 4407 #define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4408 #define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4409 #define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4410 #define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4411 #define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4412 #define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4413 #define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4414 #define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4415 #define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4416 #define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4417 #define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4418 #define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4419 #define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4420 #define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4421 #define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4422 #define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4423 #define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
mbed_official 74:9322579e4309 4424
mbed_official 74:9322579e4309 4425 /****************** Bit definition for FMC_PATT register ******************/
<> 144:ef7eb2e8f9f7 4426 #define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
<> 144:ef7eb2e8f9f7 4427 #define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4428 #define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4429 #define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4430 #define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4431 #define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4432 #define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4433 #define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4434 #define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4435 #define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
<> 144:ef7eb2e8f9f7 4436 #define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4437 #define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4438 #define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4439 #define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4440 #define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4441 #define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4442 #define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4443 #define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4444 #define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
<> 144:ef7eb2e8f9f7 4445 #define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4446 #define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4447 #define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4448 #define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4449 #define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4450 #define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4451 #define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4452 #define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 4453 #define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
<> 144:ef7eb2e8f9f7 4454 #define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4455 #define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4456 #define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4457 #define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4458 #define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 4459 #define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 4460 #define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 4461 #define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
mbed_official 74:9322579e4309 4462
mbed_official 74:9322579e4309 4463 /****************** Bit definition for FMC_ECCR register ******************/
<> 144:ef7eb2e8f9f7 4464 #define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */
mbed_official 74:9322579e4309 4465
mbed_official 74:9322579e4309 4466 /****************** Bit definition for FMC_SDCR1 register ******************/
<> 144:ef7eb2e8f9f7 4467 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
<> 144:ef7eb2e8f9f7 4468 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4469 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4470 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
<> 144:ef7eb2e8f9f7 4471 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4472 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4473 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
<> 144:ef7eb2e8f9f7 4474 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4475 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4476 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
<> 144:ef7eb2e8f9f7 4477 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
<> 144:ef7eb2e8f9f7 4478 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4479 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4480 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
<> 144:ef7eb2e8f9f7 4481 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
<> 144:ef7eb2e8f9f7 4482 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4483 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4484 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
<> 144:ef7eb2e8f9f7 4485 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
<> 144:ef7eb2e8f9f7 4486 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4487 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4488
mbed_official 74:9322579e4309 4489 /****************** Bit definition for FMC_SDCR2 register ******************/
<> 144:ef7eb2e8f9f7 4490 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
<> 144:ef7eb2e8f9f7 4491 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4492 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4493 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
<> 144:ef7eb2e8f9f7 4494 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4495 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4496 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
<> 144:ef7eb2e8f9f7 4497 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4498 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4499 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
<> 144:ef7eb2e8f9f7 4500 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
<> 144:ef7eb2e8f9f7 4501 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4502 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4503 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
<> 144:ef7eb2e8f9f7 4504 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
<> 144:ef7eb2e8f9f7 4505 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4506 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4507 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
<> 144:ef7eb2e8f9f7 4508 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
<> 144:ef7eb2e8f9f7 4509 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4510 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
mbed_official 74:9322579e4309 4511
mbed_official 74:9322579e4309 4512 /****************** Bit definition for FMC_SDTR1 register ******************/
<> 144:ef7eb2e8f9f7 4513 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
<> 144:ef7eb2e8f9f7 4514 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4515 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4516 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4517 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4518 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
<> 144:ef7eb2e8f9f7 4519 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4520 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4521 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4522 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4523 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
<> 144:ef7eb2e8f9f7 4524 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4525 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4526 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4527 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4528 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
<> 144:ef7eb2e8f9f7 4529 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4530 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4531 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4532 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
<> 144:ef7eb2e8f9f7 4533 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4534 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4535 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4536 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
<> 144:ef7eb2e8f9f7 4537 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4538 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4539 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4540 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
<> 144:ef7eb2e8f9f7 4541 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4542 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4543 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
mbed_official 74:9322579e4309 4544
mbed_official 74:9322579e4309 4545 /****************** Bit definition for FMC_SDTR2 register ******************/
<> 144:ef7eb2e8f9f7 4546 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
<> 144:ef7eb2e8f9f7 4547 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4548 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4549 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4550 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4551 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
<> 144:ef7eb2e8f9f7 4552 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4553 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4554 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4555 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4556 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
<> 144:ef7eb2e8f9f7 4557 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4558 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4559 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4560 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4561 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
<> 144:ef7eb2e8f9f7 4562 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4563 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4564 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4565 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
<> 144:ef7eb2e8f9f7 4566 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4567 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4568 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4569 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
<> 144:ef7eb2e8f9f7 4570 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4571 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4572 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4573 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
<> 144:ef7eb2e8f9f7 4574 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4575 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4576 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
mbed_official 74:9322579e4309 4577
mbed_official 74:9322579e4309 4578 /****************** Bit definition for FMC_SDCMR register ******************/
<> 144:ef7eb2e8f9f7 4579 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
<> 144:ef7eb2e8f9f7 4580 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4581 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4582 #define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4583 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
<> 144:ef7eb2e8f9f7 4584 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
<> 144:ef7eb2e8f9f7 4585 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
<> 144:ef7eb2e8f9f7 4586 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4587 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4588 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 4589 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 4590 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
mbed_official 74:9322579e4309 4591
mbed_official 74:9322579e4309 4592 /****************** Bit definition for FMC_SDRTR register ******************/
<> 144:ef7eb2e8f9f7 4593 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
<> 144:ef7eb2e8f9f7 4594 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
<> 144:ef7eb2e8f9f7 4595 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
mbed_official 74:9322579e4309 4596
mbed_official 74:9322579e4309 4597 /****************** Bit definition for FMC_SDSR register ******************/
<> 144:ef7eb2e8f9f7 4598 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
<> 144:ef7eb2e8f9f7 4599 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
<> 144:ef7eb2e8f9f7 4600 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4601 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4602 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
<> 144:ef7eb2e8f9f7 4603 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4604 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4605 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
mbed_official 74:9322579e4309 4606
mbed_official 74:9322579e4309 4607 /******************************************************************************/
mbed_official 74:9322579e4309 4608 /* */
mbed_official 74:9322579e4309 4609 /* General Purpose I/O */
mbed_official 74:9322579e4309 4610 /* */
mbed_official 74:9322579e4309 4611 /******************************************************************************/
mbed_official 74:9322579e4309 4612 /****************** Bits definition for GPIO_MODER register *****************/
<> 144:ef7eb2e8f9f7 4613 #define GPIO_MODER_MODER0 0x00000003U
<> 144:ef7eb2e8f9f7 4614 #define GPIO_MODER_MODER0_0 0x00000001U
<> 144:ef7eb2e8f9f7 4615 #define GPIO_MODER_MODER0_1 0x00000002U
<> 144:ef7eb2e8f9f7 4616 #define GPIO_MODER_MODER1 0x0000000CU
<> 144:ef7eb2e8f9f7 4617 #define GPIO_MODER_MODER1_0 0x00000004U
<> 144:ef7eb2e8f9f7 4618 #define GPIO_MODER_MODER1_1 0x00000008U
<> 144:ef7eb2e8f9f7 4619 #define GPIO_MODER_MODER2 0x00000030U
<> 144:ef7eb2e8f9f7 4620 #define GPIO_MODER_MODER2_0 0x00000010U
<> 144:ef7eb2e8f9f7 4621 #define GPIO_MODER_MODER2_1 0x00000020U
<> 144:ef7eb2e8f9f7 4622 #define GPIO_MODER_MODER3 0x000000C0U
<> 144:ef7eb2e8f9f7 4623 #define GPIO_MODER_MODER3_0 0x00000040U
<> 144:ef7eb2e8f9f7 4624 #define GPIO_MODER_MODER3_1 0x00000080U
<> 144:ef7eb2e8f9f7 4625 #define GPIO_MODER_MODER4 0x00000300U
<> 144:ef7eb2e8f9f7 4626 #define GPIO_MODER_MODER4_0 0x00000100U
<> 144:ef7eb2e8f9f7 4627 #define GPIO_MODER_MODER4_1 0x00000200U
<> 144:ef7eb2e8f9f7 4628 #define GPIO_MODER_MODER5 0x00000C00U
<> 144:ef7eb2e8f9f7 4629 #define GPIO_MODER_MODER5_0 0x00000400U
<> 144:ef7eb2e8f9f7 4630 #define GPIO_MODER_MODER5_1 0x00000800U
<> 144:ef7eb2e8f9f7 4631 #define GPIO_MODER_MODER6 0x00003000U
<> 144:ef7eb2e8f9f7 4632 #define GPIO_MODER_MODER6_0 0x00001000U
<> 144:ef7eb2e8f9f7 4633 #define GPIO_MODER_MODER6_1 0x00002000U
<> 144:ef7eb2e8f9f7 4634 #define GPIO_MODER_MODER7 0x0000C000U
<> 144:ef7eb2e8f9f7 4635 #define GPIO_MODER_MODER7_0 0x00004000U
<> 144:ef7eb2e8f9f7 4636 #define GPIO_MODER_MODER7_1 0x00008000U
<> 144:ef7eb2e8f9f7 4637 #define GPIO_MODER_MODER8 0x00030000U
<> 144:ef7eb2e8f9f7 4638 #define GPIO_MODER_MODER8_0 0x00010000U
<> 144:ef7eb2e8f9f7 4639 #define GPIO_MODER_MODER8_1 0x00020000U
<> 144:ef7eb2e8f9f7 4640 #define GPIO_MODER_MODER9 0x000C0000U
<> 144:ef7eb2e8f9f7 4641 #define GPIO_MODER_MODER9_0 0x00040000U
<> 144:ef7eb2e8f9f7 4642 #define GPIO_MODER_MODER9_1 0x00080000U
<> 144:ef7eb2e8f9f7 4643 #define GPIO_MODER_MODER10 0x00300000U
<> 144:ef7eb2e8f9f7 4644 #define GPIO_MODER_MODER10_0 0x00100000U
<> 144:ef7eb2e8f9f7 4645 #define GPIO_MODER_MODER10_1 0x00200000U
<> 144:ef7eb2e8f9f7 4646 #define GPIO_MODER_MODER11 0x00C00000U
<> 144:ef7eb2e8f9f7 4647 #define GPIO_MODER_MODER11_0 0x00400000U
<> 144:ef7eb2e8f9f7 4648 #define GPIO_MODER_MODER11_1 0x00800000U
<> 144:ef7eb2e8f9f7 4649 #define GPIO_MODER_MODER12 0x03000000U
<> 144:ef7eb2e8f9f7 4650 #define GPIO_MODER_MODER12_0 0x01000000U
<> 144:ef7eb2e8f9f7 4651 #define GPIO_MODER_MODER12_1 0x02000000U
<> 144:ef7eb2e8f9f7 4652 #define GPIO_MODER_MODER13 0x0C000000U
<> 144:ef7eb2e8f9f7 4653 #define GPIO_MODER_MODER13_0 0x04000000U
<> 144:ef7eb2e8f9f7 4654 #define GPIO_MODER_MODER13_1 0x08000000U
<> 144:ef7eb2e8f9f7 4655 #define GPIO_MODER_MODER14 0x30000000U
<> 144:ef7eb2e8f9f7 4656 #define GPIO_MODER_MODER14_0 0x10000000U
<> 144:ef7eb2e8f9f7 4657 #define GPIO_MODER_MODER14_1 0x20000000U
<> 144:ef7eb2e8f9f7 4658 #define GPIO_MODER_MODER15 0xC0000000U
<> 144:ef7eb2e8f9f7 4659 #define GPIO_MODER_MODER15_0 0x40000000U
<> 144:ef7eb2e8f9f7 4660 #define GPIO_MODER_MODER15_1 0x80000000U
mbed_official 74:9322579e4309 4661
mbed_official 74:9322579e4309 4662 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 144:ef7eb2e8f9f7 4663 #define GPIO_OTYPER_OT_0 0x00000001U
<> 144:ef7eb2e8f9f7 4664 #define GPIO_OTYPER_OT_1 0x00000002U
<> 144:ef7eb2e8f9f7 4665 #define GPIO_OTYPER_OT_2 0x00000004U
<> 144:ef7eb2e8f9f7 4666 #define GPIO_OTYPER_OT_3 0x00000008U
<> 144:ef7eb2e8f9f7 4667 #define GPIO_OTYPER_OT_4 0x00000010U
<> 144:ef7eb2e8f9f7 4668 #define GPIO_OTYPER_OT_5 0x00000020U
<> 144:ef7eb2e8f9f7 4669 #define GPIO_OTYPER_OT_6 0x00000040U
<> 144:ef7eb2e8f9f7 4670 #define GPIO_OTYPER_OT_7 0x00000080U
<> 144:ef7eb2e8f9f7 4671 #define GPIO_OTYPER_OT_8 0x00000100U
<> 144:ef7eb2e8f9f7 4672 #define GPIO_OTYPER_OT_9 0x00000200U
<> 144:ef7eb2e8f9f7 4673 #define GPIO_OTYPER_OT_10 0x00000400U
<> 144:ef7eb2e8f9f7 4674 #define GPIO_OTYPER_OT_11 0x00000800U
<> 144:ef7eb2e8f9f7 4675 #define GPIO_OTYPER_OT_12 0x00001000U
<> 144:ef7eb2e8f9f7 4676 #define GPIO_OTYPER_OT_13 0x00002000U
<> 144:ef7eb2e8f9f7 4677 #define GPIO_OTYPER_OT_14 0x00004000U
<> 144:ef7eb2e8f9f7 4678 #define GPIO_OTYPER_OT_15 0x00008000U
mbed_official 74:9322579e4309 4679
mbed_official 74:9322579e4309 4680 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 144:ef7eb2e8f9f7 4681 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
<> 144:ef7eb2e8f9f7 4682 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 4683 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 4684 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 4685 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 4686 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 4687 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
<> 144:ef7eb2e8f9f7 4688 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 4689 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 4690 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 4691 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 4692 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 4693 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
<> 144:ef7eb2e8f9f7 4694 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 4695 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 4696 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 4697 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 4698 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 4699 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
<> 144:ef7eb2e8f9f7 4700 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 4701 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 4702 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 4703 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 4704 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 4705 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
<> 144:ef7eb2e8f9f7 4706 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 4707 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 4708 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 4709 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 4710 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 4711 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
<> 144:ef7eb2e8f9f7 4712 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 4713 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 4714 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 4715 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 4716 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 4717 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
<> 144:ef7eb2e8f9f7 4718 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 4719 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 4720 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 4721 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 4722 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 4723 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
<> 144:ef7eb2e8f9f7 4724 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 4725 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 4726 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 4727 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 4728 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
mbed_official 74:9322579e4309 4729
mbed_official 74:9322579e4309 4730 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 144:ef7eb2e8f9f7 4731 #define GPIO_PUPDR_PUPDR0 0x00000003U
<> 144:ef7eb2e8f9f7 4732 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
<> 144:ef7eb2e8f9f7 4733 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
<> 144:ef7eb2e8f9f7 4734 #define GPIO_PUPDR_PUPDR1 0x0000000CU
<> 144:ef7eb2e8f9f7 4735 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
<> 144:ef7eb2e8f9f7 4736 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
<> 144:ef7eb2e8f9f7 4737 #define GPIO_PUPDR_PUPDR2 0x00000030U
<> 144:ef7eb2e8f9f7 4738 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
<> 144:ef7eb2e8f9f7 4739 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
<> 144:ef7eb2e8f9f7 4740 #define GPIO_PUPDR_PUPDR3 0x000000C0U
<> 144:ef7eb2e8f9f7 4741 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
<> 144:ef7eb2e8f9f7 4742 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
<> 144:ef7eb2e8f9f7 4743 #define GPIO_PUPDR_PUPDR4 0x00000300U
<> 144:ef7eb2e8f9f7 4744 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
<> 144:ef7eb2e8f9f7 4745 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
<> 144:ef7eb2e8f9f7 4746 #define GPIO_PUPDR_PUPDR5 0x00000C00U
<> 144:ef7eb2e8f9f7 4747 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
<> 144:ef7eb2e8f9f7 4748 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
<> 144:ef7eb2e8f9f7 4749 #define GPIO_PUPDR_PUPDR6 0x00003000U
<> 144:ef7eb2e8f9f7 4750 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
<> 144:ef7eb2e8f9f7 4751 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
<> 144:ef7eb2e8f9f7 4752 #define GPIO_PUPDR_PUPDR7 0x0000C000U
<> 144:ef7eb2e8f9f7 4753 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
<> 144:ef7eb2e8f9f7 4754 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
<> 144:ef7eb2e8f9f7 4755 #define GPIO_PUPDR_PUPDR8 0x00030000U
<> 144:ef7eb2e8f9f7 4756 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
<> 144:ef7eb2e8f9f7 4757 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
<> 144:ef7eb2e8f9f7 4758 #define GPIO_PUPDR_PUPDR9 0x000C0000U
<> 144:ef7eb2e8f9f7 4759 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
<> 144:ef7eb2e8f9f7 4760 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
<> 144:ef7eb2e8f9f7 4761 #define GPIO_PUPDR_PUPDR10 0x00300000U
<> 144:ef7eb2e8f9f7 4762 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
<> 144:ef7eb2e8f9f7 4763 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
<> 144:ef7eb2e8f9f7 4764 #define GPIO_PUPDR_PUPDR11 0x00C00000U
<> 144:ef7eb2e8f9f7 4765 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
<> 144:ef7eb2e8f9f7 4766 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
<> 144:ef7eb2e8f9f7 4767 #define GPIO_PUPDR_PUPDR12 0x03000000U
<> 144:ef7eb2e8f9f7 4768 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
<> 144:ef7eb2e8f9f7 4769 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
<> 144:ef7eb2e8f9f7 4770 #define GPIO_PUPDR_PUPDR13 0x0C000000U
<> 144:ef7eb2e8f9f7 4771 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
<> 144:ef7eb2e8f9f7 4772 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
<> 144:ef7eb2e8f9f7 4773 #define GPIO_PUPDR_PUPDR14 0x30000000U
<> 144:ef7eb2e8f9f7 4774 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
<> 144:ef7eb2e8f9f7 4775 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
<> 144:ef7eb2e8f9f7 4776 #define GPIO_PUPDR_PUPDR15 0xC0000000U
<> 144:ef7eb2e8f9f7 4777 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
<> 144:ef7eb2e8f9f7 4778 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
mbed_official 74:9322579e4309 4779
mbed_official 74:9322579e4309 4780 /****************** Bits definition for GPIO_IDR register *******************/
<> 144:ef7eb2e8f9f7 4781 #define GPIO_IDR_IDR_0 0x00000001U
<> 144:ef7eb2e8f9f7 4782 #define GPIO_IDR_IDR_1 0x00000002U
<> 144:ef7eb2e8f9f7 4783 #define GPIO_IDR_IDR_2 0x00000004U
<> 144:ef7eb2e8f9f7 4784 #define GPIO_IDR_IDR_3 0x00000008U
<> 144:ef7eb2e8f9f7 4785 #define GPIO_IDR_IDR_4 0x00000010U
<> 144:ef7eb2e8f9f7 4786 #define GPIO_IDR_IDR_5 0x00000020U
<> 144:ef7eb2e8f9f7 4787 #define GPIO_IDR_IDR_6 0x00000040U
<> 144:ef7eb2e8f9f7 4788 #define GPIO_IDR_IDR_7 0x00000080U
<> 144:ef7eb2e8f9f7 4789 #define GPIO_IDR_IDR_8 0x00000100U
<> 144:ef7eb2e8f9f7 4790 #define GPIO_IDR_IDR_9 0x00000200U
<> 144:ef7eb2e8f9f7 4791 #define GPIO_IDR_IDR_10 0x00000400U
<> 144:ef7eb2e8f9f7 4792 #define GPIO_IDR_IDR_11 0x00000800U
<> 144:ef7eb2e8f9f7 4793 #define GPIO_IDR_IDR_12 0x00001000U
<> 144:ef7eb2e8f9f7 4794 #define GPIO_IDR_IDR_13 0x00002000U
<> 144:ef7eb2e8f9f7 4795 #define GPIO_IDR_IDR_14 0x00004000U
<> 144:ef7eb2e8f9f7 4796 #define GPIO_IDR_IDR_15 0x00008000U
mbed_official 74:9322579e4309 4797
mbed_official 74:9322579e4309 4798 /****************** Bits definition for GPIO_ODR register *******************/
<> 144:ef7eb2e8f9f7 4799 #define GPIO_ODR_ODR_0 0x00000001U
<> 144:ef7eb2e8f9f7 4800 #define GPIO_ODR_ODR_1 0x00000002U
<> 144:ef7eb2e8f9f7 4801 #define GPIO_ODR_ODR_2 0x00000004U
<> 144:ef7eb2e8f9f7 4802 #define GPIO_ODR_ODR_3 0x00000008U
<> 144:ef7eb2e8f9f7 4803 #define GPIO_ODR_ODR_4 0x00000010U
<> 144:ef7eb2e8f9f7 4804 #define GPIO_ODR_ODR_5 0x00000020U
<> 144:ef7eb2e8f9f7 4805 #define GPIO_ODR_ODR_6 0x00000040U
<> 144:ef7eb2e8f9f7 4806 #define GPIO_ODR_ODR_7 0x00000080U
<> 144:ef7eb2e8f9f7 4807 #define GPIO_ODR_ODR_8 0x00000100U
<> 144:ef7eb2e8f9f7 4808 #define GPIO_ODR_ODR_9 0x00000200U
<> 144:ef7eb2e8f9f7 4809 #define GPIO_ODR_ODR_10 0x00000400U
<> 144:ef7eb2e8f9f7 4810 #define GPIO_ODR_ODR_11 0x00000800U
<> 144:ef7eb2e8f9f7 4811 #define GPIO_ODR_ODR_12 0x00001000U
<> 144:ef7eb2e8f9f7 4812 #define GPIO_ODR_ODR_13 0x00002000U
<> 144:ef7eb2e8f9f7 4813 #define GPIO_ODR_ODR_14 0x00004000U
<> 144:ef7eb2e8f9f7 4814 #define GPIO_ODR_ODR_15 0x00008000U
mbed_official 74:9322579e4309 4815
mbed_official 74:9322579e4309 4816 /****************** Bits definition for GPIO_BSRR register ******************/
<> 144:ef7eb2e8f9f7 4817 #define GPIO_BSRR_BS_0 0x00000001U
<> 144:ef7eb2e8f9f7 4818 #define GPIO_BSRR_BS_1 0x00000002U
<> 144:ef7eb2e8f9f7 4819 #define GPIO_BSRR_BS_2 0x00000004U
<> 144:ef7eb2e8f9f7 4820 #define GPIO_BSRR_BS_3 0x00000008U
<> 144:ef7eb2e8f9f7 4821 #define GPIO_BSRR_BS_4 0x00000010U
<> 144:ef7eb2e8f9f7 4822 #define GPIO_BSRR_BS_5 0x00000020U
<> 144:ef7eb2e8f9f7 4823 #define GPIO_BSRR_BS_6 0x00000040U
<> 144:ef7eb2e8f9f7 4824 #define GPIO_BSRR_BS_7 0x00000080U
<> 144:ef7eb2e8f9f7 4825 #define GPIO_BSRR_BS_8 0x00000100U
<> 144:ef7eb2e8f9f7 4826 #define GPIO_BSRR_BS_9 0x00000200U
<> 144:ef7eb2e8f9f7 4827 #define GPIO_BSRR_BS_10 0x00000400U
<> 144:ef7eb2e8f9f7 4828 #define GPIO_BSRR_BS_11 0x00000800U
<> 144:ef7eb2e8f9f7 4829 #define GPIO_BSRR_BS_12 0x00001000U
<> 144:ef7eb2e8f9f7 4830 #define GPIO_BSRR_BS_13 0x00002000U
<> 144:ef7eb2e8f9f7 4831 #define GPIO_BSRR_BS_14 0x00004000U
<> 144:ef7eb2e8f9f7 4832 #define GPIO_BSRR_BS_15 0x00008000U
<> 144:ef7eb2e8f9f7 4833 #define GPIO_BSRR_BR_0 0x00010000U
<> 144:ef7eb2e8f9f7 4834 #define GPIO_BSRR_BR_1 0x00020000U
<> 144:ef7eb2e8f9f7 4835 #define GPIO_BSRR_BR_2 0x00040000U
<> 144:ef7eb2e8f9f7 4836 #define GPIO_BSRR_BR_3 0x00080000U
<> 144:ef7eb2e8f9f7 4837 #define GPIO_BSRR_BR_4 0x00100000U
<> 144:ef7eb2e8f9f7 4838 #define GPIO_BSRR_BR_5 0x00200000U
<> 144:ef7eb2e8f9f7 4839 #define GPIO_BSRR_BR_6 0x00400000U
<> 144:ef7eb2e8f9f7 4840 #define GPIO_BSRR_BR_7 0x00800000U
<> 144:ef7eb2e8f9f7 4841 #define GPIO_BSRR_BR_8 0x01000000U
<> 144:ef7eb2e8f9f7 4842 #define GPIO_BSRR_BR_9 0x02000000U
<> 144:ef7eb2e8f9f7 4843 #define GPIO_BSRR_BR_10 0x04000000U
<> 144:ef7eb2e8f9f7 4844 #define GPIO_BSRR_BR_11 0x08000000U
<> 144:ef7eb2e8f9f7 4845 #define GPIO_BSRR_BR_12 0x10000000U
<> 144:ef7eb2e8f9f7 4846 #define GPIO_BSRR_BR_13 0x20000000U
<> 144:ef7eb2e8f9f7 4847 #define GPIO_BSRR_BR_14 0x40000000U
<> 144:ef7eb2e8f9f7 4848 #define GPIO_BSRR_BR_15 0x80000000U
mbed_official 74:9322579e4309 4849
mbed_official 74:9322579e4309 4850 /****************** Bit definition for GPIO_LCKR register *********************/
<> 144:ef7eb2e8f9f7 4851 #define GPIO_LCKR_LCK0 0x00000001U
<> 144:ef7eb2e8f9f7 4852 #define GPIO_LCKR_LCK1 0x00000002U
<> 144:ef7eb2e8f9f7 4853 #define GPIO_LCKR_LCK2 0x00000004U
<> 144:ef7eb2e8f9f7 4854 #define GPIO_LCKR_LCK3 0x00000008U
<> 144:ef7eb2e8f9f7 4855 #define GPIO_LCKR_LCK4 0x00000010U
<> 144:ef7eb2e8f9f7 4856 #define GPIO_LCKR_LCK5 0x00000020U
<> 144:ef7eb2e8f9f7 4857 #define GPIO_LCKR_LCK6 0x00000040U
<> 144:ef7eb2e8f9f7 4858 #define GPIO_LCKR_LCK7 0x00000080U
<> 144:ef7eb2e8f9f7 4859 #define GPIO_LCKR_LCK8 0x00000100U
<> 144:ef7eb2e8f9f7 4860 #define GPIO_LCKR_LCK9 0x00000200U
<> 144:ef7eb2e8f9f7 4861 #define GPIO_LCKR_LCK10 0x00000400U
<> 144:ef7eb2e8f9f7 4862 #define GPIO_LCKR_LCK11 0x00000800U
<> 144:ef7eb2e8f9f7 4863 #define GPIO_LCKR_LCK12 0x00001000U
<> 144:ef7eb2e8f9f7 4864 #define GPIO_LCKR_LCK13 0x00002000U
<> 144:ef7eb2e8f9f7 4865 #define GPIO_LCKR_LCK14 0x00004000U
<> 144:ef7eb2e8f9f7 4866 #define GPIO_LCKR_LCK15 0x00008000U
<> 144:ef7eb2e8f9f7 4867 #define GPIO_LCKR_LCKK 0x00010000U
mbed_official 74:9322579e4309 4868
mbed_official 83:a036322b8637 4869
mbed_official 74:9322579e4309 4870 /******************************************************************************/
mbed_official 74:9322579e4309 4871 /* */
mbed_official 74:9322579e4309 4872 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 74:9322579e4309 4873 /* */
mbed_official 74:9322579e4309 4874 /******************************************************************************/
mbed_official 74:9322579e4309 4875 /******************* Bit definition for I2C_CR1 register *******************/
<> 144:ef7eb2e8f9f7 4876 #define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */
<> 144:ef7eb2e8f9f7 4877 #define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
<> 144:ef7eb2e8f9f7 4878 #define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
<> 144:ef7eb2e8f9f7 4879 #define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
<> 144:ef7eb2e8f9f7 4880 #define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
<> 144:ef7eb2e8f9f7 4881 #define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
<> 144:ef7eb2e8f9f7 4882 #define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
<> 144:ef7eb2e8f9f7 4883 #define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
<> 144:ef7eb2e8f9f7 4884 #define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */
<> 144:ef7eb2e8f9f7 4885 #define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
<> 144:ef7eb2e8f9f7 4886 #define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
<> 144:ef7eb2e8f9f7 4887 #define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
<> 144:ef7eb2e8f9f7 4888 #define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */
<> 144:ef7eb2e8f9f7 4889 #define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
<> 144:ef7eb2e8f9f7 4890 #define I2C_CR1_GCEN 0x00080000U /*!< General call enable */
<> 144:ef7eb2e8f9f7 4891 #define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
<> 144:ef7eb2e8f9f7 4892 #define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
<> 144:ef7eb2e8f9f7 4893 #define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
<> 144:ef7eb2e8f9f7 4894 #define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */
mbed_official 74:9322579e4309 4895
mbed_official 83:a036322b8637 4896 /* Legacy define */
mbed_official 83:a036322b8637 4897 #define I2C_CR1_DFN I2C_CR1_DNF /*!< Digital noise filter */
mbed_official 83:a036322b8637 4898
mbed_official 74:9322579e4309 4899 /****************** Bit definition for I2C_CR2 register ********************/
<> 144:ef7eb2e8f9f7 4900 #define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
<> 144:ef7eb2e8f9f7 4901 #define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
<> 144:ef7eb2e8f9f7 4902 #define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
<> 144:ef7eb2e8f9f7 4903 #define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
<> 144:ef7eb2e8f9f7 4904 #define I2C_CR2_START 0x00002000U /*!< START generation */
<> 144:ef7eb2e8f9f7 4905 #define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
<> 144:ef7eb2e8f9f7 4906 #define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
<> 144:ef7eb2e8f9f7 4907 #define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
<> 144:ef7eb2e8f9f7 4908 #define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
<> 144:ef7eb2e8f9f7 4909 #define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
<> 144:ef7eb2e8f9f7 4910 #define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
mbed_official 74:9322579e4309 4911
mbed_official 74:9322579e4309 4912 /******************* Bit definition for I2C_OAR1 register ******************/
<> 144:ef7eb2e8f9f7 4913 #define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
<> 144:ef7eb2e8f9f7 4914 #define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
<> 144:ef7eb2e8f9f7 4915 #define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
mbed_official 74:9322579e4309 4916
mbed_official 74:9322579e4309 4917 /******************* Bit definition for I2C_OAR2 register ******************/
<> 144:ef7eb2e8f9f7 4918 #define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
<> 144:ef7eb2e8f9f7 4919 #define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
<> 144:ef7eb2e8f9f7 4920 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
<> 144:ef7eb2e8f9f7 4921 #define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 144:ef7eb2e8f9f7 4922 #define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 144:ef7eb2e8f9f7 4923 #define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 144:ef7eb2e8f9f7 4924 #define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 144:ef7eb2e8f9f7 4925 #define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 144:ef7eb2e8f9f7 4926 #define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 144:ef7eb2e8f9f7 4927 #define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */
<> 144:ef7eb2e8f9f7 4928 #define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
mbed_official 74:9322579e4309 4929
mbed_official 74:9322579e4309 4930 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 144:ef7eb2e8f9f7 4931 #define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
<> 144:ef7eb2e8f9f7 4932 #define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
<> 144:ef7eb2e8f9f7 4933 #define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
<> 144:ef7eb2e8f9f7 4934 #define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
<> 144:ef7eb2e8f9f7 4935 #define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
mbed_official 74:9322579e4309 4936
mbed_official 74:9322579e4309 4937 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 144:ef7eb2e8f9f7 4938 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
<> 144:ef7eb2e8f9f7 4939 #define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
<> 144:ef7eb2e8f9f7 4940 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
<> 144:ef7eb2e8f9f7 4941 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
<> 144:ef7eb2e8f9f7 4942 #define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
mbed_official 74:9322579e4309 4943
mbed_official 74:9322579e4309 4944 /****************** Bit definition for I2C_ISR register *********************/
<> 144:ef7eb2e8f9f7 4945 #define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
<> 144:ef7eb2e8f9f7 4946 #define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
<> 144:ef7eb2e8f9f7 4947 #define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
<> 144:ef7eb2e8f9f7 4948 #define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
<> 144:ef7eb2e8f9f7 4949 #define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
<> 144:ef7eb2e8f9f7 4950 #define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
<> 144:ef7eb2e8f9f7 4951 #define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
<> 144:ef7eb2e8f9f7 4952 #define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
<> 144:ef7eb2e8f9f7 4953 #define I2C_ISR_BERR 0x00000100U /*!< Bus error */
<> 144:ef7eb2e8f9f7 4954 #define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
<> 144:ef7eb2e8f9f7 4955 #define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
<> 144:ef7eb2e8f9f7 4956 #define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
<> 144:ef7eb2e8f9f7 4957 #define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
<> 144:ef7eb2e8f9f7 4958 #define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
<> 144:ef7eb2e8f9f7 4959 #define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */
<> 144:ef7eb2e8f9f7 4960 #define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
<> 144:ef7eb2e8f9f7 4961 #define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
mbed_official 74:9322579e4309 4962
mbed_official 74:9322579e4309 4963 /****************** Bit definition for I2C_ICR register *********************/
<> 144:ef7eb2e8f9f7 4964 #define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
<> 144:ef7eb2e8f9f7 4965 #define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
<> 144:ef7eb2e8f9f7 4966 #define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
<> 144:ef7eb2e8f9f7 4967 #define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
<> 144:ef7eb2e8f9f7 4968 #define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
<> 144:ef7eb2e8f9f7 4969 #define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
<> 144:ef7eb2e8f9f7 4970 #define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
<> 144:ef7eb2e8f9f7 4971 #define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
<> 144:ef7eb2e8f9f7 4972 #define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
mbed_official 74:9322579e4309 4973
mbed_official 74:9322579e4309 4974 /****************** Bit definition for I2C_PECR register *********************/
<> 144:ef7eb2e8f9f7 4975 #define I2C_PECR_PEC 0x000000FFU /*!< PEC register */
mbed_official 74:9322579e4309 4976
mbed_official 74:9322579e4309 4977 /****************** Bit definition for I2C_RXDR register *********************/
<> 144:ef7eb2e8f9f7 4978 #define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
mbed_official 74:9322579e4309 4979
mbed_official 74:9322579e4309 4980 /****************** Bit definition for I2C_TXDR register *********************/
<> 144:ef7eb2e8f9f7 4981 #define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
mbed_official 74:9322579e4309 4982
mbed_official 74:9322579e4309 4983
mbed_official 74:9322579e4309 4984 /******************************************************************************/
mbed_official 74:9322579e4309 4985 /* */
mbed_official 74:9322579e4309 4986 /* Independent WATCHDOG */
mbed_official 74:9322579e4309 4987 /* */
mbed_official 74:9322579e4309 4988 /******************************************************************************/
mbed_official 74:9322579e4309 4989 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 4990 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
mbed_official 74:9322579e4309 4991
mbed_official 74:9322579e4309 4992 /******************* Bit definition for IWDG_PR register ********************/
<> 144:ef7eb2e8f9f7 4993 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
<> 144:ef7eb2e8f9f7 4994 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 4995 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 4996 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
mbed_official 74:9322579e4309 4997
mbed_official 74:9322579e4309 4998 /******************* Bit definition for IWDG_RLR register *******************/
<> 144:ef7eb2e8f9f7 4999 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
mbed_official 74:9322579e4309 5000
mbed_official 74:9322579e4309 5001 /******************* Bit definition for IWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 5002 #define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 5003 #define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 5004 #define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */
mbed_official 74:9322579e4309 5005
mbed_official 74:9322579e4309 5006 /******************* Bit definition for IWDG_KR register ********************/
<> 144:ef7eb2e8f9f7 5007 #define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */
mbed_official 74:9322579e4309 5008
mbed_official 74:9322579e4309 5009 /******************************************************************************/
mbed_official 74:9322579e4309 5010 /* */
mbed_official 74:9322579e4309 5011 /* LCD-TFT Display Controller (LTDC) */
mbed_official 74:9322579e4309 5012 /* */
mbed_official 74:9322579e4309 5013 /******************************************************************************/
mbed_official 74:9322579e4309 5014
mbed_official 74:9322579e4309 5015 /******************** Bit definition for LTDC_SSCR register *****************/
mbed_official 74:9322579e4309 5016
<> 144:ef7eb2e8f9f7 5017 #define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
<> 144:ef7eb2e8f9f7 5018 #define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
mbed_official 74:9322579e4309 5019
mbed_official 74:9322579e4309 5020 /******************** Bit definition for LTDC_BPCR register *****************/
mbed_official 74:9322579e4309 5021
<> 144:ef7eb2e8f9f7 5022 #define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
<> 144:ef7eb2e8f9f7 5023 #define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
mbed_official 74:9322579e4309 5024
mbed_official 74:9322579e4309 5025 /******************** Bit definition for LTDC_AWCR register *****************/
mbed_official 74:9322579e4309 5026
<> 144:ef7eb2e8f9f7 5027 #define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
<> 144:ef7eb2e8f9f7 5028 #define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
mbed_official 74:9322579e4309 5029
mbed_official 74:9322579e4309 5030 /******************** Bit definition for LTDC_TWCR register *****************/
mbed_official 74:9322579e4309 5031
<> 144:ef7eb2e8f9f7 5032 #define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
<> 144:ef7eb2e8f9f7 5033 #define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
mbed_official 74:9322579e4309 5034
mbed_official 74:9322579e4309 5035 /******************** Bit definition for LTDC_GCR register ******************/
mbed_official 74:9322579e4309 5036
<> 144:ef7eb2e8f9f7 5037 #define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
<> 144:ef7eb2e8f9f7 5038 #define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
<> 144:ef7eb2e8f9f7 5039 #define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
<> 144:ef7eb2e8f9f7 5040 #define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
<> 144:ef7eb2e8f9f7 5041 #define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
<> 144:ef7eb2e8f9f7 5042 #define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
<> 144:ef7eb2e8f9f7 5043 #define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
<> 144:ef7eb2e8f9f7 5044 #define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
<> 144:ef7eb2e8f9f7 5045 #define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
<> 144:ef7eb2e8f9f7 5046
<> 144:ef7eb2e8f9f7 5047 /* Legacy define */
<> 144:ef7eb2e8f9f7 5048 #define LTDC_GCR_DTEN LTDC_GCR_DEN
mbed_official 74:9322579e4309 5049
mbed_official 74:9322579e4309 5050 /******************** Bit definition for LTDC_SRCR register *****************/
mbed_official 74:9322579e4309 5051
<> 144:ef7eb2e8f9f7 5052 #define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
<> 144:ef7eb2e8f9f7 5053 #define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
mbed_official 74:9322579e4309 5054
mbed_official 74:9322579e4309 5055 /******************** Bit definition for LTDC_BCCR register *****************/
mbed_official 74:9322579e4309 5056
<> 144:ef7eb2e8f9f7 5057 #define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
<> 144:ef7eb2e8f9f7 5058 #define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
<> 144:ef7eb2e8f9f7 5059 #define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
mbed_official 74:9322579e4309 5060
mbed_official 74:9322579e4309 5061 /******************** Bit definition for LTDC_IER register ******************/
mbed_official 74:9322579e4309 5062
<> 144:ef7eb2e8f9f7 5063 #define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
<> 144:ef7eb2e8f9f7 5064 #define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
<> 144:ef7eb2e8f9f7 5065 #define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 5066 #define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
mbed_official 74:9322579e4309 5067
mbed_official 74:9322579e4309 5068 /******************** Bit definition for LTDC_ISR register ******************/
mbed_official 74:9322579e4309 5069
<> 144:ef7eb2e8f9f7 5070 #define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
<> 144:ef7eb2e8f9f7 5071 #define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
<> 144:ef7eb2e8f9f7 5072 #define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 5073 #define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
mbed_official 74:9322579e4309 5074
mbed_official 74:9322579e4309 5075 /******************** Bit definition for LTDC_ICR register ******************/
mbed_official 74:9322579e4309 5076
<> 144:ef7eb2e8f9f7 5077 #define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
<> 144:ef7eb2e8f9f7 5078 #define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
<> 144:ef7eb2e8f9f7 5079 #define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 5080 #define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
mbed_official 74:9322579e4309 5081
mbed_official 74:9322579e4309 5082 /******************** Bit definition for LTDC_LIPCR register ****************/
mbed_official 74:9322579e4309 5083
<> 144:ef7eb2e8f9f7 5084 #define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
mbed_official 74:9322579e4309 5085
mbed_official 74:9322579e4309 5086 /******************** Bit definition for LTDC_CPSR register *****************/
mbed_official 74:9322579e4309 5087
<> 144:ef7eb2e8f9f7 5088 #define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
<> 144:ef7eb2e8f9f7 5089 #define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
mbed_official 74:9322579e4309 5090
mbed_official 74:9322579e4309 5091 /******************** Bit definition for LTDC_CDSR register *****************/
mbed_official 74:9322579e4309 5092
<> 144:ef7eb2e8f9f7 5093 #define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
<> 144:ef7eb2e8f9f7 5094 #define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
<> 144:ef7eb2e8f9f7 5095 #define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
<> 144:ef7eb2e8f9f7 5096 #define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
mbed_official 74:9322579e4309 5097
mbed_official 74:9322579e4309 5098 /******************** Bit definition for LTDC_LxCR register *****************/
mbed_official 74:9322579e4309 5099
<> 144:ef7eb2e8f9f7 5100 #define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
<> 144:ef7eb2e8f9f7 5101 #define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
<> 144:ef7eb2e8f9f7 5102 #define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
mbed_official 74:9322579e4309 5103
mbed_official 74:9322579e4309 5104 /******************** Bit definition for LTDC_LxWHPCR register **************/
mbed_official 74:9322579e4309 5105
<> 144:ef7eb2e8f9f7 5106 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
<> 144:ef7eb2e8f9f7 5107 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
mbed_official 74:9322579e4309 5108
mbed_official 74:9322579e4309 5109 /******************** Bit definition for LTDC_LxWVPCR register **************/
mbed_official 74:9322579e4309 5110
<> 144:ef7eb2e8f9f7 5111 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
<> 144:ef7eb2e8f9f7 5112 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
mbed_official 74:9322579e4309 5113
mbed_official 74:9322579e4309 5114 /******************** Bit definition for LTDC_LxCKCR register ***************/
mbed_official 74:9322579e4309 5115
<> 144:ef7eb2e8f9f7 5116 #define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
<> 144:ef7eb2e8f9f7 5117 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
<> 144:ef7eb2e8f9f7 5118 #define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
mbed_official 74:9322579e4309 5119
mbed_official 74:9322579e4309 5120 /******************** Bit definition for LTDC_LxPFCR register ***************/
mbed_official 74:9322579e4309 5121
<> 144:ef7eb2e8f9f7 5122 #define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
mbed_official 74:9322579e4309 5123
mbed_official 74:9322579e4309 5124 /******************** Bit definition for LTDC_LxCACR register ***************/
mbed_official 74:9322579e4309 5125
<> 144:ef7eb2e8f9f7 5126 #define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
mbed_official 74:9322579e4309 5127
mbed_official 74:9322579e4309 5128 /******************** Bit definition for LTDC_LxDCCR register ***************/
mbed_official 74:9322579e4309 5129
<> 144:ef7eb2e8f9f7 5130 #define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
<> 144:ef7eb2e8f9f7 5131 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
<> 144:ef7eb2e8f9f7 5132 #define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
<> 144:ef7eb2e8f9f7 5133 #define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
mbed_official 74:9322579e4309 5134
mbed_official 74:9322579e4309 5135 /******************** Bit definition for LTDC_LxBFCR register ***************/
mbed_official 74:9322579e4309 5136
<> 144:ef7eb2e8f9f7 5137 #define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
<> 144:ef7eb2e8f9f7 5138 #define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
mbed_official 74:9322579e4309 5139
mbed_official 74:9322579e4309 5140 /******************** Bit definition for LTDC_LxCFBAR register **************/
mbed_official 74:9322579e4309 5141
<> 144:ef7eb2e8f9f7 5142 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
mbed_official 74:9322579e4309 5143
mbed_official 74:9322579e4309 5144 /******************** Bit definition for LTDC_LxCFBLR register **************/
mbed_official 74:9322579e4309 5145
<> 144:ef7eb2e8f9f7 5146 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
<> 144:ef7eb2e8f9f7 5147 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
mbed_official 74:9322579e4309 5148
mbed_official 74:9322579e4309 5149 /******************** Bit definition for LTDC_LxCFBLNR register *************/
mbed_official 74:9322579e4309 5150
<> 144:ef7eb2e8f9f7 5151 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
mbed_official 74:9322579e4309 5152
mbed_official 74:9322579e4309 5153 /******************** Bit definition for LTDC_LxCLUTWR register *************/
mbed_official 74:9322579e4309 5154
<> 144:ef7eb2e8f9f7 5155 #define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
<> 144:ef7eb2e8f9f7 5156 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
<> 144:ef7eb2e8f9f7 5157 #define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
<> 144:ef7eb2e8f9f7 5158 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
mbed_official 74:9322579e4309 5159
mbed_official 74:9322579e4309 5160 /******************************************************************************/
mbed_official 74:9322579e4309 5161 /* */
mbed_official 74:9322579e4309 5162 /* Power Control */
mbed_official 74:9322579e4309 5163 /* */
mbed_official 74:9322579e4309 5164 /******************************************************************************/
mbed_official 74:9322579e4309 5165 /******************** Bit definition for PWR_CR1 register ********************/
<> 144:ef7eb2e8f9f7 5166 #define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 144:ef7eb2e8f9f7 5167 #define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 144:ef7eb2e8f9f7 5168 #define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 144:ef7eb2e8f9f7 5169 #define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 144:ef7eb2e8f9f7 5170 #define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 144:ef7eb2e8f9f7 5171 #define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5172 #define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5173 #define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */
mbed_official 74:9322579e4309 5174
mbed_official 74:9322579e4309 5175 /*!< PVD level configuration */
<> 144:ef7eb2e8f9f7 5176 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 144:ef7eb2e8f9f7 5177 #define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 144:ef7eb2e8f9f7 5178 #define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 144:ef7eb2e8f9f7 5179 #define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 144:ef7eb2e8f9f7 5180 #define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 144:ef7eb2e8f9f7 5181 #define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 144:ef7eb2e8f9f7 5182 #define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 144:ef7eb2e8f9f7 5183 #define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 144:ef7eb2e8f9f7 5184 #define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 144:ef7eb2e8f9f7 5185 #define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 144:ef7eb2e8f9f7 5186 #define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */
<> 144:ef7eb2e8f9f7 5187 #define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */
<> 144:ef7eb2e8f9f7 5188 #define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 5189 #define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 144:ef7eb2e8f9f7 5190 #define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5191 #define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5192 #define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */
<> 144:ef7eb2e8f9f7 5193 #define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
<> 144:ef7eb2e8f9f7 5194 #define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
<> 144:ef7eb2e8f9f7 5195 #define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5196 #define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */
mbed_official 74:9322579e4309 5197
mbed_official 74:9322579e4309 5198 /******************* Bit definition for PWR_CSR1 register ********************/
<> 144:ef7eb2e8f9f7 5199 #define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */
<> 144:ef7eb2e8f9f7 5200 #define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */
<> 144:ef7eb2e8f9f7 5201 #define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */
<> 144:ef7eb2e8f9f7 5202 #define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */
<> 144:ef7eb2e8f9f7 5203 #define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */
<> 144:ef7eb2e8f9f7 5204 #define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */
<> 144:ef7eb2e8f9f7 5205 #define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
<> 144:ef7eb2e8f9f7 5206 #define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */
<> 144:ef7eb2e8f9f7 5207 #define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
<> 144:ef7eb2e8f9f7 5208 #define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */
<> 144:ef7eb2e8f9f7 5209
<> 144:ef7eb2e8f9f7 5210 /* Legacy define */
<> 144:ef7eb2e8f9f7 5211 #define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
mbed_official 74:9322579e4309 5212
mbed_official 74:9322579e4309 5213 /******************** Bit definition for PWR_CR2 register ********************/
<> 144:ef7eb2e8f9f7 5214 #define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */
<> 144:ef7eb2e8f9f7 5215 #define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */
<> 144:ef7eb2e8f9f7 5216 #define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */
<> 144:ef7eb2e8f9f7 5217 #define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */
<> 144:ef7eb2e8f9f7 5218 #define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */
<> 144:ef7eb2e8f9f7 5219 #define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */
<> 144:ef7eb2e8f9f7 5220 #define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */
<> 144:ef7eb2e8f9f7 5221 #define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */
<> 144:ef7eb2e8f9f7 5222 #define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */
<> 144:ef7eb2e8f9f7 5223 #define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */
<> 144:ef7eb2e8f9f7 5224 #define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */
<> 144:ef7eb2e8f9f7 5225 #define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */
mbed_official 74:9322579e4309 5226
mbed_official 74:9322579e4309 5227 /******************* Bit definition for PWR_CSR2 register ********************/
<> 144:ef7eb2e8f9f7 5228 #define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */
<> 144:ef7eb2e8f9f7 5229 #define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */
<> 144:ef7eb2e8f9f7 5230 #define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */
<> 144:ef7eb2e8f9f7 5231 #define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */
<> 144:ef7eb2e8f9f7 5232 #define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */
<> 144:ef7eb2e8f9f7 5233 #define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */
<> 144:ef7eb2e8f9f7 5234 #define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */
<> 144:ef7eb2e8f9f7 5235 #define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */
<> 144:ef7eb2e8f9f7 5236 #define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */
<> 144:ef7eb2e8f9f7 5237 #define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */
<> 144:ef7eb2e8f9f7 5238 #define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */
<> 144:ef7eb2e8f9f7 5239 #define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */
mbed_official 74:9322579e4309 5240
mbed_official 74:9322579e4309 5241 /******************************************************************************/
mbed_official 74:9322579e4309 5242 /* */
mbed_official 74:9322579e4309 5243 /* QUADSPI */
mbed_official 74:9322579e4309 5244 /* */
mbed_official 74:9322579e4309 5245 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5246 /* QUADSPI IP version */
<> 144:ef7eb2e8f9f7 5247 #define QSPI1_V1_0
mbed_official 74:9322579e4309 5248 /***************** Bit definition for QUADSPI_CR register *******************/
<> 144:ef7eb2e8f9f7 5249 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
<> 144:ef7eb2e8f9f7 5250 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
<> 144:ef7eb2e8f9f7 5251 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
<> 144:ef7eb2e8f9f7 5252 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
<> 144:ef7eb2e8f9f7 5253 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */
<> 144:ef7eb2e8f9f7 5254 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
<> 144:ef7eb2e8f9f7 5255 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
<> 144:ef7eb2e8f9f7 5256 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */
<> 144:ef7eb2e8f9f7 5257 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5258 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5259 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5260 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5261 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5262 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 5263 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 5264 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
<> 144:ef7eb2e8f9f7 5265 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
<> 144:ef7eb2e8f9f7 5266 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 5267 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5268 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
<> 144:ef7eb2e8f9f7 5269 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
<> 144:ef7eb2e8f9f7 5270 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5271 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5272 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5273 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5274 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5275 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 5276 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 5277 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
mbed_official 74:9322579e4309 5278
mbed_official 74:9322579e4309 5279 /***************** Bit definition for QUADSPI_DCR register ******************/
<> 144:ef7eb2e8f9f7 5280 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
<> 144:ef7eb2e8f9f7 5281 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
<> 144:ef7eb2e8f9f7 5282 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5283 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5284 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5285 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
<> 144:ef7eb2e8f9f7 5286 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5287 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5288 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5289 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5290 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
mbed_official 74:9322579e4309 5291
mbed_official 74:9322579e4309 5292 /****************** Bit definition for QUADSPI_SR register *******************/
<> 144:ef7eb2e8f9f7 5293 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
<> 144:ef7eb2e8f9f7 5294 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
<> 144:ef7eb2e8f9f7 5295 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
<> 144:ef7eb2e8f9f7 5296 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
<> 144:ef7eb2e8f9f7 5297 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
<> 144:ef7eb2e8f9f7 5298 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
<> 144:ef7eb2e8f9f7 5299 #define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */
<> 144:ef7eb2e8f9f7 5300 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5301 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5302 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5303 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5304 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
mbed_official 74:9322579e4309 5305
mbed_official 74:9322579e4309 5306 /****************** Bit definition for QUADSPI_FCR register ******************/
<> 144:ef7eb2e8f9f7 5307 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
<> 144:ef7eb2e8f9f7 5308 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
<> 144:ef7eb2e8f9f7 5309 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
<> 144:ef7eb2e8f9f7 5310 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
mbed_official 74:9322579e4309 5311
mbed_official 74:9322579e4309 5312 /****************** Bit definition for QUADSPI_DLR register ******************/
<> 144:ef7eb2e8f9f7 5313 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
mbed_official 74:9322579e4309 5314
mbed_official 74:9322579e4309 5315 /****************** Bit definition for QUADSPI_CCR register ******************/
<> 144:ef7eb2e8f9f7 5316 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
<> 144:ef7eb2e8f9f7 5317 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5318 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5319 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5320 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5321 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5322 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
<> 144:ef7eb2e8f9f7 5323 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
<> 144:ef7eb2e8f9f7 5324 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
<> 144:ef7eb2e8f9f7 5325 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
<> 144:ef7eb2e8f9f7 5326 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5327 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5328 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
<> 144:ef7eb2e8f9f7 5329 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5330 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5331 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
<> 144:ef7eb2e8f9f7 5332 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5333 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5334 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
<> 144:ef7eb2e8f9f7 5335 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5336 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5337 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
<> 144:ef7eb2e8f9f7 5338 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5339 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5340 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
<> 144:ef7eb2e8f9f7 5341 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5342 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5343 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5344 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5345 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 5346 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
<> 144:ef7eb2e8f9f7 5347 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5348 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5349 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
<> 144:ef7eb2e8f9f7 5350 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5351 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5352 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
<> 144:ef7eb2e8f9f7 5353 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
<> 144:ef7eb2e8f9f7 5354 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
mbed_official 74:9322579e4309 5355 /****************** Bit definition for QUADSPI_AR register *******************/
<> 144:ef7eb2e8f9f7 5356 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
mbed_official 74:9322579e4309 5357
mbed_official 74:9322579e4309 5358 /****************** Bit definition for QUADSPI_ABR register ******************/
<> 144:ef7eb2e8f9f7 5359 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
mbed_official 74:9322579e4309 5360
mbed_official 74:9322579e4309 5361 /****************** Bit definition for QUADSPI_DR register *******************/
<> 144:ef7eb2e8f9f7 5362 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
mbed_official 74:9322579e4309 5363
mbed_official 74:9322579e4309 5364 /****************** Bit definition for QUADSPI_PSMKR register ****************/
<> 144:ef7eb2e8f9f7 5365 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
mbed_official 74:9322579e4309 5366
mbed_official 74:9322579e4309 5367 /****************** Bit definition for QUADSPI_PSMAR register ****************/
<> 144:ef7eb2e8f9f7 5368 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
mbed_official 74:9322579e4309 5369
mbed_official 74:9322579e4309 5370 /****************** Bit definition for QUADSPI_PIR register *****************/
<> 144:ef7eb2e8f9f7 5371 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
mbed_official 74:9322579e4309 5372
mbed_official 74:9322579e4309 5373 /****************** Bit definition for QUADSPI_LPTR register *****************/
<> 144:ef7eb2e8f9f7 5374 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
mbed_official 74:9322579e4309 5375
mbed_official 74:9322579e4309 5376 /******************************************************************************/
mbed_official 74:9322579e4309 5377 /* */
mbed_official 74:9322579e4309 5378 /* Reset and Clock Control */
mbed_official 74:9322579e4309 5379 /* */
mbed_official 74:9322579e4309 5380 /******************************************************************************/
mbed_official 74:9322579e4309 5381 /******************** Bit definition for RCC_CR register ********************/
<> 144:ef7eb2e8f9f7 5382 #define RCC_CR_HSION 0x00000001U
<> 144:ef7eb2e8f9f7 5383 #define RCC_CR_HSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 5384 #define RCC_CR_HSITRIM 0x000000F8U
<> 144:ef7eb2e8f9f7 5385 #define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5386 #define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5387 #define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5388 #define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 5389 #define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 5390 #define RCC_CR_HSICAL 0x0000FF00U
<> 144:ef7eb2e8f9f7 5391 #define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 5392 #define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 5393 #define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 5394 #define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 5395 #define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 5396 #define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 5397 #define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 5398 #define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 5399 #define RCC_CR_HSEON 0x00010000U
<> 144:ef7eb2e8f9f7 5400 #define RCC_CR_HSERDY 0x00020000U
<> 144:ef7eb2e8f9f7 5401 #define RCC_CR_HSEBYP 0x00040000U
<> 144:ef7eb2e8f9f7 5402 #define RCC_CR_CSSON 0x00080000U
<> 144:ef7eb2e8f9f7 5403 #define RCC_CR_PLLON 0x01000000U
<> 144:ef7eb2e8f9f7 5404 #define RCC_CR_PLLRDY 0x02000000U
<> 144:ef7eb2e8f9f7 5405 #define RCC_CR_PLLI2SON 0x04000000U
<> 144:ef7eb2e8f9f7 5406 #define RCC_CR_PLLI2SRDY 0x08000000U
<> 144:ef7eb2e8f9f7 5407 #define RCC_CR_PLLSAION 0x10000000U
<> 144:ef7eb2e8f9f7 5408 #define RCC_CR_PLLSAIRDY 0x20000000U
mbed_official 74:9322579e4309 5409
mbed_official 74:9322579e4309 5410 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 144:ef7eb2e8f9f7 5411 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 144:ef7eb2e8f9f7 5412 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 144:ef7eb2e8f9f7 5413 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 144:ef7eb2e8f9f7 5414 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 144:ef7eb2e8f9f7 5415 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 144:ef7eb2e8f9f7 5416 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 144:ef7eb2e8f9f7 5417 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 144:ef7eb2e8f9f7 5418 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 144:ef7eb2e8f9f7 5419 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 144:ef7eb2e8f9f7 5420 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 144:ef7eb2e8f9f7 5421 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 144:ef7eb2e8f9f7 5422 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 144:ef7eb2e8f9f7 5423 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 144:ef7eb2e8f9f7 5424 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 144:ef7eb2e8f9f7 5425 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 144:ef7eb2e8f9f7 5426 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 144:ef7eb2e8f9f7 5427 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 144:ef7eb2e8f9f7 5428 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 144:ef7eb2e8f9f7 5429 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 144:ef7eb2e8f9f7 5430 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 144:ef7eb2e8f9f7 5431 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 144:ef7eb2e8f9f7 5432 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 144:ef7eb2e8f9f7 5433 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 144:ef7eb2e8f9f7 5434 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 144:ef7eb2e8f9f7 5435 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 5436 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 5437 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 5438 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
mbed_official 74:9322579e4309 5439
mbed_official 83:a036322b8637 5440
mbed_official 74:9322579e4309 5441 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 74:9322579e4309 5442 /*!< SW configuration */
<> 144:ef7eb2e8f9f7 5443 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 144:ef7eb2e8f9f7 5444 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5445 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5446 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 144:ef7eb2e8f9f7 5447 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 144:ef7eb2e8f9f7 5448 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
mbed_official 74:9322579e4309 5449
mbed_official 74:9322579e4309 5450 /*!< SWS configuration */
<> 144:ef7eb2e8f9f7 5451 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 144:ef7eb2e8f9f7 5452 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5453 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5454 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 144:ef7eb2e8f9f7 5455 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 144:ef7eb2e8f9f7 5456 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
mbed_official 74:9322579e4309 5457
mbed_official 74:9322579e4309 5458 /*!< HPRE configuration */
<> 144:ef7eb2e8f9f7 5459 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 144:ef7eb2e8f9f7 5460 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5461 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5462 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5463 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 5464
<> 144:ef7eb2e8f9f7 5465 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 144:ef7eb2e8f9f7 5466 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5467 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5468 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5469 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 144:ef7eb2e8f9f7 5470 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 144:ef7eb2e8f9f7 5471 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 144:ef7eb2e8f9f7 5472 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 144:ef7eb2e8f9f7 5473 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
mbed_official 74:9322579e4309 5474
mbed_official 74:9322579e4309 5475 /*!< PPRE1 configuration */
<> 144:ef7eb2e8f9f7 5476 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 144:ef7eb2e8f9f7 5477 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5478 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5479 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5480
<> 144:ef7eb2e8f9f7 5481 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 5482 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5483 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5484 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5485 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
mbed_official 74:9322579e4309 5486
mbed_official 74:9322579e4309 5487 /*!< PPRE2 configuration */
<> 144:ef7eb2e8f9f7 5488 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 144:ef7eb2e8f9f7 5489 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 5490 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 5491 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 5492
<> 144:ef7eb2e8f9f7 5493 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 144:ef7eb2e8f9f7 5494 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 144:ef7eb2e8f9f7 5495 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 144:ef7eb2e8f9f7 5496 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 144:ef7eb2e8f9f7 5497 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
mbed_official 74:9322579e4309 5498
mbed_official 74:9322579e4309 5499 /*!< RTCPRE configuration */
<> 144:ef7eb2e8f9f7 5500 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 144:ef7eb2e8f9f7 5501 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 144:ef7eb2e8f9f7 5502 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 144:ef7eb2e8f9f7 5503 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 144:ef7eb2e8f9f7 5504 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 144:ef7eb2e8f9f7 5505 #define RCC_CFGR_RTCPRE_4 0x00100000U
mbed_official 74:9322579e4309 5506
mbed_official 74:9322579e4309 5507 /*!< MCO1 configuration */
<> 144:ef7eb2e8f9f7 5508 #define RCC_CFGR_MCO1 0x00600000U
<> 144:ef7eb2e8f9f7 5509 #define RCC_CFGR_MCO1_0 0x00200000U
<> 144:ef7eb2e8f9f7 5510 #define RCC_CFGR_MCO1_1 0x00400000U
<> 144:ef7eb2e8f9f7 5511
<> 144:ef7eb2e8f9f7 5512 #define RCC_CFGR_I2SSRC 0x00800000U
<> 144:ef7eb2e8f9f7 5513
<> 144:ef7eb2e8f9f7 5514 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 144:ef7eb2e8f9f7 5515 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 144:ef7eb2e8f9f7 5516 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 144:ef7eb2e8f9f7 5517 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 144:ef7eb2e8f9f7 5518
<> 144:ef7eb2e8f9f7 5519 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 144:ef7eb2e8f9f7 5520 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 144:ef7eb2e8f9f7 5521 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 144:ef7eb2e8f9f7 5522 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 144:ef7eb2e8f9f7 5523
<> 144:ef7eb2e8f9f7 5524 #define RCC_CFGR_MCO2 0xC0000000U
<> 144:ef7eb2e8f9f7 5525 #define RCC_CFGR_MCO2_0 0x40000000U
<> 144:ef7eb2e8f9f7 5526 #define RCC_CFGR_MCO2_1 0x80000000U
mbed_official 74:9322579e4309 5527
mbed_official 74:9322579e4309 5528 /******************** Bit definition for RCC_CIR register *******************/
<> 144:ef7eb2e8f9f7 5529 #define RCC_CIR_LSIRDYF 0x00000001U
<> 144:ef7eb2e8f9f7 5530 #define RCC_CIR_LSERDYF 0x00000002U
<> 144:ef7eb2e8f9f7 5531 #define RCC_CIR_HSIRDYF 0x00000004U
<> 144:ef7eb2e8f9f7 5532 #define RCC_CIR_HSERDYF 0x00000008U
<> 144:ef7eb2e8f9f7 5533 #define RCC_CIR_PLLRDYF 0x00000010U
<> 144:ef7eb2e8f9f7 5534 #define RCC_CIR_PLLI2SRDYF 0x00000020U
<> 144:ef7eb2e8f9f7 5535 #define RCC_CIR_PLLSAIRDYF 0x00000040U
<> 144:ef7eb2e8f9f7 5536 #define RCC_CIR_CSSF 0x00000080U
<> 144:ef7eb2e8f9f7 5537 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 144:ef7eb2e8f9f7 5538 #define RCC_CIR_LSERDYIE 0x00000200U
<> 144:ef7eb2e8f9f7 5539 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 144:ef7eb2e8f9f7 5540 #define RCC_CIR_HSERDYIE 0x00000800U
<> 144:ef7eb2e8f9f7 5541 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 144:ef7eb2e8f9f7 5542 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
<> 144:ef7eb2e8f9f7 5543 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
<> 144:ef7eb2e8f9f7 5544 #define RCC_CIR_LSIRDYC 0x00010000U
<> 144:ef7eb2e8f9f7 5545 #define RCC_CIR_LSERDYC 0x00020000U
<> 144:ef7eb2e8f9f7 5546 #define RCC_CIR_HSIRDYC 0x00040000U
<> 144:ef7eb2e8f9f7 5547 #define RCC_CIR_HSERDYC 0x00080000U
<> 144:ef7eb2e8f9f7 5548 #define RCC_CIR_PLLRDYC 0x00100000U
<> 144:ef7eb2e8f9f7 5549 #define RCC_CIR_PLLI2SRDYC 0x00200000U
<> 144:ef7eb2e8f9f7 5550 #define RCC_CIR_PLLSAIRDYC 0x00400000U
<> 144:ef7eb2e8f9f7 5551 #define RCC_CIR_CSSC 0x00800000U
mbed_official 74:9322579e4309 5552
mbed_official 74:9322579e4309 5553 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 144:ef7eb2e8f9f7 5554 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 144:ef7eb2e8f9f7 5555 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 144:ef7eb2e8f9f7 5556 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 144:ef7eb2e8f9f7 5557 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
<> 144:ef7eb2e8f9f7 5558 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
<> 144:ef7eb2e8f9f7 5559 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
<> 144:ef7eb2e8f9f7 5560 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
<> 144:ef7eb2e8f9f7 5561 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 144:ef7eb2e8f9f7 5562 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
<> 144:ef7eb2e8f9f7 5563 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
<> 144:ef7eb2e8f9f7 5564 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
<> 144:ef7eb2e8f9f7 5565 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 144:ef7eb2e8f9f7 5566 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 144:ef7eb2e8f9f7 5567 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 144:ef7eb2e8f9f7 5568 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
<> 144:ef7eb2e8f9f7 5569 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
<> 144:ef7eb2e8f9f7 5570 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
mbed_official 74:9322579e4309 5571
mbed_official 74:9322579e4309 5572 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 144:ef7eb2e8f9f7 5573 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
<> 144:ef7eb2e8f9f7 5574 #define RCC_AHB2RSTR_RNGRST 0x00000040U
<> 144:ef7eb2e8f9f7 5575 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
mbed_official 74:9322579e4309 5576
mbed_official 74:9322579e4309 5577 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 74:9322579e4309 5578
<> 144:ef7eb2e8f9f7 5579 #define RCC_AHB3RSTR_FMCRST 0x00000001U
<> 144:ef7eb2e8f9f7 5580 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
mbed_official 74:9322579e4309 5581
mbed_official 74:9322579e4309 5582 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 144:ef7eb2e8f9f7 5583 #define RCC_APB1RSTR_TIM2RST 0x00000001U
<> 144:ef7eb2e8f9f7 5584 #define RCC_APB1RSTR_TIM3RST 0x00000002U
<> 144:ef7eb2e8f9f7 5585 #define RCC_APB1RSTR_TIM4RST 0x00000004U
<> 144:ef7eb2e8f9f7 5586 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 144:ef7eb2e8f9f7 5587 #define RCC_APB1RSTR_TIM6RST 0x00000010U
<> 144:ef7eb2e8f9f7 5588 #define RCC_APB1RSTR_TIM7RST 0x00000020U
<> 144:ef7eb2e8f9f7 5589 #define RCC_APB1RSTR_TIM12RST 0x00000040U
<> 144:ef7eb2e8f9f7 5590 #define RCC_APB1RSTR_TIM13RST 0x00000080U
<> 144:ef7eb2e8f9f7 5591 #define RCC_APB1RSTR_TIM14RST 0x00000100U
<> 144:ef7eb2e8f9f7 5592 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
<> 144:ef7eb2e8f9f7 5593 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 144:ef7eb2e8f9f7 5594 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 144:ef7eb2e8f9f7 5595 #define RCC_APB1RSTR_SPI3RST 0x00008000U
<> 144:ef7eb2e8f9f7 5596 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
<> 144:ef7eb2e8f9f7 5597 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 144:ef7eb2e8f9f7 5598 #define RCC_APB1RSTR_USART3RST 0x00040000U
<> 144:ef7eb2e8f9f7 5599 #define RCC_APB1RSTR_UART4RST 0x00080000U
<> 144:ef7eb2e8f9f7 5600 #define RCC_APB1RSTR_UART5RST 0x00100000U
<> 144:ef7eb2e8f9f7 5601 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 144:ef7eb2e8f9f7 5602 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 144:ef7eb2e8f9f7 5603 #define RCC_APB1RSTR_I2C3RST 0x00800000U
<> 144:ef7eb2e8f9f7 5604 #define RCC_APB1RSTR_I2C4RST 0x01000000U
<> 144:ef7eb2e8f9f7 5605 #define RCC_APB1RSTR_CAN1RST 0x02000000U
<> 144:ef7eb2e8f9f7 5606 #define RCC_APB1RSTR_CAN2RST 0x04000000U
<> 144:ef7eb2e8f9f7 5607 #define RCC_APB1RSTR_CECRST 0x08000000U
<> 144:ef7eb2e8f9f7 5608 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 144:ef7eb2e8f9f7 5609 #define RCC_APB1RSTR_DACRST 0x20000000U
<> 144:ef7eb2e8f9f7 5610 #define RCC_APB1RSTR_UART7RST 0x40000000U
<> 144:ef7eb2e8f9f7 5611 #define RCC_APB1RSTR_UART8RST 0x80000000U
mbed_official 74:9322579e4309 5612
mbed_official 74:9322579e4309 5613 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 144:ef7eb2e8f9f7 5614 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 144:ef7eb2e8f9f7 5615 #define RCC_APB2RSTR_TIM8RST 0x00000002U
<> 144:ef7eb2e8f9f7 5616 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 144:ef7eb2e8f9f7 5617 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 144:ef7eb2e8f9f7 5618 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 144:ef7eb2e8f9f7 5619 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
<> 144:ef7eb2e8f9f7 5620 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 144:ef7eb2e8f9f7 5621 #define RCC_APB2RSTR_SPI4RST 0x00002000U
<> 144:ef7eb2e8f9f7 5622 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 144:ef7eb2e8f9f7 5623 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 144:ef7eb2e8f9f7 5624 #define RCC_APB2RSTR_TIM10RST 0x00020000U
<> 144:ef7eb2e8f9f7 5625 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 144:ef7eb2e8f9f7 5626 #define RCC_APB2RSTR_SPI5RST 0x00100000U
<> 144:ef7eb2e8f9f7 5627 #define RCC_APB2RSTR_SPI6RST 0x00200000U
<> 144:ef7eb2e8f9f7 5628 #define RCC_APB2RSTR_SAI1RST 0x00400000U
<> 144:ef7eb2e8f9f7 5629 #define RCC_APB2RSTR_SAI2RST 0x00800000U
<> 144:ef7eb2e8f9f7 5630 #define RCC_APB2RSTR_LTDCRST 0x04000000U
mbed_official 74:9322579e4309 5631
mbed_official 74:9322579e4309 5632 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 144:ef7eb2e8f9f7 5633 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 144:ef7eb2e8f9f7 5634 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 144:ef7eb2e8f9f7 5635 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 144:ef7eb2e8f9f7 5636 #define RCC_AHB1ENR_GPIODEN 0x00000008U
<> 144:ef7eb2e8f9f7 5637 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
<> 144:ef7eb2e8f9f7 5638 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
<> 144:ef7eb2e8f9f7 5639 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
<> 144:ef7eb2e8f9f7 5640 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 144:ef7eb2e8f9f7 5641 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
<> 144:ef7eb2e8f9f7 5642 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
<> 144:ef7eb2e8f9f7 5643 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
<> 144:ef7eb2e8f9f7 5644 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 144:ef7eb2e8f9f7 5645 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
<> 144:ef7eb2e8f9f7 5646 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
<> 144:ef7eb2e8f9f7 5647 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 144:ef7eb2e8f9f7 5648 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 144:ef7eb2e8f9f7 5649 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
<> 144:ef7eb2e8f9f7 5650 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
<> 144:ef7eb2e8f9f7 5651 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
<> 144:ef7eb2e8f9f7 5652 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
<> 144:ef7eb2e8f9f7 5653 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5654 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
<> 144:ef7eb2e8f9f7 5655 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
mbed_official 74:9322579e4309 5656
mbed_official 74:9322579e4309 5657 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 144:ef7eb2e8f9f7 5658 #define RCC_AHB2ENR_DCMIEN 0x00000001U
<> 144:ef7eb2e8f9f7 5659 #define RCC_AHB2ENR_RNGEN 0x00000040U
<> 144:ef7eb2e8f9f7 5660 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
mbed_official 74:9322579e4309 5661
mbed_official 74:9322579e4309 5662 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 144:ef7eb2e8f9f7 5663 #define RCC_AHB3ENR_FMCEN 0x00000001U
<> 144:ef7eb2e8f9f7 5664 #define RCC_AHB3ENR_QSPIEN 0x00000002U
mbed_official 74:9322579e4309 5665
mbed_official 74:9322579e4309 5666 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 144:ef7eb2e8f9f7 5667 #define RCC_APB1ENR_TIM2EN 0x00000001U
<> 144:ef7eb2e8f9f7 5668 #define RCC_APB1ENR_TIM3EN 0x00000002U
<> 144:ef7eb2e8f9f7 5669 #define RCC_APB1ENR_TIM4EN 0x00000004U
<> 144:ef7eb2e8f9f7 5670 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 144:ef7eb2e8f9f7 5671 #define RCC_APB1ENR_TIM6EN 0x00000010U
<> 144:ef7eb2e8f9f7 5672 #define RCC_APB1ENR_TIM7EN 0x00000020U
<> 144:ef7eb2e8f9f7 5673 #define RCC_APB1ENR_TIM12EN 0x00000040U
<> 144:ef7eb2e8f9f7 5674 #define RCC_APB1ENR_TIM13EN 0x00000080U
<> 144:ef7eb2e8f9f7 5675 #define RCC_APB1ENR_TIM14EN 0x00000100U
<> 144:ef7eb2e8f9f7 5676 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
<> 144:ef7eb2e8f9f7 5677 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 144:ef7eb2e8f9f7 5678 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 144:ef7eb2e8f9f7 5679 #define RCC_APB1ENR_SPI3EN 0x00008000U
<> 144:ef7eb2e8f9f7 5680 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
<> 144:ef7eb2e8f9f7 5681 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 144:ef7eb2e8f9f7 5682 #define RCC_APB1ENR_USART3EN 0x00040000U
<> 144:ef7eb2e8f9f7 5683 #define RCC_APB1ENR_UART4EN 0x00080000U
<> 144:ef7eb2e8f9f7 5684 #define RCC_APB1ENR_UART5EN 0x00100000U
<> 144:ef7eb2e8f9f7 5685 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 144:ef7eb2e8f9f7 5686 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 144:ef7eb2e8f9f7 5687 #define RCC_APB1ENR_I2C3EN 0x00800000U
<> 144:ef7eb2e8f9f7 5688 #define RCC_APB1ENR_I2C4EN 0x01000000U
<> 144:ef7eb2e8f9f7 5689 #define RCC_APB1ENR_CAN1EN 0x02000000U
<> 144:ef7eb2e8f9f7 5690 #define RCC_APB1ENR_CAN2EN 0x04000000U
<> 144:ef7eb2e8f9f7 5691 #define RCC_APB1ENR_CECEN 0x08000000U
<> 144:ef7eb2e8f9f7 5692 #define RCC_APB1ENR_PWREN 0x10000000U
<> 144:ef7eb2e8f9f7 5693 #define RCC_APB1ENR_DACEN 0x20000000U
<> 144:ef7eb2e8f9f7 5694 #define RCC_APB1ENR_UART7EN 0x40000000U
<> 144:ef7eb2e8f9f7 5695 #define RCC_APB1ENR_UART8EN 0x80000000U
mbed_official 74:9322579e4309 5696
mbed_official 74:9322579e4309 5697 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 144:ef7eb2e8f9f7 5698 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 144:ef7eb2e8f9f7 5699 #define RCC_APB2ENR_TIM8EN 0x00000002U
<> 144:ef7eb2e8f9f7 5700 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 144:ef7eb2e8f9f7 5701 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 144:ef7eb2e8f9f7 5702 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 144:ef7eb2e8f9f7 5703 #define RCC_APB2ENR_ADC2EN 0x00000200U
<> 144:ef7eb2e8f9f7 5704 #define RCC_APB2ENR_ADC3EN 0x00000400U
<> 144:ef7eb2e8f9f7 5705 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
<> 144:ef7eb2e8f9f7 5706 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 144:ef7eb2e8f9f7 5707 #define RCC_APB2ENR_SPI4EN 0x00002000U
<> 144:ef7eb2e8f9f7 5708 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 144:ef7eb2e8f9f7 5709 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 144:ef7eb2e8f9f7 5710 #define RCC_APB2ENR_TIM10EN 0x00020000U
<> 144:ef7eb2e8f9f7 5711 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 144:ef7eb2e8f9f7 5712 #define RCC_APB2ENR_SPI5EN 0x00100000U
<> 144:ef7eb2e8f9f7 5713 #define RCC_APB2ENR_SPI6EN 0x00200000U
<> 144:ef7eb2e8f9f7 5714 #define RCC_APB2ENR_SAI1EN 0x00400000U
<> 144:ef7eb2e8f9f7 5715 #define RCC_APB2ENR_SAI2EN 0x00800000U
<> 144:ef7eb2e8f9f7 5716 #define RCC_APB2ENR_LTDCEN 0x04000000U
mbed_official 74:9322579e4309 5717
mbed_official 74:9322579e4309 5718 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 144:ef7eb2e8f9f7 5719 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5720 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5721 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 144:ef7eb2e8f9f7 5722 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
<> 144:ef7eb2e8f9f7 5723 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5724 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5725 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5726 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 144:ef7eb2e8f9f7 5727 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5728 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
<> 144:ef7eb2e8f9f7 5729 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
<> 144:ef7eb2e8f9f7 5730 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 144:ef7eb2e8f9f7 5731 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
<> 144:ef7eb2e8f9f7 5732 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 144:ef7eb2e8f9f7 5733 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 5734 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5735 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5736 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
<> 144:ef7eb2e8f9f7 5737 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 5738 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 5739 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
<> 144:ef7eb2e8f9f7 5740 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
<> 144:ef7eb2e8f9f7 5741 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
<> 144:ef7eb2e8f9f7 5742 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
<> 144:ef7eb2e8f9f7 5743 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5744 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
<> 144:ef7eb2e8f9f7 5745 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
mbed_official 74:9322579e4309 5746
mbed_official 74:9322579e4309 5747 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 144:ef7eb2e8f9f7 5748 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5749 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5750 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
mbed_official 74:9322579e4309 5751
mbed_official 74:9322579e4309 5752 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 144:ef7eb2e8f9f7 5753 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5754 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
mbed_official 74:9322579e4309 5755 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 144:ef7eb2e8f9f7 5756 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5757 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5758 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
<> 144:ef7eb2e8f9f7 5759 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 144:ef7eb2e8f9f7 5760 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5761 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5762 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
<> 144:ef7eb2e8f9f7 5763 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
<> 144:ef7eb2e8f9f7 5764 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5765 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
<> 144:ef7eb2e8f9f7 5766 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 144:ef7eb2e8f9f7 5767 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 144:ef7eb2e8f9f7 5768 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
<> 144:ef7eb2e8f9f7 5769 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
<> 144:ef7eb2e8f9f7 5770 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5771 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5772 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
<> 144:ef7eb2e8f9f7 5773 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
<> 144:ef7eb2e8f9f7 5774 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 5775 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 5776 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
<> 144:ef7eb2e8f9f7 5777 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
<> 144:ef7eb2e8f9f7 5778 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
<> 144:ef7eb2e8f9f7 5779 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
<> 144:ef7eb2e8f9f7 5780 #define RCC_APB1LPENR_CECLPEN 0x08000000U
<> 144:ef7eb2e8f9f7 5781 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 144:ef7eb2e8f9f7 5782 #define RCC_APB1LPENR_DACLPEN 0x20000000U
<> 144:ef7eb2e8f9f7 5783 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
<> 144:ef7eb2e8f9f7 5784 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
mbed_official 74:9322579e4309 5785
mbed_official 74:9322579e4309 5786 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 144:ef7eb2e8f9f7 5787 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 144:ef7eb2e8f9f7 5788 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
<> 144:ef7eb2e8f9f7 5789 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 144:ef7eb2e8f9f7 5790 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 144:ef7eb2e8f9f7 5791 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 144:ef7eb2e8f9f7 5792 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
<> 144:ef7eb2e8f9f7 5793 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
<> 144:ef7eb2e8f9f7 5794 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
<> 144:ef7eb2e8f9f7 5795 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 144:ef7eb2e8f9f7 5796 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
<> 144:ef7eb2e8f9f7 5797 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 144:ef7eb2e8f9f7 5798 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 144:ef7eb2e8f9f7 5799 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
<> 144:ef7eb2e8f9f7 5800 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 144:ef7eb2e8f9f7 5801 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
<> 144:ef7eb2e8f9f7 5802 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
<> 144:ef7eb2e8f9f7 5803 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
<> 144:ef7eb2e8f9f7 5804 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
<> 144:ef7eb2e8f9f7 5805 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
mbed_official 74:9322579e4309 5806
mbed_official 74:9322579e4309 5807 /******************** Bit definition for RCC_BDCR register ******************/
<> 144:ef7eb2e8f9f7 5808 #define RCC_BDCR_LSEON 0x00000001U
<> 144:ef7eb2e8f9f7 5809 #define RCC_BDCR_LSERDY 0x00000002U
<> 144:ef7eb2e8f9f7 5810 #define RCC_BDCR_LSEBYP 0x00000004U
<> 144:ef7eb2e8f9f7 5811 #define RCC_BDCR_LSEDRV 0x00000018U
<> 144:ef7eb2e8f9f7 5812 #define RCC_BDCR_LSEDRV_0 0x00000008U
<> 144:ef7eb2e8f9f7 5813 #define RCC_BDCR_LSEDRV_1 0x00000010U
<> 144:ef7eb2e8f9f7 5814 #define RCC_BDCR_RTCSEL 0x00000300U
<> 144:ef7eb2e8f9f7 5815 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 144:ef7eb2e8f9f7 5816 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 144:ef7eb2e8f9f7 5817 #define RCC_BDCR_RTCEN 0x00008000U
<> 144:ef7eb2e8f9f7 5818 #define RCC_BDCR_BDRST 0x00010000U
mbed_official 74:9322579e4309 5819
mbed_official 74:9322579e4309 5820 /******************** Bit definition for RCC_CSR register *******************/
<> 144:ef7eb2e8f9f7 5821 #define RCC_CSR_LSION 0x00000001U
<> 144:ef7eb2e8f9f7 5822 #define RCC_CSR_LSIRDY 0x00000002U
<> 144:ef7eb2e8f9f7 5823 #define RCC_CSR_RMVF 0x01000000U
<> 144:ef7eb2e8f9f7 5824 #define RCC_CSR_BORRSTF 0x02000000U
<> 144:ef7eb2e8f9f7 5825 #define RCC_CSR_PINRSTF 0x04000000U
<> 144:ef7eb2e8f9f7 5826 #define RCC_CSR_PORRSTF 0x08000000U
<> 144:ef7eb2e8f9f7 5827 #define RCC_CSR_SFTRSTF 0x10000000U
<> 144:ef7eb2e8f9f7 5828 #define RCC_CSR_IWDGRSTF 0x20000000U
<> 144:ef7eb2e8f9f7 5829 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 144:ef7eb2e8f9f7 5830 #define RCC_CSR_LPWRRSTF 0x80000000U
mbed_official 74:9322579e4309 5831
mbed_official 74:9322579e4309 5832 /******************** Bit definition for RCC_SSCGR register *****************/
<> 144:ef7eb2e8f9f7 5833 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 144:ef7eb2e8f9f7 5834 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 144:ef7eb2e8f9f7 5835 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 144:ef7eb2e8f9f7 5836 #define RCC_SSCGR_SSCGEN 0x80000000U
mbed_official 74:9322579e4309 5837
mbed_official 74:9322579e4309 5838 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 144:ef7eb2e8f9f7 5839 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
<> 144:ef7eb2e8f9f7 5840 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
<> 144:ef7eb2e8f9f7 5841 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
<> 144:ef7eb2e8f9f7 5842 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
<> 144:ef7eb2e8f9f7 5843 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
<> 144:ef7eb2e8f9f7 5844 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
<> 144:ef7eb2e8f9f7 5845 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
<> 144:ef7eb2e8f9f7 5846 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
<> 144:ef7eb2e8f9f7 5847 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
<> 144:ef7eb2e8f9f7 5848 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
<> 144:ef7eb2e8f9f7 5849 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
<> 144:ef7eb2e8f9f7 5850 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
<> 144:ef7eb2e8f9f7 5851 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
<> 144:ef7eb2e8f9f7 5852 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
<> 144:ef7eb2e8f9f7 5853 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 5854 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 5855 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 5856 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
<> 144:ef7eb2e8f9f7 5857 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
<> 144:ef7eb2e8f9f7 5858 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
<> 144:ef7eb2e8f9f7 5859 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
<> 144:ef7eb2e8f9f7 5860 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
mbed_official 74:9322579e4309 5861
mbed_official 74:9322579e4309 5862 /******************** Bit definition for RCC_PLLSAICFGR register ************/
<> 144:ef7eb2e8f9f7 5863 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
<> 144:ef7eb2e8f9f7 5864 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
<> 144:ef7eb2e8f9f7 5865 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
<> 144:ef7eb2e8f9f7 5866 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
<> 144:ef7eb2e8f9f7 5867 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
<> 144:ef7eb2e8f9f7 5868 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
<> 144:ef7eb2e8f9f7 5869 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
<> 144:ef7eb2e8f9f7 5870 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
<> 144:ef7eb2e8f9f7 5871 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
<> 144:ef7eb2e8f9f7 5872 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
<> 144:ef7eb2e8f9f7 5873 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
<> 144:ef7eb2e8f9f7 5874 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
<> 144:ef7eb2e8f9f7 5875 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
<> 144:ef7eb2e8f9f7 5876 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
<> 144:ef7eb2e8f9f7 5877 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
<> 144:ef7eb2e8f9f7 5878 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
<> 144:ef7eb2e8f9f7 5879 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
<> 144:ef7eb2e8f9f7 5880 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
<> 144:ef7eb2e8f9f7 5881 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
<> 144:ef7eb2e8f9f7 5882 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
<> 144:ef7eb2e8f9f7 5883 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
<> 144:ef7eb2e8f9f7 5884 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
mbed_official 74:9322579e4309 5885
mbed_official 74:9322579e4309 5886 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
<> 144:ef7eb2e8f9f7 5887 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
<> 144:ef7eb2e8f9f7 5888 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
<> 144:ef7eb2e8f9f7 5889 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
<> 144:ef7eb2e8f9f7 5890 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
<> 144:ef7eb2e8f9f7 5891 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
<> 144:ef7eb2e8f9f7 5892 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
<> 144:ef7eb2e8f9f7 5893
<> 144:ef7eb2e8f9f7 5894 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
<> 144:ef7eb2e8f9f7 5895 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
<> 144:ef7eb2e8f9f7 5896 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
<> 144:ef7eb2e8f9f7 5897 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
<> 144:ef7eb2e8f9f7 5898 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
<> 144:ef7eb2e8f9f7 5899 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
<> 144:ef7eb2e8f9f7 5900
<> 144:ef7eb2e8f9f7 5901 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
<> 144:ef7eb2e8f9f7 5902 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
<> 144:ef7eb2e8f9f7 5903 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
<> 144:ef7eb2e8f9f7 5904
<> 144:ef7eb2e8f9f7 5905 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
<> 144:ef7eb2e8f9f7 5906 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
<> 144:ef7eb2e8f9f7 5907 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
<> 144:ef7eb2e8f9f7 5908
<> 144:ef7eb2e8f9f7 5909 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
<> 144:ef7eb2e8f9f7 5910 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
<> 144:ef7eb2e8f9f7 5911 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
<> 144:ef7eb2e8f9f7 5912
<> 144:ef7eb2e8f9f7 5913 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
mbed_official 74:9322579e4309 5914
mbed_official 74:9322579e4309 5915 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
<> 144:ef7eb2e8f9f7 5916 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
<> 144:ef7eb2e8f9f7 5917 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
<> 144:ef7eb2e8f9f7 5918 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
<> 144:ef7eb2e8f9f7 5919 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
<> 144:ef7eb2e8f9f7 5920 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
<> 144:ef7eb2e8f9f7 5921 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
<> 144:ef7eb2e8f9f7 5922 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
<> 144:ef7eb2e8f9f7 5923 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
<> 144:ef7eb2e8f9f7 5924 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
<> 144:ef7eb2e8f9f7 5925 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
<> 144:ef7eb2e8f9f7 5926 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
<> 144:ef7eb2e8f9f7 5927 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
<> 144:ef7eb2e8f9f7 5928 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
<> 144:ef7eb2e8f9f7 5929 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
<> 144:ef7eb2e8f9f7 5930 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
<> 144:ef7eb2e8f9f7 5931 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
<> 144:ef7eb2e8f9f7 5932 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
<> 144:ef7eb2e8f9f7 5933 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
<> 144:ef7eb2e8f9f7 5934 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
<> 144:ef7eb2e8f9f7 5935 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
<> 144:ef7eb2e8f9f7 5936 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
<> 144:ef7eb2e8f9f7 5937 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
<> 144:ef7eb2e8f9f7 5938 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
<> 144:ef7eb2e8f9f7 5939 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
<> 144:ef7eb2e8f9f7 5940 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
<> 144:ef7eb2e8f9f7 5941 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
<> 144:ef7eb2e8f9f7 5942 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
<> 144:ef7eb2e8f9f7 5943 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
<> 144:ef7eb2e8f9f7 5944 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
<> 144:ef7eb2e8f9f7 5945 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
<> 144:ef7eb2e8f9f7 5946 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
<> 144:ef7eb2e8f9f7 5947 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
<> 144:ef7eb2e8f9f7 5948 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
<> 144:ef7eb2e8f9f7 5949 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
<> 144:ef7eb2e8f9f7 5950 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
<> 144:ef7eb2e8f9f7 5951 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
<> 144:ef7eb2e8f9f7 5952 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
<> 144:ef7eb2e8f9f7 5953 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
<> 144:ef7eb2e8f9f7 5954 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
<> 144:ef7eb2e8f9f7 5955 #define RCC_DCKCFGR2_CECSEL 0x04000000U
<> 144:ef7eb2e8f9f7 5956 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
<> 144:ef7eb2e8f9f7 5957 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
mbed_official 74:9322579e4309 5958
mbed_official 74:9322579e4309 5959 /******************************************************************************/
mbed_official 74:9322579e4309 5960 /* */
mbed_official 74:9322579e4309 5961 /* RNG */
mbed_official 74:9322579e4309 5962 /* */
mbed_official 74:9322579e4309 5963 /******************************************************************************/
mbed_official 74:9322579e4309 5964 /******************** Bits definition for RNG_CR register *******************/
<> 144:ef7eb2e8f9f7 5965 #define RNG_CR_RNGEN 0x00000004U
<> 144:ef7eb2e8f9f7 5966 #define RNG_CR_IE 0x00000008U
mbed_official 74:9322579e4309 5967
mbed_official 74:9322579e4309 5968 /******************** Bits definition for RNG_SR register *******************/
<> 144:ef7eb2e8f9f7 5969 #define RNG_SR_DRDY 0x00000001U
<> 144:ef7eb2e8f9f7 5970 #define RNG_SR_CECS 0x00000002U
<> 144:ef7eb2e8f9f7 5971 #define RNG_SR_SECS 0x00000004U
<> 144:ef7eb2e8f9f7 5972 #define RNG_SR_CEIS 0x00000020U
<> 144:ef7eb2e8f9f7 5973 #define RNG_SR_SEIS 0x00000040U
mbed_official 74:9322579e4309 5974
mbed_official 74:9322579e4309 5975 /******************************************************************************/
mbed_official 74:9322579e4309 5976 /* */
mbed_official 74:9322579e4309 5977 /* Real-Time Clock (RTC) */
mbed_official 74:9322579e4309 5978 /* */
mbed_official 74:9322579e4309 5979 /******************************************************************************/
mbed_official 74:9322579e4309 5980 /******************** Bits definition for RTC_TR register *******************/
<> 144:ef7eb2e8f9f7 5981 #define RTC_TR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 5982 #define RTC_TR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 5983 #define RTC_TR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 5984 #define RTC_TR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 5985 #define RTC_TR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 5986 #define RTC_TR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 5987 #define RTC_TR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 5988 #define RTC_TR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 5989 #define RTC_TR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 5990 #define RTC_TR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 5991 #define RTC_TR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 5992 #define RTC_TR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 5993 #define RTC_TR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 5994 #define RTC_TR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 5995 #define RTC_TR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 5996 #define RTC_TR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 5997 #define RTC_TR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 5998 #define RTC_TR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 5999 #define RTC_TR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 6000 #define RTC_TR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 6001 #define RTC_TR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 6002 #define RTC_TR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 6003 #define RTC_TR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 6004 #define RTC_TR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6005 #define RTC_TR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6006 #define RTC_TR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6007 #define RTC_TR_SU_3 0x00000008U
mbed_official 74:9322579e4309 6008
mbed_official 74:9322579e4309 6009 /******************** Bits definition for RTC_DR register *******************/
<> 144:ef7eb2e8f9f7 6010 #define RTC_DR_YT 0x00F00000U
<> 144:ef7eb2e8f9f7 6011 #define RTC_DR_YT_0 0x00100000U
<> 144:ef7eb2e8f9f7 6012 #define RTC_DR_YT_1 0x00200000U
<> 144:ef7eb2e8f9f7 6013 #define RTC_DR_YT_2 0x00400000U
<> 144:ef7eb2e8f9f7 6014 #define RTC_DR_YT_3 0x00800000U
<> 144:ef7eb2e8f9f7 6015 #define RTC_DR_YU 0x000F0000U
<> 144:ef7eb2e8f9f7 6016 #define RTC_DR_YU_0 0x00010000U
<> 144:ef7eb2e8f9f7 6017 #define RTC_DR_YU_1 0x00020000U
<> 144:ef7eb2e8f9f7 6018 #define RTC_DR_YU_2 0x00040000U
<> 144:ef7eb2e8f9f7 6019 #define RTC_DR_YU_3 0x00080000U
<> 144:ef7eb2e8f9f7 6020 #define RTC_DR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 6021 #define RTC_DR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 6022 #define RTC_DR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 6023 #define RTC_DR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 6024 #define RTC_DR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 6025 #define RTC_DR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 6026 #define RTC_DR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 6027 #define RTC_DR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 6028 #define RTC_DR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 6029 #define RTC_DR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 6030 #define RTC_DR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 6031 #define RTC_DR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 6032 #define RTC_DR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 6033 #define RTC_DR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 6034 #define RTC_DR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6035 #define RTC_DR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6036 #define RTC_DR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6037 #define RTC_DR_DU_3 0x00000008U
mbed_official 74:9322579e4309 6038
mbed_official 74:9322579e4309 6039 /******************** Bits definition for RTC_CR register *******************/
<> 144:ef7eb2e8f9f7 6040 #define RTC_CR_ITSE 0x01000000U
<> 144:ef7eb2e8f9f7 6041 #define RTC_CR_COE 0x00800000U
<> 144:ef7eb2e8f9f7 6042 #define RTC_CR_OSEL 0x00600000U
<> 144:ef7eb2e8f9f7 6043 #define RTC_CR_OSEL_0 0x00200000U
<> 144:ef7eb2e8f9f7 6044 #define RTC_CR_OSEL_1 0x00400000U
<> 144:ef7eb2e8f9f7 6045 #define RTC_CR_POL 0x00100000U
<> 144:ef7eb2e8f9f7 6046 #define RTC_CR_COSEL 0x00080000U
<> 144:ef7eb2e8f9f7 6047 #define RTC_CR_BCK 0x00040000U
<> 144:ef7eb2e8f9f7 6048 #define RTC_CR_SUB1H 0x00020000U
<> 144:ef7eb2e8f9f7 6049 #define RTC_CR_ADD1H 0x00010000U
<> 144:ef7eb2e8f9f7 6050 #define RTC_CR_TSIE 0x00008000U
<> 144:ef7eb2e8f9f7 6051 #define RTC_CR_WUTIE 0x00004000U
<> 144:ef7eb2e8f9f7 6052 #define RTC_CR_ALRBIE 0x00002000U
<> 144:ef7eb2e8f9f7 6053 #define RTC_CR_ALRAIE 0x00001000U
<> 144:ef7eb2e8f9f7 6054 #define RTC_CR_TSE 0x00000800U
<> 144:ef7eb2e8f9f7 6055 #define RTC_CR_WUTE 0x00000400U
<> 144:ef7eb2e8f9f7 6056 #define RTC_CR_ALRBE 0x00000200U
<> 144:ef7eb2e8f9f7 6057 #define RTC_CR_ALRAE 0x00000100U
<> 144:ef7eb2e8f9f7 6058 #define RTC_CR_FMT 0x00000040U
<> 144:ef7eb2e8f9f7 6059 #define RTC_CR_BYPSHAD 0x00000020U
<> 144:ef7eb2e8f9f7 6060 #define RTC_CR_REFCKON 0x00000010U
<> 144:ef7eb2e8f9f7 6061 #define RTC_CR_TSEDGE 0x00000008U
<> 144:ef7eb2e8f9f7 6062 #define RTC_CR_WUCKSEL 0x00000007U
<> 144:ef7eb2e8f9f7 6063 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 144:ef7eb2e8f9f7 6064 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 144:ef7eb2e8f9f7 6065 #define RTC_CR_WUCKSEL_2 0x00000004U
mbed_official 74:9322579e4309 6066
mbed_official 74:9322579e4309 6067 /******************** Bits definition for RTC_ISR register ******************/
<> 144:ef7eb2e8f9f7 6068 #define RTC_ISR_ITSF 0x00020000U
<> 144:ef7eb2e8f9f7 6069 #define RTC_ISR_RECALPF 0x00010000U
<> 144:ef7eb2e8f9f7 6070 #define RTC_ISR_TAMP3F 0x00008000U
<> 144:ef7eb2e8f9f7 6071 #define RTC_ISR_TAMP2F 0x00004000U
<> 144:ef7eb2e8f9f7 6072 #define RTC_ISR_TAMP1F 0x00002000U
<> 144:ef7eb2e8f9f7 6073 #define RTC_ISR_TSOVF 0x00001000U
<> 144:ef7eb2e8f9f7 6074 #define RTC_ISR_TSF 0x00000800U
<> 144:ef7eb2e8f9f7 6075 #define RTC_ISR_WUTF 0x00000400U
<> 144:ef7eb2e8f9f7 6076 #define RTC_ISR_ALRBF 0x00000200U
<> 144:ef7eb2e8f9f7 6077 #define RTC_ISR_ALRAF 0x00000100U
<> 144:ef7eb2e8f9f7 6078 #define RTC_ISR_INIT 0x00000080U
<> 144:ef7eb2e8f9f7 6079 #define RTC_ISR_INITF 0x00000040U
<> 144:ef7eb2e8f9f7 6080 #define RTC_ISR_RSF 0x00000020U
<> 144:ef7eb2e8f9f7 6081 #define RTC_ISR_INITS 0x00000010U
<> 144:ef7eb2e8f9f7 6082 #define RTC_ISR_SHPF 0x00000008U
<> 144:ef7eb2e8f9f7 6083 #define RTC_ISR_WUTWF 0x00000004U
<> 144:ef7eb2e8f9f7 6084 #define RTC_ISR_ALRBWF 0x00000002U
<> 144:ef7eb2e8f9f7 6085 #define RTC_ISR_ALRAWF 0x00000001U
mbed_official 74:9322579e4309 6086
mbed_official 74:9322579e4309 6087 /******************** Bits definition for RTC_PRER register *****************/
<> 144:ef7eb2e8f9f7 6088 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 144:ef7eb2e8f9f7 6089 #define RTC_PRER_PREDIV_S 0x00007FFFU
mbed_official 74:9322579e4309 6090
mbed_official 74:9322579e4309 6091 /******************** Bits definition for RTC_WUTR register *****************/
<> 144:ef7eb2e8f9f7 6092 #define RTC_WUTR_WUT 0x0000FFFFU
mbed_official 74:9322579e4309 6093
mbed_official 74:9322579e4309 6094 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 144:ef7eb2e8f9f7 6095 #define RTC_ALRMAR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 6096 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 6097 #define RTC_ALRMAR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 6098 #define RTC_ALRMAR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 6099 #define RTC_ALRMAR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 6100 #define RTC_ALRMAR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 6101 #define RTC_ALRMAR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 6102 #define RTC_ALRMAR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 6103 #define RTC_ALRMAR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 6104 #define RTC_ALRMAR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 6105 #define RTC_ALRMAR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 6106 #define RTC_ALRMAR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 6107 #define RTC_ALRMAR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 6108 #define RTC_ALRMAR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 6109 #define RTC_ALRMAR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 6110 #define RTC_ALRMAR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 6111 #define RTC_ALRMAR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 6112 #define RTC_ALRMAR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 6113 #define RTC_ALRMAR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 6114 #define RTC_ALRMAR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 6115 #define RTC_ALRMAR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 6116 #define RTC_ALRMAR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 6117 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 6118 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 6119 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 6120 #define RTC_ALRMAR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 6121 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 6122 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 6123 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 6124 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 6125 #define RTC_ALRMAR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 6126 #define RTC_ALRMAR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 6127 #define RTC_ALRMAR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 6128 #define RTC_ALRMAR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 6129 #define RTC_ALRMAR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 6130 #define RTC_ALRMAR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 6131 #define RTC_ALRMAR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6132 #define RTC_ALRMAR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6133 #define RTC_ALRMAR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6134 #define RTC_ALRMAR_SU_3 0x00000008U
mbed_official 74:9322579e4309 6135
mbed_official 74:9322579e4309 6136 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 144:ef7eb2e8f9f7 6137 #define RTC_ALRMBR_MSK4 0x80000000U
<> 144:ef7eb2e8f9f7 6138 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 144:ef7eb2e8f9f7 6139 #define RTC_ALRMBR_DT 0x30000000U
<> 144:ef7eb2e8f9f7 6140 #define RTC_ALRMBR_DT_0 0x10000000U
<> 144:ef7eb2e8f9f7 6141 #define RTC_ALRMBR_DT_1 0x20000000U
<> 144:ef7eb2e8f9f7 6142 #define RTC_ALRMBR_DU 0x0F000000U
<> 144:ef7eb2e8f9f7 6143 #define RTC_ALRMBR_DU_0 0x01000000U
<> 144:ef7eb2e8f9f7 6144 #define RTC_ALRMBR_DU_1 0x02000000U
<> 144:ef7eb2e8f9f7 6145 #define RTC_ALRMBR_DU_2 0x04000000U
<> 144:ef7eb2e8f9f7 6146 #define RTC_ALRMBR_DU_3 0x08000000U
<> 144:ef7eb2e8f9f7 6147 #define RTC_ALRMBR_MSK3 0x00800000U
<> 144:ef7eb2e8f9f7 6148 #define RTC_ALRMBR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 6149 #define RTC_ALRMBR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 6150 #define RTC_ALRMBR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 6151 #define RTC_ALRMBR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 6152 #define RTC_ALRMBR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 6153 #define RTC_ALRMBR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 6154 #define RTC_ALRMBR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 6155 #define RTC_ALRMBR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 6156 #define RTC_ALRMBR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 6157 #define RTC_ALRMBR_MSK2 0x00008000U
<> 144:ef7eb2e8f9f7 6158 #define RTC_ALRMBR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 6159 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 6160 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 6161 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 6162 #define RTC_ALRMBR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 6163 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 6164 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 6165 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 6166 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 6167 #define RTC_ALRMBR_MSK1 0x00000080U
<> 144:ef7eb2e8f9f7 6168 #define RTC_ALRMBR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 6169 #define RTC_ALRMBR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 6170 #define RTC_ALRMBR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 6171 #define RTC_ALRMBR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 6172 #define RTC_ALRMBR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 6173 #define RTC_ALRMBR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6174 #define RTC_ALRMBR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6175 #define RTC_ALRMBR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6176 #define RTC_ALRMBR_SU_3 0x00000008U
mbed_official 74:9322579e4309 6177
mbed_official 74:9322579e4309 6178 /******************** Bits definition for RTC_WPR register ******************/
<> 144:ef7eb2e8f9f7 6179 #define RTC_WPR_KEY 0x000000FFU
mbed_official 74:9322579e4309 6180
mbed_official 74:9322579e4309 6181 /******************** Bits definition for RTC_SSR register ******************/
<> 144:ef7eb2e8f9f7 6182 #define RTC_SSR_SS 0x0000FFFFU
mbed_official 74:9322579e4309 6183
mbed_official 74:9322579e4309 6184 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 144:ef7eb2e8f9f7 6185 #define RTC_SHIFTR_SUBFS 0x00007FFFU
<> 144:ef7eb2e8f9f7 6186 #define RTC_SHIFTR_ADD1S 0x80000000U
mbed_official 74:9322579e4309 6187
mbed_official 74:9322579e4309 6188 /******************** Bits definition for RTC_TSTR register *****************/
<> 144:ef7eb2e8f9f7 6189 #define RTC_TSTR_PM 0x00400000U
<> 144:ef7eb2e8f9f7 6190 #define RTC_TSTR_HT 0x00300000U
<> 144:ef7eb2e8f9f7 6191 #define RTC_TSTR_HT_0 0x00100000U
<> 144:ef7eb2e8f9f7 6192 #define RTC_TSTR_HT_1 0x00200000U
<> 144:ef7eb2e8f9f7 6193 #define RTC_TSTR_HU 0x000F0000U
<> 144:ef7eb2e8f9f7 6194 #define RTC_TSTR_HU_0 0x00010000U
<> 144:ef7eb2e8f9f7 6195 #define RTC_TSTR_HU_1 0x00020000U
<> 144:ef7eb2e8f9f7 6196 #define RTC_TSTR_HU_2 0x00040000U
<> 144:ef7eb2e8f9f7 6197 #define RTC_TSTR_HU_3 0x00080000U
<> 144:ef7eb2e8f9f7 6198 #define RTC_TSTR_MNT 0x00007000U
<> 144:ef7eb2e8f9f7 6199 #define RTC_TSTR_MNT_0 0x00001000U
<> 144:ef7eb2e8f9f7 6200 #define RTC_TSTR_MNT_1 0x00002000U
<> 144:ef7eb2e8f9f7 6201 #define RTC_TSTR_MNT_2 0x00004000U
<> 144:ef7eb2e8f9f7 6202 #define RTC_TSTR_MNU 0x00000F00U
<> 144:ef7eb2e8f9f7 6203 #define RTC_TSTR_MNU_0 0x00000100U
<> 144:ef7eb2e8f9f7 6204 #define RTC_TSTR_MNU_1 0x00000200U
<> 144:ef7eb2e8f9f7 6205 #define RTC_TSTR_MNU_2 0x00000400U
<> 144:ef7eb2e8f9f7 6206 #define RTC_TSTR_MNU_3 0x00000800U
<> 144:ef7eb2e8f9f7 6207 #define RTC_TSTR_ST 0x00000070U
<> 144:ef7eb2e8f9f7 6208 #define RTC_TSTR_ST_0 0x00000010U
<> 144:ef7eb2e8f9f7 6209 #define RTC_TSTR_ST_1 0x00000020U
<> 144:ef7eb2e8f9f7 6210 #define RTC_TSTR_ST_2 0x00000040U
<> 144:ef7eb2e8f9f7 6211 #define RTC_TSTR_SU 0x0000000FU
<> 144:ef7eb2e8f9f7 6212 #define RTC_TSTR_SU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6213 #define RTC_TSTR_SU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6214 #define RTC_TSTR_SU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6215 #define RTC_TSTR_SU_3 0x00000008U
mbed_official 74:9322579e4309 6216
mbed_official 74:9322579e4309 6217 /******************** Bits definition for RTC_TSDR register *****************/
<> 144:ef7eb2e8f9f7 6218 #define RTC_TSDR_WDU 0x0000E000U
<> 144:ef7eb2e8f9f7 6219 #define RTC_TSDR_WDU_0 0x00002000U
<> 144:ef7eb2e8f9f7 6220 #define RTC_TSDR_WDU_1 0x00004000U
<> 144:ef7eb2e8f9f7 6221 #define RTC_TSDR_WDU_2 0x00008000U
<> 144:ef7eb2e8f9f7 6222 #define RTC_TSDR_MT 0x00001000U
<> 144:ef7eb2e8f9f7 6223 #define RTC_TSDR_MU 0x00000F00U
<> 144:ef7eb2e8f9f7 6224 #define RTC_TSDR_MU_0 0x00000100U
<> 144:ef7eb2e8f9f7 6225 #define RTC_TSDR_MU_1 0x00000200U
<> 144:ef7eb2e8f9f7 6226 #define RTC_TSDR_MU_2 0x00000400U
<> 144:ef7eb2e8f9f7 6227 #define RTC_TSDR_MU_3 0x00000800U
<> 144:ef7eb2e8f9f7 6228 #define RTC_TSDR_DT 0x00000030U
<> 144:ef7eb2e8f9f7 6229 #define RTC_TSDR_DT_0 0x00000010U
<> 144:ef7eb2e8f9f7 6230 #define RTC_TSDR_DT_1 0x00000020U
<> 144:ef7eb2e8f9f7 6231 #define RTC_TSDR_DU 0x0000000FU
<> 144:ef7eb2e8f9f7 6232 #define RTC_TSDR_DU_0 0x00000001U
<> 144:ef7eb2e8f9f7 6233 #define RTC_TSDR_DU_1 0x00000002U
<> 144:ef7eb2e8f9f7 6234 #define RTC_TSDR_DU_2 0x00000004U
<> 144:ef7eb2e8f9f7 6235 #define RTC_TSDR_DU_3 0x00000008U
mbed_official 74:9322579e4309 6236
mbed_official 74:9322579e4309 6237 /******************** Bits definition for RTC_TSSSR register ****************/
<> 144:ef7eb2e8f9f7 6238 #define RTC_TSSSR_SS 0x0000FFFFU
mbed_official 74:9322579e4309 6239
mbed_official 74:9322579e4309 6240 /******************** Bits definition for RTC_CAL register *****************/
<> 144:ef7eb2e8f9f7 6241 #define RTC_CALR_CALP 0x00008000U
<> 144:ef7eb2e8f9f7 6242 #define RTC_CALR_CALW8 0x00004000U
<> 144:ef7eb2e8f9f7 6243 #define RTC_CALR_CALW16 0x00002000U
<> 144:ef7eb2e8f9f7 6244 #define RTC_CALR_CALM 0x000001FFU
<> 144:ef7eb2e8f9f7 6245 #define RTC_CALR_CALM_0 0x00000001U
<> 144:ef7eb2e8f9f7 6246 #define RTC_CALR_CALM_1 0x00000002U
<> 144:ef7eb2e8f9f7 6247 #define RTC_CALR_CALM_2 0x00000004U
<> 144:ef7eb2e8f9f7 6248 #define RTC_CALR_CALM_3 0x00000008U
<> 144:ef7eb2e8f9f7 6249 #define RTC_CALR_CALM_4 0x00000010U
<> 144:ef7eb2e8f9f7 6250 #define RTC_CALR_CALM_5 0x00000020U
<> 144:ef7eb2e8f9f7 6251 #define RTC_CALR_CALM_6 0x00000040U
<> 144:ef7eb2e8f9f7 6252 #define RTC_CALR_CALM_7 0x00000080U
<> 144:ef7eb2e8f9f7 6253 #define RTC_CALR_CALM_8 0x00000100U
mbed_official 74:9322579e4309 6254
mbed_official 74:9322579e4309 6255 /******************** Bits definition for RTC_TAMPCR register ****************/
<> 144:ef7eb2e8f9f7 6256 #define RTC_TAMPCR_TAMP3MF 0x01000000U
<> 144:ef7eb2e8f9f7 6257 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
<> 144:ef7eb2e8f9f7 6258 #define RTC_TAMPCR_TAMP3IE 0x00400000U
<> 144:ef7eb2e8f9f7 6259 #define RTC_TAMPCR_TAMP2MF 0x00200000U
<> 144:ef7eb2e8f9f7 6260 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
<> 144:ef7eb2e8f9f7 6261 #define RTC_TAMPCR_TAMP2IE 0x00080000U
<> 144:ef7eb2e8f9f7 6262 #define RTC_TAMPCR_TAMP1MF 0x00040000U
<> 144:ef7eb2e8f9f7 6263 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
<> 144:ef7eb2e8f9f7 6264 #define RTC_TAMPCR_TAMP1IE 0x00010000U
<> 144:ef7eb2e8f9f7 6265 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
<> 144:ef7eb2e8f9f7 6266 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
<> 144:ef7eb2e8f9f7 6267 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
<> 144:ef7eb2e8f9f7 6268 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
<> 144:ef7eb2e8f9f7 6269 #define RTC_TAMPCR_TAMPFLT 0x00001800U
<> 144:ef7eb2e8f9f7 6270 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
<> 144:ef7eb2e8f9f7 6271 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
<> 144:ef7eb2e8f9f7 6272 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
<> 144:ef7eb2e8f9f7 6273 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
<> 144:ef7eb2e8f9f7 6274 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
<> 144:ef7eb2e8f9f7 6275 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
<> 144:ef7eb2e8f9f7 6276 #define RTC_TAMPCR_TAMPTS 0x00000080U
<> 144:ef7eb2e8f9f7 6277 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
<> 144:ef7eb2e8f9f7 6278 #define RTC_TAMPCR_TAMP3E 0x00000020U
<> 144:ef7eb2e8f9f7 6279 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
<> 144:ef7eb2e8f9f7 6280 #define RTC_TAMPCR_TAMP2E 0x00000008U
<> 144:ef7eb2e8f9f7 6281 #define RTC_TAMPCR_TAMPIE 0x00000004U
<> 144:ef7eb2e8f9f7 6282 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
<> 144:ef7eb2e8f9f7 6283 #define RTC_TAMPCR_TAMP1E 0x00000001U
<> 144:ef7eb2e8f9f7 6284
<> 144:ef7eb2e8f9f7 6285 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6286 #define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
<> 144:ef7eb2e8f9f7 6287 #define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
<> 144:ef7eb2e8f9f7 6288 #define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
mbed_official 74:9322579e4309 6289
mbed_official 74:9322579e4309 6290 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 144:ef7eb2e8f9f7 6291 #define RTC_ALRMASSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 6292 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 6293 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 6294 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 6295 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 6296 #define RTC_ALRMASSR_SS 0x00007FFFU
mbed_official 74:9322579e4309 6297
mbed_official 74:9322579e4309 6298 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 144:ef7eb2e8f9f7 6299 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
<> 144:ef7eb2e8f9f7 6300 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
<> 144:ef7eb2e8f9f7 6301 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
<> 144:ef7eb2e8f9f7 6302 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
<> 144:ef7eb2e8f9f7 6303 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
<> 144:ef7eb2e8f9f7 6304 #define RTC_ALRMBSSR_SS 0x00007FFFU
mbed_official 74:9322579e4309 6305
mbed_official 74:9322579e4309 6306 /******************** Bits definition for RTC_OR register ****************/
<> 144:ef7eb2e8f9f7 6307 #define RTC_OR_TSINSEL 0x00000006U
<> 144:ef7eb2e8f9f7 6308 #define RTC_OR_TSINSEL_0 0x00000002U
<> 144:ef7eb2e8f9f7 6309 #define RTC_OR_TSINSEL_1 0x00000004U
<> 144:ef7eb2e8f9f7 6310 #define RTC_OR_ALARMTYPE 0x00000008U
mbed_official 74:9322579e4309 6311
mbed_official 74:9322579e4309 6312 /******************** Bits definition for RTC_BKP0R register ****************/
<> 144:ef7eb2e8f9f7 6313 #define RTC_BKP0R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6314
mbed_official 74:9322579e4309 6315 /******************** Bits definition for RTC_BKP1R register ****************/
<> 144:ef7eb2e8f9f7 6316 #define RTC_BKP1R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6317
mbed_official 74:9322579e4309 6318 /******************** Bits definition for RTC_BKP2R register ****************/
<> 144:ef7eb2e8f9f7 6319 #define RTC_BKP2R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6320
mbed_official 74:9322579e4309 6321 /******************** Bits definition for RTC_BKP3R register ****************/
<> 144:ef7eb2e8f9f7 6322 #define RTC_BKP3R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6323
mbed_official 74:9322579e4309 6324 /******************** Bits definition for RTC_BKP4R register ****************/
<> 144:ef7eb2e8f9f7 6325 #define RTC_BKP4R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6326
mbed_official 74:9322579e4309 6327 /******************** Bits definition for RTC_BKP5R register ****************/
<> 144:ef7eb2e8f9f7 6328 #define RTC_BKP5R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6329
mbed_official 74:9322579e4309 6330 /******************** Bits definition for RTC_BKP6R register ****************/
<> 144:ef7eb2e8f9f7 6331 #define RTC_BKP6R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6332
mbed_official 74:9322579e4309 6333 /******************** Bits definition for RTC_BKP7R register ****************/
<> 144:ef7eb2e8f9f7 6334 #define RTC_BKP7R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6335
mbed_official 74:9322579e4309 6336 /******************** Bits definition for RTC_BKP8R register ****************/
<> 144:ef7eb2e8f9f7 6337 #define RTC_BKP8R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6338
mbed_official 74:9322579e4309 6339 /******************** Bits definition for RTC_BKP9R register ****************/
<> 144:ef7eb2e8f9f7 6340 #define RTC_BKP9R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6341
mbed_official 74:9322579e4309 6342 /******************** Bits definition for RTC_BKP10R register ***************/
<> 144:ef7eb2e8f9f7 6343 #define RTC_BKP10R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6344
mbed_official 74:9322579e4309 6345 /******************** Bits definition for RTC_BKP11R register ***************/
<> 144:ef7eb2e8f9f7 6346 #define RTC_BKP11R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6347
mbed_official 74:9322579e4309 6348 /******************** Bits definition for RTC_BKP12R register ***************/
<> 144:ef7eb2e8f9f7 6349 #define RTC_BKP12R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6350
mbed_official 74:9322579e4309 6351 /******************** Bits definition for RTC_BKP13R register ***************/
<> 144:ef7eb2e8f9f7 6352 #define RTC_BKP13R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6353
mbed_official 74:9322579e4309 6354 /******************** Bits definition for RTC_BKP14R register ***************/
<> 144:ef7eb2e8f9f7 6355 #define RTC_BKP14R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6356
mbed_official 74:9322579e4309 6357 /******************** Bits definition for RTC_BKP15R register ***************/
<> 144:ef7eb2e8f9f7 6358 #define RTC_BKP15R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6359
mbed_official 74:9322579e4309 6360 /******************** Bits definition for RTC_BKP16R register ***************/
<> 144:ef7eb2e8f9f7 6361 #define RTC_BKP16R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6362
mbed_official 74:9322579e4309 6363 /******************** Bits definition for RTC_BKP17R register ***************/
<> 144:ef7eb2e8f9f7 6364 #define RTC_BKP17R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6365
mbed_official 74:9322579e4309 6366 /******************** Bits definition for RTC_BKP18R register ***************/
<> 144:ef7eb2e8f9f7 6367 #define RTC_BKP18R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6368
mbed_official 74:9322579e4309 6369 /******************** Bits definition for RTC_BKP19R register ***************/
<> 144:ef7eb2e8f9f7 6370 #define RTC_BKP19R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6371
mbed_official 74:9322579e4309 6372 /******************** Bits definition for RTC_BKP20R register ***************/
<> 144:ef7eb2e8f9f7 6373 #define RTC_BKP20R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6374
mbed_official 74:9322579e4309 6375 /******************** Bits definition for RTC_BKP21R register ***************/
<> 144:ef7eb2e8f9f7 6376 #define RTC_BKP21R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6377
mbed_official 74:9322579e4309 6378 /******************** Bits definition for RTC_BKP22R register ***************/
<> 144:ef7eb2e8f9f7 6379 #define RTC_BKP22R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6380
mbed_official 74:9322579e4309 6381 /******************** Bits definition for RTC_BKP23R register ***************/
<> 144:ef7eb2e8f9f7 6382 #define RTC_BKP23R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6383
mbed_official 74:9322579e4309 6384 /******************** Bits definition for RTC_BKP24R register ***************/
<> 144:ef7eb2e8f9f7 6385 #define RTC_BKP24R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6386
mbed_official 74:9322579e4309 6387 /******************** Bits definition for RTC_BKP25R register ***************/
<> 144:ef7eb2e8f9f7 6388 #define RTC_BKP25R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6389
mbed_official 74:9322579e4309 6390 /******************** Bits definition for RTC_BKP26R register ***************/
<> 144:ef7eb2e8f9f7 6391 #define RTC_BKP26R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6392
mbed_official 74:9322579e4309 6393 /******************** Bits definition for RTC_BKP27R register ***************/
<> 144:ef7eb2e8f9f7 6394 #define RTC_BKP27R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6395
mbed_official 74:9322579e4309 6396 /******************** Bits definition for RTC_BKP28R register ***************/
<> 144:ef7eb2e8f9f7 6397 #define RTC_BKP28R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6398
mbed_official 74:9322579e4309 6399 /******************** Bits definition for RTC_BKP29R register ***************/
<> 144:ef7eb2e8f9f7 6400 #define RTC_BKP29R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6401
mbed_official 74:9322579e4309 6402 /******************** Bits definition for RTC_BKP30R register ***************/
<> 144:ef7eb2e8f9f7 6403 #define RTC_BKP30R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6404
mbed_official 74:9322579e4309 6405 /******************** Bits definition for RTC_BKP31R register ***************/
<> 144:ef7eb2e8f9f7 6406 #define RTC_BKP31R 0xFFFFFFFFU
mbed_official 74:9322579e4309 6407
mbed_official 74:9322579e4309 6408 /******************** Number of backup registers ******************************/
<> 144:ef7eb2e8f9f7 6409 #define RTC_BKP_NUMBER 0x00000020U
mbed_official 74:9322579e4309 6410
mbed_official 74:9322579e4309 6411
mbed_official 74:9322579e4309 6412 /******************************************************************************/
mbed_official 74:9322579e4309 6413 /* */
mbed_official 74:9322579e4309 6414 /* Serial Audio Interface */
mbed_official 74:9322579e4309 6415 /* */
mbed_official 74:9322579e4309 6416 /******************************************************************************/
mbed_official 74:9322579e4309 6417 /******************** Bit definition for SAI_GCR register *******************/
<> 144:ef7eb2e8f9f7 6418 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
<> 144:ef7eb2e8f9f7 6419 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6420 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6421
<> 144:ef7eb2e8f9f7 6422 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
<> 144:ef7eb2e8f9f7 6423 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6424 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
mbed_official 74:9322579e4309 6425
mbed_official 74:9322579e4309 6426 /******************* Bit definition for SAI_xCR1 register *******************/
<> 144:ef7eb2e8f9f7 6427 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
<> 144:ef7eb2e8f9f7 6428 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6429 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6430
<> 144:ef7eb2e8f9f7 6431 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
<> 144:ef7eb2e8f9f7 6432 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6433 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6434
<> 144:ef7eb2e8f9f7 6435 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
<> 144:ef7eb2e8f9f7 6436 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6437 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6438 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6439
<> 144:ef7eb2e8f9f7 6440 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
<> 144:ef7eb2e8f9f7 6441 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
<> 144:ef7eb2e8f9f7 6442
<> 144:ef7eb2e8f9f7 6443 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
<> 144:ef7eb2e8f9f7 6444 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6445 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6446
<> 144:ef7eb2e8f9f7 6447 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
<> 144:ef7eb2e8f9f7 6448 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
<> 144:ef7eb2e8f9f7 6449 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
<> 144:ef7eb2e8f9f7 6450 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
<> 144:ef7eb2e8f9f7 6451 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
<> 144:ef7eb2e8f9f7 6452
<> 144:ef7eb2e8f9f7 6453 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
<> 144:ef7eb2e8f9f7 6454 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6455 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6456 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6457 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
mbed_official 74:9322579e4309 6458
mbed_official 74:9322579e4309 6459 /******************* Bit definition for SAI_xCR2 register *******************/
<> 144:ef7eb2e8f9f7 6460 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
<> 144:ef7eb2e8f9f7 6461 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6462 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6463 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6464
<> 144:ef7eb2e8f9f7 6465 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
<> 144:ef7eb2e8f9f7 6466 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
<> 144:ef7eb2e8f9f7 6467 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
<> 144:ef7eb2e8f9f7 6468 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
<> 144:ef7eb2e8f9f7 6469
<> 144:ef7eb2e8f9f7 6470 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
<> 144:ef7eb2e8f9f7 6471 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6472 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6473 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6474 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6475 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6476 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6477
<> 144:ef7eb2e8f9f7 6478 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
<> 144:ef7eb2e8f9f7 6479
<> 144:ef7eb2e8f9f7 6480 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
<> 144:ef7eb2e8f9f7 6481 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6482 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
mbed_official 74:9322579e4309 6483
mbed_official 74:9322579e4309 6484 /****************** Bit definition for SAI_xFRCR register *******************/
<> 144:ef7eb2e8f9f7 6485 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
<> 144:ef7eb2e8f9f7 6486 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6487 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6488 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6489 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6490 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6491 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6492 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6493 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 6494
<> 144:ef7eb2e8f9f7 6495 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
<> 144:ef7eb2e8f9f7 6496 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6497 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6498 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6499 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6500 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6501 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 6502 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 6503
<> 144:ef7eb2e8f9f7 6504 #define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
<> 144:ef7eb2e8f9f7 6505 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
<> 144:ef7eb2e8f9f7 6506 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
<> 144:ef7eb2e8f9f7 6507
<> 144:ef7eb2e8f9f7 6508 /* Legacy define */
<> 144:ef7eb2e8f9f7 6509 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
mbed_official 74:9322579e4309 6510
mbed_official 74:9322579e4309 6511 /****************** Bit definition for SAI_xSLOTR register *******************/
<> 144:ef7eb2e8f9f7 6512 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
<> 144:ef7eb2e8f9f7 6513 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6514 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6515 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6516 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6517 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 6518
<> 144:ef7eb2e8f9f7 6519 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
<> 144:ef7eb2e8f9f7 6520 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6521 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6522
<> 144:ef7eb2e8f9f7 6523 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
<> 144:ef7eb2e8f9f7 6524 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6525 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6526 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6527 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6528
<> 144:ef7eb2e8f9f7 6529 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
mbed_official 74:9322579e4309 6530
mbed_official 74:9322579e4309 6531 /******************* Bit definition for SAI_xIMR register *******************/
<> 144:ef7eb2e8f9f7 6532 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
<> 144:ef7eb2e8f9f7 6533 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
<> 144:ef7eb2e8f9f7 6534 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
<> 144:ef7eb2e8f9f7 6535 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
<> 144:ef7eb2e8f9f7 6536 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
<> 144:ef7eb2e8f9f7 6537 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
<> 144:ef7eb2e8f9f7 6538 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
mbed_official 74:9322579e4309 6539
mbed_official 74:9322579e4309 6540 /******************** Bit definition for SAI_xSR register *******************/
<> 144:ef7eb2e8f9f7 6541 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
<> 144:ef7eb2e8f9f7 6542 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
<> 144:ef7eb2e8f9f7 6543 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
<> 144:ef7eb2e8f9f7 6544 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
<> 144:ef7eb2e8f9f7 6545 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
<> 144:ef7eb2e8f9f7 6546 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
<> 144:ef7eb2e8f9f7 6547 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
<> 144:ef7eb2e8f9f7 6548
<> 144:ef7eb2e8f9f7 6549 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
<> 144:ef7eb2e8f9f7 6550 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6551 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6552 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
mbed_official 74:9322579e4309 6553
mbed_official 74:9322579e4309 6554 /****************** Bit definition for SAI_xCLRFR register ******************/
<> 144:ef7eb2e8f9f7 6555 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
<> 144:ef7eb2e8f9f7 6556 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
<> 144:ef7eb2e8f9f7 6557 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
<> 144:ef7eb2e8f9f7 6558 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
<> 144:ef7eb2e8f9f7 6559 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
<> 144:ef7eb2e8f9f7 6560 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
<> 144:ef7eb2e8f9f7 6561 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
mbed_official 74:9322579e4309 6562
mbed_official 74:9322579e4309 6563 /****************** Bit definition for SAI_xDR register *********************/
<> 144:ef7eb2e8f9f7 6564 #define SAI_xDR_DATA 0xFFFFFFFFU
mbed_official 74:9322579e4309 6565
mbed_official 74:9322579e4309 6566 /******************************************************************************/
mbed_official 74:9322579e4309 6567 /* */
mbed_official 74:9322579e4309 6568 /* SPDIF-RX Interface */
mbed_official 74:9322579e4309 6569 /* */
mbed_official 74:9322579e4309 6570 /******************************************************************************/
mbed_official 74:9322579e4309 6571 /******************** Bit definition for SPDIF_CR register *******************/
<> 144:ef7eb2e8f9f7 6572 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
<> 144:ef7eb2e8f9f7 6573 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
<> 144:ef7eb2e8f9f7 6574 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
<> 144:ef7eb2e8f9f7 6575 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
<> 144:ef7eb2e8f9f7 6576 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
<> 144:ef7eb2e8f9f7 6577 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
<> 144:ef7eb2e8f9f7 6578 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
<> 144:ef7eb2e8f9f7 6579 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
<> 144:ef7eb2e8f9f7 6580 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
<> 144:ef7eb2e8f9f7 6581 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
<> 144:ef7eb2e8f9f7 6582 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
<> 144:ef7eb2e8f9f7 6583 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
<> 144:ef7eb2e8f9f7 6584 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */
mbed_official 74:9322579e4309 6585
mbed_official 74:9322579e4309 6586 /******************* Bit definition for SPDIFRX_IMR register *******************/
<> 144:ef7eb2e8f9f7 6587 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
<> 144:ef7eb2e8f9f7 6588 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
<> 144:ef7eb2e8f9f7 6589 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
<> 144:ef7eb2e8f9f7 6590 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6591 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
<> 144:ef7eb2e8f9f7 6592 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
<> 144:ef7eb2e8f9f7 6593 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
mbed_official 74:9322579e4309 6594
mbed_official 74:9322579e4309 6595 /******************* Bit definition for SPDIFRX_SR register *******************/
<> 144:ef7eb2e8f9f7 6596 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
<> 144:ef7eb2e8f9f7 6597 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
<> 144:ef7eb2e8f9f7 6598 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
<> 144:ef7eb2e8f9f7 6599 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
<> 144:ef7eb2e8f9f7 6600 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
<> 144:ef7eb2e8f9f7 6601 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
<> 144:ef7eb2e8f9f7 6602 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
<> 144:ef7eb2e8f9f7 6603 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
<> 144:ef7eb2e8f9f7 6604 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
<> 144:ef7eb2e8f9f7 6605 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */
mbed_official 74:9322579e4309 6606
mbed_official 74:9322579e4309 6607 /******************* Bit definition for SPDIFRX_IFCR register *******************/
<> 144:ef7eb2e8f9f7 6608 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
<> 144:ef7eb2e8f9f7 6609 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
<> 144:ef7eb2e8f9f7 6610 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
<> 144:ef7eb2e8f9f7 6611 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
mbed_official 74:9322579e4309 6612
mbed_official 74:9322579e4309 6613 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
<> 144:ef7eb2e8f9f7 6614 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
<> 144:ef7eb2e8f9f7 6615 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
<> 144:ef7eb2e8f9f7 6616 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
<> 144:ef7eb2e8f9f7 6617 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
<> 144:ef7eb2e8f9f7 6618 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
<> 144:ef7eb2e8f9f7 6619 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
mbed_official 74:9322579e4309 6620
mbed_official 74:9322579e4309 6621 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
<> 144:ef7eb2e8f9f7 6622 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
<> 144:ef7eb2e8f9f7 6623 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
<> 144:ef7eb2e8f9f7 6624 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
<> 144:ef7eb2e8f9f7 6625 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
<> 144:ef7eb2e8f9f7 6626 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
<> 144:ef7eb2e8f9f7 6627 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
mbed_official 74:9322579e4309 6628
mbed_official 74:9322579e4309 6629 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
<> 144:ef7eb2e8f9f7 6630 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
<> 144:ef7eb2e8f9f7 6631 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
mbed_official 74:9322579e4309 6632
mbed_official 74:9322579e4309 6633 /******************* Bit definition for SPDIFRX_CSR register *******************/
<> 144:ef7eb2e8f9f7 6634 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
<> 144:ef7eb2e8f9f7 6635 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
<> 144:ef7eb2e8f9f7 6636 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
mbed_official 74:9322579e4309 6637
mbed_official 74:9322579e4309 6638 /******************* Bit definition for SPDIFRX_DIR register *******************/
<> 144:ef7eb2e8f9f7 6639 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
<> 144:ef7eb2e8f9f7 6640 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
mbed_official 74:9322579e4309 6641
mbed_official 74:9322579e4309 6642
mbed_official 74:9322579e4309 6643 /******************************************************************************/
mbed_official 74:9322579e4309 6644 /* */
mbed_official 74:9322579e4309 6645 /* SD host Interface */
mbed_official 74:9322579e4309 6646 /* */
mbed_official 74:9322579e4309 6647 /******************************************************************************/
mbed_official 74:9322579e4309 6648 /****************** Bit definition for SDMMC_POWER register ******************/
<> 144:ef7eb2e8f9f7 6649 #define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 144:ef7eb2e8f9f7 6650 #define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6651 #define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
mbed_official 74:9322579e4309 6652
mbed_official 74:9322579e4309 6653 /****************** Bit definition for SDMMC_CLKCR register ******************/
<> 144:ef7eb2e8f9f7 6654 #define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
<> 144:ef7eb2e8f9f7 6655 #define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
<> 144:ef7eb2e8f9f7 6656 #define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
<> 144:ef7eb2e8f9f7 6657 #define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
mbed_official 74:9322579e4309 6658
<> 144:ef7eb2e8f9f7 6659 #define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 144:ef7eb2e8f9f7 6660 #define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6661 #define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
mbed_official 74:9322579e4309 6662
<> 144:ef7eb2e8f9f7 6663 #define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */
<> 144:ef7eb2e8f9f7 6664 #define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
mbed_official 74:9322579e4309 6665
mbed_official 74:9322579e4309 6666 /******************* Bit definition for SDMMC_ARG register *******************/
<> 144:ef7eb2e8f9f7 6667 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
mbed_official 74:9322579e4309 6668
mbed_official 74:9322579e4309 6669 /******************* Bit definition for SDMMC_CMD register *******************/
<> 144:ef7eb2e8f9f7 6670 #define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */
mbed_official 74:9322579e4309 6671
<> 144:ef7eb2e8f9f7 6672 #define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 144:ef7eb2e8f9f7 6673 #define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 6674 #define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
mbed_official 74:9322579e4309 6675
<> 144:ef7eb2e8f9f7 6676 #define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
<> 144:ef7eb2e8f9f7 6677 #define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 144:ef7eb2e8f9f7 6678 #define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
<> 144:ef7eb2e8f9f7 6679 #define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
mbed_official 74:9322579e4309 6680
mbed_official 74:9322579e4309 6681 /***************** Bit definition for SDMMC_RESPCMD register *****************/
<> 144:ef7eb2e8f9f7 6682 #define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
mbed_official 74:9322579e4309 6683
mbed_official 74:9322579e4309 6684 /****************** Bit definition for SDMMC_RESP0 register ******************/
<> 144:ef7eb2e8f9f7 6685 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
mbed_official 74:9322579e4309 6686
mbed_official 74:9322579e4309 6687 /****************** Bit definition for SDMMC_RESP1 register ******************/
<> 144:ef7eb2e8f9f7 6688 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
mbed_official 74:9322579e4309 6689
mbed_official 74:9322579e4309 6690 /****************** Bit definition for SDMMC_RESP2 register ******************/
<> 144:ef7eb2e8f9f7 6691 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
mbed_official 74:9322579e4309 6692
mbed_official 74:9322579e4309 6693 /****************** Bit definition for SDMMC_RESP3 register ******************/
<> 144:ef7eb2e8f9f7 6694 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
mbed_official 74:9322579e4309 6695
mbed_official 74:9322579e4309 6696 /****************** Bit definition for SDMMC_RESP4 register ******************/
<> 144:ef7eb2e8f9f7 6697 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
mbed_official 74:9322579e4309 6698
mbed_official 74:9322579e4309 6699 /****************** Bit definition for SDMMC_DTIMER register *****************/
<> 144:ef7eb2e8f9f7 6700 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
mbed_official 74:9322579e4309 6701
mbed_official 74:9322579e4309 6702 /****************** Bit definition for SDMMC_DLEN register *******************/
<> 144:ef7eb2e8f9f7 6703 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
mbed_official 74:9322579e4309 6704
mbed_official 74:9322579e4309 6705 /****************** Bit definition for SDMMC_DCTRL register ******************/
<> 144:ef7eb2e8f9f7 6706 #define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
<> 144:ef7eb2e8f9f7 6707 #define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
<> 144:ef7eb2e8f9f7 6708 #define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
<> 144:ef7eb2e8f9f7 6709 #define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
<> 144:ef7eb2e8f9f7 6710
<> 144:ef7eb2e8f9f7 6711 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 144:ef7eb2e8f9f7 6712 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6713 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6714 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 6715 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 6716
<> 144:ef7eb2e8f9f7 6717 #define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */
<> 144:ef7eb2e8f9f7 6718 #define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
<> 144:ef7eb2e8f9f7 6719 #define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
<> 144:ef7eb2e8f9f7 6720 #define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
mbed_official 74:9322579e4309 6721
mbed_official 74:9322579e4309 6722 /****************** Bit definition for SDMMC_DCOUNT register *****************/
<> 144:ef7eb2e8f9f7 6723 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
<> 144:ef7eb2e8f9f7 6724
<> 144:ef7eb2e8f9f7 6725 /****************** Bit definition for SDMMC_STA registe ********************/
<> 144:ef7eb2e8f9f7 6726 #define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
<> 144:ef7eb2e8f9f7 6727 #define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
<> 144:ef7eb2e8f9f7 6728 #define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
<> 144:ef7eb2e8f9f7 6729 #define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
<> 144:ef7eb2e8f9f7 6730 #define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
<> 144:ef7eb2e8f9f7 6731 #define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
<> 144:ef7eb2e8f9f7 6732 #define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
<> 144:ef7eb2e8f9f7 6733 #define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
<> 144:ef7eb2e8f9f7 6734 #define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 144:ef7eb2e8f9f7 6735 #define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
<> 144:ef7eb2e8f9f7 6736 #define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
<> 144:ef7eb2e8f9f7 6737 #define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */
<> 144:ef7eb2e8f9f7 6738 #define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */
<> 144:ef7eb2e8f9f7 6739 #define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 144:ef7eb2e8f9f7 6740 #define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 144:ef7eb2e8f9f7 6741 #define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
<> 144:ef7eb2e8f9f7 6742 #define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
<> 144:ef7eb2e8f9f7 6743 #define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 6744 #define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
<> 144:ef7eb2e8f9f7 6745 #define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
<> 144:ef7eb2e8f9f7 6746 #define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
<> 144:ef7eb2e8f9f7 6747 #define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */
mbed_official 74:9322579e4309 6748
mbed_official 74:9322579e4309 6749 /******************* Bit definition for SDMMC_ICR register *******************/
<> 144:ef7eb2e8f9f7 6750 #define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 6751 #define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
<> 144:ef7eb2e8f9f7 6752 #define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 6753 #define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
<> 144:ef7eb2e8f9f7 6754 #define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
<> 144:ef7eb2e8f9f7 6755 #define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
<> 144:ef7eb2e8f9f7 6756 #define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
<> 144:ef7eb2e8f9f7 6757 #define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
<> 144:ef7eb2e8f9f7 6758 #define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 6759 #define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
<> 144:ef7eb2e8f9f7 6760 #define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */
mbed_official 74:9322579e4309 6761
mbed_official 74:9322579e4309 6762 /****************** Bit definition for SDMMC_MASK register *******************/
<> 144:ef7eb2e8f9f7 6763 #define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 6764 #define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
<> 144:ef7eb2e8f9f7 6765 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 6766 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
<> 144:ef7eb2e8f9f7 6767 #define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6768 #define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6769 #define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
<> 144:ef7eb2e8f9f7 6770 #define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
<> 144:ef7eb2e8f9f7 6771 #define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
<> 144:ef7eb2e8f9f7 6772 #define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
<> 144:ef7eb2e8f9f7 6773 #define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 6774 #define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
<> 144:ef7eb2e8f9f7 6775 #define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
<> 144:ef7eb2e8f9f7 6776 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 6777 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6778 #define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6779 #define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
<> 144:ef7eb2e8f9f7 6780 #define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 6781 #define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
<> 144:ef7eb2e8f9f7 6782 #define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 6783 #define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
<> 144:ef7eb2e8f9f7 6784 #define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */
mbed_official 74:9322579e4309 6785
mbed_official 74:9322579e4309 6786 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
<> 144:ef7eb2e8f9f7 6787 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 74:9322579e4309 6788
mbed_official 74:9322579e4309 6789 /****************** Bit definition for SDMMC_FIFO register *******************/
<> 144:ef7eb2e8f9f7 6790 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
mbed_official 74:9322579e4309 6791
mbed_official 74:9322579e4309 6792 /******************************************************************************/
mbed_official 74:9322579e4309 6793 /* */
mbed_official 74:9322579e4309 6794 /* Serial Peripheral Interface (SPI) */
mbed_official 74:9322579e4309 6795 /* */
mbed_official 74:9322579e4309 6796 /******************************************************************************/
mbed_official 74:9322579e4309 6797 /******************* Bit definition for SPI_CR1 register ********************/
<> 144:ef7eb2e8f9f7 6798 #define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 6799 #define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 6800 #define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */
<> 144:ef7eb2e8f9f7 6801 #define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */
<> 144:ef7eb2e8f9f7 6802 #define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 6803 #define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 6804 #define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 6805 #define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */
<> 144:ef7eb2e8f9f7 6806 #define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */
<> 144:ef7eb2e8f9f7 6807 #define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */
<> 144:ef7eb2e8f9f7 6808 #define SPI_CR1_SSM 0x00000200U /*!< Software slave management */
<> 144:ef7eb2e8f9f7 6809 #define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */
<> 144:ef7eb2e8f9f7 6810 #define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */
<> 144:ef7eb2e8f9f7 6811 #define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */
<> 144:ef7eb2e8f9f7 6812 #define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */
<> 144:ef7eb2e8f9f7 6813 #define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */
<> 144:ef7eb2e8f9f7 6814 #define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */
mbed_official 74:9322579e4309 6815
mbed_official 74:9322579e4309 6816 /******************* Bit definition for SPI_CR2 register ********************/
<> 144:ef7eb2e8f9f7 6817 #define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 6818 #define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */
<> 144:ef7eb2e8f9f7 6819 #define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */
<> 144:ef7eb2e8f9f7 6820 #define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */
<> 144:ef7eb2e8f9f7 6821 #define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */
<> 144:ef7eb2e8f9f7 6822 #define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 6823 #define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 6824 #define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 6825 #define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */
<> 144:ef7eb2e8f9f7 6826 #define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 6827 #define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 6828 #define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 6829 #define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 6830 #define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */
<> 144:ef7eb2e8f9f7 6831 #define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */
<> 144:ef7eb2e8f9f7 6832 #define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */
mbed_official 74:9322579e4309 6833
mbed_official 74:9322579e4309 6834 /******************** Bit definition for SPI_SR register ********************/
<> 144:ef7eb2e8f9f7 6835 #define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */
<> 144:ef7eb2e8f9f7 6836 #define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */
<> 144:ef7eb2e8f9f7 6837 #define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */
<> 144:ef7eb2e8f9f7 6838 #define SPI_SR_UDR 0x00000008U /*!< Underrun flag */
<> 144:ef7eb2e8f9f7 6839 #define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */
<> 144:ef7eb2e8f9f7 6840 #define SPI_SR_MODF 0x00000020U /*!< Mode fault */
<> 144:ef7eb2e8f9f7 6841 #define SPI_SR_OVR 0x00000040U /*!< Overrun flag */
<> 144:ef7eb2e8f9f7 6842 #define SPI_SR_BSY 0x00000080U /*!< Busy flag */
<> 144:ef7eb2e8f9f7 6843 #define SPI_SR_FRE 0x00000100U /*!< TI frame format error */
<> 144:ef7eb2e8f9f7 6844 #define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */
<> 144:ef7eb2e8f9f7 6845 #define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 6846 #define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 6847 #define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */
<> 144:ef7eb2e8f9f7 6848 #define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 6849 #define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */
mbed_official 74:9322579e4309 6850
mbed_official 74:9322579e4309 6851 /******************** Bit definition for SPI_DR register ********************/
<> 144:ef7eb2e8f9f7 6852 #define SPI_DR_DR 0xFFFFU /*!< Data Register */
mbed_official 74:9322579e4309 6853
mbed_official 74:9322579e4309 6854 /******************* Bit definition for SPI_CRCPR register ******************/
<> 144:ef7eb2e8f9f7 6855 #define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */
mbed_official 74:9322579e4309 6856
mbed_official 74:9322579e4309 6857 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 144:ef7eb2e8f9f7 6858 #define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */
mbed_official 74:9322579e4309 6859
mbed_official 74:9322579e4309 6860 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 144:ef7eb2e8f9f7 6861 #define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */
mbed_official 74:9322579e4309 6862
mbed_official 74:9322579e4309 6863 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 144:ef7eb2e8f9f7 6864 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 144:ef7eb2e8f9f7 6865 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 144:ef7eb2e8f9f7 6866 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6867 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6868 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 144:ef7eb2e8f9f7 6869 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 144:ef7eb2e8f9f7 6870 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6871 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6872 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 144:ef7eb2e8f9f7 6873 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 144:ef7eb2e8f9f7 6874 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 6875 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 6876 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 144:ef7eb2e8f9f7 6877 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
<> 144:ef7eb2e8f9f7 6878 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
mbed_official 74:9322579e4309 6879
mbed_official 74:9322579e4309 6880 /****************** Bit definition for SPI_I2SPR register *******************/
<> 144:ef7eb2e8f9f7 6881 #define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */
<> 144:ef7eb2e8f9f7 6882 #define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */
<> 144:ef7eb2e8f9f7 6883 #define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */
mbed_official 74:9322579e4309 6884
mbed_official 74:9322579e4309 6885
mbed_official 74:9322579e4309 6886 /******************************************************************************/
mbed_official 74:9322579e4309 6887 /* */
mbed_official 74:9322579e4309 6888 /* SYSCFG */
mbed_official 74:9322579e4309 6889 /* */
mbed_official 74:9322579e4309 6890 /******************************************************************************/
mbed_official 74:9322579e4309 6891 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 144:ef7eb2e8f9f7 6892 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */
<> 144:ef7eb2e8f9f7 6893
<> 144:ef7eb2e8f9f7 6894
<> 144:ef7eb2e8f9f7 6895 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */
<> 144:ef7eb2e8f9f7 6896 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
<> 144:ef7eb2e8f9f7 6897 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
mbed_official 74:9322579e4309 6898
mbed_official 74:9322579e4309 6899 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 83:a036322b8637 6900
<> 144:ef7eb2e8f9f7 6901 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 6902 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 6903 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 6904 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
<> 144:ef7eb2e8f9f7 6905
<> 144:ef7eb2e8f9f7 6906 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
mbed_official 74:9322579e4309 6907
mbed_official 74:9322579e4309 6908 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 144:ef7eb2e8f9f7 6909 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
<> 144:ef7eb2e8f9f7 6910 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
<> 144:ef7eb2e8f9f7 6911 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
<> 144:ef7eb2e8f9f7 6912 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
mbed_official 74:9322579e4309 6913 /**
mbed_official 74:9322579e4309 6914 * @brief EXTI0 configuration
mbed_official 74:9322579e4309 6915 */
<> 144:ef7eb2e8f9f7 6916 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 144:ef7eb2e8f9f7 6917 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 144:ef7eb2e8f9f7 6918 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 144:ef7eb2e8f9f7 6919 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
<> 144:ef7eb2e8f9f7 6920 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
<> 144:ef7eb2e8f9f7 6921 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
<> 144:ef7eb2e8f9f7 6922 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
<> 144:ef7eb2e8f9f7 6923 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
<> 144:ef7eb2e8f9f7 6924 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
<> 144:ef7eb2e8f9f7 6925 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
<> 144:ef7eb2e8f9f7 6926 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
mbed_official 74:9322579e4309 6927
mbed_official 74:9322579e4309 6928 /**
mbed_official 74:9322579e4309 6929 * @brief EXTI1 configuration
mbed_official 74:9322579e4309 6930 */
<> 144:ef7eb2e8f9f7 6931 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 144:ef7eb2e8f9f7 6932 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 144:ef7eb2e8f9f7 6933 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 144:ef7eb2e8f9f7 6934 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
<> 144:ef7eb2e8f9f7 6935 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
<> 144:ef7eb2e8f9f7 6936 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
<> 144:ef7eb2e8f9f7 6937 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
<> 144:ef7eb2e8f9f7 6938 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
<> 144:ef7eb2e8f9f7 6939 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
<> 144:ef7eb2e8f9f7 6940 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
<> 144:ef7eb2e8f9f7 6941 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
mbed_official 74:9322579e4309 6942
mbed_official 74:9322579e4309 6943 /**
mbed_official 74:9322579e4309 6944 * @brief EXTI2 configuration
mbed_official 74:9322579e4309 6945 */
<> 144:ef7eb2e8f9f7 6946 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 144:ef7eb2e8f9f7 6947 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 144:ef7eb2e8f9f7 6948 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 144:ef7eb2e8f9f7 6949 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
<> 144:ef7eb2e8f9f7 6950 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
<> 144:ef7eb2e8f9f7 6951 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
<> 144:ef7eb2e8f9f7 6952 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
<> 144:ef7eb2e8f9f7 6953 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
<> 144:ef7eb2e8f9f7 6954 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
<> 144:ef7eb2e8f9f7 6955 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
<> 144:ef7eb2e8f9f7 6956 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
mbed_official 74:9322579e4309 6957
mbed_official 74:9322579e4309 6958 /**
mbed_official 74:9322579e4309 6959 * @brief EXTI3 configuration
mbed_official 74:9322579e4309 6960 */
<> 144:ef7eb2e8f9f7 6961 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 144:ef7eb2e8f9f7 6962 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 144:ef7eb2e8f9f7 6963 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 144:ef7eb2e8f9f7 6964 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
<> 144:ef7eb2e8f9f7 6965 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
<> 144:ef7eb2e8f9f7 6966 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
<> 144:ef7eb2e8f9f7 6967 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
<> 144:ef7eb2e8f9f7 6968 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 144:ef7eb2e8f9f7 6969 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
<> 144:ef7eb2e8f9f7 6970 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
<> 144:ef7eb2e8f9f7 6971 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
mbed_official 74:9322579e4309 6972
mbed_official 74:9322579e4309 6973 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 144:ef7eb2e8f9f7 6974 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
<> 144:ef7eb2e8f9f7 6975 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
<> 144:ef7eb2e8f9f7 6976 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
<> 144:ef7eb2e8f9f7 6977 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
mbed_official 74:9322579e4309 6978 /**
mbed_official 74:9322579e4309 6979 * @brief EXTI4 configuration
mbed_official 74:9322579e4309 6980 */
<> 144:ef7eb2e8f9f7 6981 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 144:ef7eb2e8f9f7 6982 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 144:ef7eb2e8f9f7 6983 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 144:ef7eb2e8f9f7 6984 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
<> 144:ef7eb2e8f9f7 6985 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
<> 144:ef7eb2e8f9f7 6986 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
<> 144:ef7eb2e8f9f7 6987 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
<> 144:ef7eb2e8f9f7 6988 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
<> 144:ef7eb2e8f9f7 6989 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
<> 144:ef7eb2e8f9f7 6990 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
<> 144:ef7eb2e8f9f7 6991 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
mbed_official 74:9322579e4309 6992
mbed_official 74:9322579e4309 6993 /**
mbed_official 74:9322579e4309 6994 * @brief EXTI5 configuration
mbed_official 74:9322579e4309 6995 */
<> 144:ef7eb2e8f9f7 6996 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 144:ef7eb2e8f9f7 6997 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 144:ef7eb2e8f9f7 6998 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 144:ef7eb2e8f9f7 6999 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
<> 144:ef7eb2e8f9f7 7000 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
<> 144:ef7eb2e8f9f7 7001 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
<> 144:ef7eb2e8f9f7 7002 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
<> 144:ef7eb2e8f9f7 7003 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
<> 144:ef7eb2e8f9f7 7004 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
<> 144:ef7eb2e8f9f7 7005 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
<> 144:ef7eb2e8f9f7 7006 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
mbed_official 74:9322579e4309 7007
mbed_official 74:9322579e4309 7008 /**
mbed_official 74:9322579e4309 7009 * @brief EXTI6 configuration
mbed_official 74:9322579e4309 7010 */
<> 144:ef7eb2e8f9f7 7011 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 144:ef7eb2e8f9f7 7012 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 144:ef7eb2e8f9f7 7013 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 144:ef7eb2e8f9f7 7014 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
<> 144:ef7eb2e8f9f7 7015 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
<> 144:ef7eb2e8f9f7 7016 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
<> 144:ef7eb2e8f9f7 7017 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
<> 144:ef7eb2e8f9f7 7018 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
<> 144:ef7eb2e8f9f7 7019 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
<> 144:ef7eb2e8f9f7 7020 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
<> 144:ef7eb2e8f9f7 7021 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
mbed_official 74:9322579e4309 7022
mbed_official 74:9322579e4309 7023 /**
mbed_official 74:9322579e4309 7024 * @brief EXTI7 configuration
mbed_official 74:9322579e4309 7025 */
<> 144:ef7eb2e8f9f7 7026 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 144:ef7eb2e8f9f7 7027 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 144:ef7eb2e8f9f7 7028 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 144:ef7eb2e8f9f7 7029 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
<> 144:ef7eb2e8f9f7 7030 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
<> 144:ef7eb2e8f9f7 7031 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
<> 144:ef7eb2e8f9f7 7032 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
<> 144:ef7eb2e8f9f7 7033 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 144:ef7eb2e8f9f7 7034 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
<> 144:ef7eb2e8f9f7 7035 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
<> 144:ef7eb2e8f9f7 7036 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
mbed_official 74:9322579e4309 7037
mbed_official 74:9322579e4309 7038 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 144:ef7eb2e8f9f7 7039 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
<> 144:ef7eb2e8f9f7 7040 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
<> 144:ef7eb2e8f9f7 7041 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
<> 144:ef7eb2e8f9f7 7042 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
mbed_official 74:9322579e4309 7043
mbed_official 74:9322579e4309 7044 /**
mbed_official 74:9322579e4309 7045 * @brief EXTI8 configuration
mbed_official 74:9322579e4309 7046 */
<> 144:ef7eb2e8f9f7 7047 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 144:ef7eb2e8f9f7 7048 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 144:ef7eb2e8f9f7 7049 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 144:ef7eb2e8f9f7 7050 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
<> 144:ef7eb2e8f9f7 7051 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
<> 144:ef7eb2e8f9f7 7052 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
<> 144:ef7eb2e8f9f7 7053 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
<> 144:ef7eb2e8f9f7 7054 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
<> 144:ef7eb2e8f9f7 7055 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
<> 144:ef7eb2e8f9f7 7056 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
mbed_official 74:9322579e4309 7057
mbed_official 74:9322579e4309 7058 /**
mbed_official 74:9322579e4309 7059 * @brief EXTI9 configuration
mbed_official 74:9322579e4309 7060 */
<> 144:ef7eb2e8f9f7 7061 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 144:ef7eb2e8f9f7 7062 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 144:ef7eb2e8f9f7 7063 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 144:ef7eb2e8f9f7 7064 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
<> 144:ef7eb2e8f9f7 7065 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
<> 144:ef7eb2e8f9f7 7066 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
<> 144:ef7eb2e8f9f7 7067 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
<> 144:ef7eb2e8f9f7 7068 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
<> 144:ef7eb2e8f9f7 7069 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
<> 144:ef7eb2e8f9f7 7070 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
mbed_official 74:9322579e4309 7071
mbed_official 74:9322579e4309 7072 /**
mbed_official 74:9322579e4309 7073 * @brief EXTI10 configuration
mbed_official 74:9322579e4309 7074 */
<> 144:ef7eb2e8f9f7 7075 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 144:ef7eb2e8f9f7 7076 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 144:ef7eb2e8f9f7 7077 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 144:ef7eb2e8f9f7 7078 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
<> 144:ef7eb2e8f9f7 7079 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
<> 144:ef7eb2e8f9f7 7080 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
<> 144:ef7eb2e8f9f7 7081 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
<> 144:ef7eb2e8f9f7 7082 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
<> 144:ef7eb2e8f9f7 7083 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
<> 144:ef7eb2e8f9f7 7084 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
mbed_official 74:9322579e4309 7085
mbed_official 74:9322579e4309 7086 /**
mbed_official 74:9322579e4309 7087 * @brief EXTI11 configuration
mbed_official 74:9322579e4309 7088 */
<> 144:ef7eb2e8f9f7 7089 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 144:ef7eb2e8f9f7 7090 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 144:ef7eb2e8f9f7 7091 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 144:ef7eb2e8f9f7 7092 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
<> 144:ef7eb2e8f9f7 7093 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
<> 144:ef7eb2e8f9f7 7094 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
<> 144:ef7eb2e8f9f7 7095 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
<> 144:ef7eb2e8f9f7 7096 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 144:ef7eb2e8f9f7 7097 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
<> 144:ef7eb2e8f9f7 7098 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
mbed_official 74:9322579e4309 7099
mbed_official 74:9322579e4309 7100
mbed_official 74:9322579e4309 7101 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 144:ef7eb2e8f9f7 7102 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
<> 144:ef7eb2e8f9f7 7103 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
<> 144:ef7eb2e8f9f7 7104 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
<> 144:ef7eb2e8f9f7 7105 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
mbed_official 74:9322579e4309 7106 /**
mbed_official 74:9322579e4309 7107 * @brief EXTI12 configuration
mbed_official 74:9322579e4309 7108 */
<> 144:ef7eb2e8f9f7 7109 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 144:ef7eb2e8f9f7 7110 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 144:ef7eb2e8f9f7 7111 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 144:ef7eb2e8f9f7 7112 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
<> 144:ef7eb2e8f9f7 7113 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
<> 144:ef7eb2e8f9f7 7114 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
<> 144:ef7eb2e8f9f7 7115 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
<> 144:ef7eb2e8f9f7 7116 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
<> 144:ef7eb2e8f9f7 7117 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
<> 144:ef7eb2e8f9f7 7118 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
mbed_official 74:9322579e4309 7119
mbed_official 74:9322579e4309 7120 /**
mbed_official 74:9322579e4309 7121 * @brief EXTI13 configuration
mbed_official 74:9322579e4309 7122 */
<> 144:ef7eb2e8f9f7 7123 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 144:ef7eb2e8f9f7 7124 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 144:ef7eb2e8f9f7 7125 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 144:ef7eb2e8f9f7 7126 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
<> 144:ef7eb2e8f9f7 7127 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
<> 144:ef7eb2e8f9f7 7128 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
<> 144:ef7eb2e8f9f7 7129 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
<> 144:ef7eb2e8f9f7 7130 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
<> 144:ef7eb2e8f9f7 7131 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
<> 144:ef7eb2e8f9f7 7132 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
mbed_official 74:9322579e4309 7133
mbed_official 74:9322579e4309 7134 /**
mbed_official 74:9322579e4309 7135 * @brief EXTI14 configuration
mbed_official 74:9322579e4309 7136 */
<> 144:ef7eb2e8f9f7 7137 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 144:ef7eb2e8f9f7 7138 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 144:ef7eb2e8f9f7 7139 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 144:ef7eb2e8f9f7 7140 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
<> 144:ef7eb2e8f9f7 7141 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
<> 144:ef7eb2e8f9f7 7142 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
<> 144:ef7eb2e8f9f7 7143 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
<> 144:ef7eb2e8f9f7 7144 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
<> 144:ef7eb2e8f9f7 7145 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
<> 144:ef7eb2e8f9f7 7146 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
mbed_official 74:9322579e4309 7147
mbed_official 74:9322579e4309 7148 /**
mbed_official 74:9322579e4309 7149 * @brief EXTI15 configuration
mbed_official 74:9322579e4309 7150 */
<> 144:ef7eb2e8f9f7 7151 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 144:ef7eb2e8f9f7 7152 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 144:ef7eb2e8f9f7 7153 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 144:ef7eb2e8f9f7 7154 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
<> 144:ef7eb2e8f9f7 7155 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
<> 144:ef7eb2e8f9f7 7156 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
<> 144:ef7eb2e8f9f7 7157 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
<> 144:ef7eb2e8f9f7 7158 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
<> 144:ef7eb2e8f9f7 7159 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
<> 144:ef7eb2e8f9f7 7160 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
<> 144:ef7eb2e8f9f7 7161
mbed_official 74:9322579e4309 7162
mbed_official 74:9322579e4309 7163 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 144:ef7eb2e8f9f7 7164 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */
<> 144:ef7eb2e8f9f7 7165 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */
mbed_official 74:9322579e4309 7166
mbed_official 74:9322579e4309 7167 /******************************************************************************/
mbed_official 74:9322579e4309 7168 /* */
mbed_official 74:9322579e4309 7169 /* TIM */
mbed_official 74:9322579e4309 7170 /* */
mbed_official 74:9322579e4309 7171 /******************************************************************************/
mbed_official 74:9322579e4309 7172 /******************* Bit definition for TIM_CR1 register ********************/
<> 144:ef7eb2e8f9f7 7173 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
<> 144:ef7eb2e8f9f7 7174 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
<> 144:ef7eb2e8f9f7 7175 #define TIM_CR1_URS 0x0004U /*!<Update request source */
<> 144:ef7eb2e8f9f7 7176 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
<> 144:ef7eb2e8f9f7 7177 #define TIM_CR1_DIR 0x0010U /*!<Direction */
<> 144:ef7eb2e8f9f7 7178
<> 144:ef7eb2e8f9f7 7179 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 144:ef7eb2e8f9f7 7180 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7181 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7182
<> 144:ef7eb2e8f9f7 7183 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
<> 144:ef7eb2e8f9f7 7184
<> 144:ef7eb2e8f9f7 7185 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
<> 144:ef7eb2e8f9f7 7186 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7187 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7188 #define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */
mbed_official 74:9322579e4309 7189
mbed_official 74:9322579e4309 7190 /******************* Bit definition for TIM_CR2 register ********************/
<> 144:ef7eb2e8f9f7 7191 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
<> 144:ef7eb2e8f9f7 7192 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
<> 144:ef7eb2e8f9f7 7193 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
<> 144:ef7eb2e8f9f7 7194
<> 144:ef7eb2e8f9f7 7195 #define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 7196 #define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 7197
<> 144:ef7eb2e8f9f7 7198 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 7199 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7200 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7201 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7202
<> 144:ef7eb2e8f9f7 7203 #define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 144:ef7eb2e8f9f7 7204 #define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7205 #define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7206 #define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7207 #define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7208
<> 144:ef7eb2e8f9f7 7209 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
<> 144:ef7eb2e8f9f7 7210 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
<> 144:ef7eb2e8f9f7 7211 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
<> 144:ef7eb2e8f9f7 7212 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
<> 144:ef7eb2e8f9f7 7213 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
<> 144:ef7eb2e8f9f7 7214 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
<> 144:ef7eb2e8f9f7 7215 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
<> 144:ef7eb2e8f9f7 7216 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
mbed_official 74:9322579e4309 7217
mbed_official 74:9322579e4309 7218 /******************* Bit definition for TIM_SMCR register *******************/
<> 144:ef7eb2e8f9f7 7219 #define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 144:ef7eb2e8f9f7 7220 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7221 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7222 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7223 #define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7224 #define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */
<> 144:ef7eb2e8f9f7 7225
<> 144:ef7eb2e8f9f7 7226 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
<> 144:ef7eb2e8f9f7 7227 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7228 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7229 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7230
<> 144:ef7eb2e8f9f7 7231 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
<> 144:ef7eb2e8f9f7 7232
<> 144:ef7eb2e8f9f7 7233 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 144:ef7eb2e8f9f7 7234 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7235 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7236 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7237 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7238
<> 144:ef7eb2e8f9f7 7239 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 144:ef7eb2e8f9f7 7240 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7241 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7242
<> 144:ef7eb2e8f9f7 7243 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
<> 144:ef7eb2e8f9f7 7244 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
mbed_official 74:9322579e4309 7245
mbed_official 74:9322579e4309 7246 /******************* Bit definition for TIM_DIER register *******************/
<> 144:ef7eb2e8f9f7 7247 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
<> 144:ef7eb2e8f9f7 7248 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
<> 144:ef7eb2e8f9f7 7249 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
<> 144:ef7eb2e8f9f7 7250 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
<> 144:ef7eb2e8f9f7 7251 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
<> 144:ef7eb2e8f9f7 7252 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
<> 144:ef7eb2e8f9f7 7253 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
<> 144:ef7eb2e8f9f7 7254 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
<> 144:ef7eb2e8f9f7 7255 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
<> 144:ef7eb2e8f9f7 7256 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
<> 144:ef7eb2e8f9f7 7257 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
<> 144:ef7eb2e8f9f7 7258 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
<> 144:ef7eb2e8f9f7 7259 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
<> 144:ef7eb2e8f9f7 7260 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
<> 144:ef7eb2e8f9f7 7261 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
mbed_official 74:9322579e4309 7262
mbed_official 74:9322579e4309 7263 /******************** Bit definition for TIM_SR register ********************/
<> 144:ef7eb2e8f9f7 7264 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
<> 144:ef7eb2e8f9f7 7265 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
<> 144:ef7eb2e8f9f7 7266 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
<> 144:ef7eb2e8f9f7 7267 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
<> 144:ef7eb2e8f9f7 7268 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
<> 144:ef7eb2e8f9f7 7269 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
<> 144:ef7eb2e8f9f7 7270 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
<> 144:ef7eb2e8f9f7 7271 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
<> 144:ef7eb2e8f9f7 7272 #define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */
<> 144:ef7eb2e8f9f7 7273 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
<> 144:ef7eb2e8f9f7 7274 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
<> 144:ef7eb2e8f9f7 7275 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
<> 144:ef7eb2e8f9f7 7276 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 74:9322579e4309 7277
mbed_official 74:9322579e4309 7278 /******************* Bit definition for TIM_EGR register ********************/
<> 144:ef7eb2e8f9f7 7279 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
<> 144:ef7eb2e8f9f7 7280 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
<> 144:ef7eb2e8f9f7 7281 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
<> 144:ef7eb2e8f9f7 7282 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
<> 144:ef7eb2e8f9f7 7283 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
<> 144:ef7eb2e8f9f7 7284 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
<> 144:ef7eb2e8f9f7 7285 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
<> 144:ef7eb2e8f9f7 7286 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
<> 144:ef7eb2e8f9f7 7287 #define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */
mbed_official 74:9322579e4309 7288
mbed_official 74:9322579e4309 7289 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 144:ef7eb2e8f9f7 7290 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 144:ef7eb2e8f9f7 7291 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7292 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7293
<> 144:ef7eb2e8f9f7 7294 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
<> 144:ef7eb2e8f9f7 7295 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
<> 144:ef7eb2e8f9f7 7296
<> 144:ef7eb2e8f9f7 7297 #define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 144:ef7eb2e8f9f7 7298 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7299 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7300 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7301 #define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7302
<> 144:ef7eb2e8f9f7 7303 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
<> 144:ef7eb2e8f9f7 7304
<> 144:ef7eb2e8f9f7 7305 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 144:ef7eb2e8f9f7 7306 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7307 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7308
<> 144:ef7eb2e8f9f7 7309 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
<> 144:ef7eb2e8f9f7 7310 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
<> 144:ef7eb2e8f9f7 7311
<> 144:ef7eb2e8f9f7 7312 #define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 144:ef7eb2e8f9f7 7313 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7314 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7315 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7316 #define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7317
<> 144:ef7eb2e8f9f7 7318 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
mbed_official 74:9322579e4309 7319
mbed_official 74:9322579e4309 7320 /*----------------------------------------------------------------------------*/
mbed_official 74:9322579e4309 7321
<> 144:ef7eb2e8f9f7 7322 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 144:ef7eb2e8f9f7 7323 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7324 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7325
<> 144:ef7eb2e8f9f7 7326 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 144:ef7eb2e8f9f7 7327 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7328 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7329 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7330 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7331
<> 144:ef7eb2e8f9f7 7332 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 144:ef7eb2e8f9f7 7333 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7334 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7335
<> 144:ef7eb2e8f9f7 7336 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 144:ef7eb2e8f9f7 7337 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7338 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7339 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7340 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
mbed_official 74:9322579e4309 7341
mbed_official 74:9322579e4309 7342 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 144:ef7eb2e8f9f7 7343 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 144:ef7eb2e8f9f7 7344 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7345 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7346
<> 144:ef7eb2e8f9f7 7347 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
<> 144:ef7eb2e8f9f7 7348 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
<> 144:ef7eb2e8f9f7 7349
<> 144:ef7eb2e8f9f7 7350 #define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 144:ef7eb2e8f9f7 7351 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7352 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7353 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7354 #define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7355
<> 144:ef7eb2e8f9f7 7356
<> 144:ef7eb2e8f9f7 7357
<> 144:ef7eb2e8f9f7 7358 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
<> 144:ef7eb2e8f9f7 7359
<> 144:ef7eb2e8f9f7 7360 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 144:ef7eb2e8f9f7 7361 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7362 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7363
<> 144:ef7eb2e8f9f7 7364 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 7365 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 7366
<> 144:ef7eb2e8f9f7 7367 #define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 7368 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7369 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7370 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7371 #define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7372
<> 144:ef7eb2e8f9f7 7373 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
mbed_official 74:9322579e4309 7374
mbed_official 74:9322579e4309 7375 /*----------------------------------------------------------------------------*/
mbed_official 74:9322579e4309 7376
<> 144:ef7eb2e8f9f7 7377 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 144:ef7eb2e8f9f7 7378 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7379 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7380
<> 144:ef7eb2e8f9f7 7381 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 144:ef7eb2e8f9f7 7382 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7383 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7384 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7385 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7386
<> 144:ef7eb2e8f9f7 7387 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 144:ef7eb2e8f9f7 7388 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7389 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7390
<> 144:ef7eb2e8f9f7 7391 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 144:ef7eb2e8f9f7 7392 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7393 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7394 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7395 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
mbed_official 74:9322579e4309 7396
mbed_official 74:9322579e4309 7397 /******************* Bit definition for TIM_CCER register *******************/
<> 144:ef7eb2e8f9f7 7398 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
<> 144:ef7eb2e8f9f7 7399 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
<> 144:ef7eb2e8f9f7 7400 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
<> 144:ef7eb2e8f9f7 7401 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 7402 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
<> 144:ef7eb2e8f9f7 7403 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
<> 144:ef7eb2e8f9f7 7404 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
<> 144:ef7eb2e8f9f7 7405 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 7406 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
<> 144:ef7eb2e8f9f7 7407 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
<> 144:ef7eb2e8f9f7 7408 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
<> 144:ef7eb2e8f9f7 7409 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 7410 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
<> 144:ef7eb2e8f9f7 7411 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
<> 144:ef7eb2e8f9f7 7412 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 7413 #define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */
<> 144:ef7eb2e8f9f7 7414 #define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */
<> 144:ef7eb2e8f9f7 7415 #define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */
<> 144:ef7eb2e8f9f7 7416 #define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */
mbed_official 74:9322579e4309 7417
mbed_official 74:9322579e4309 7418
mbed_official 74:9322579e4309 7419 /******************* Bit definition for TIM_CNT register ********************/
<> 144:ef7eb2e8f9f7 7420 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
mbed_official 74:9322579e4309 7421
mbed_official 74:9322579e4309 7422 /******************* Bit definition for TIM_PSC register ********************/
<> 144:ef7eb2e8f9f7 7423 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
mbed_official 74:9322579e4309 7424
mbed_official 74:9322579e4309 7425 /******************* Bit definition for TIM_ARR register ********************/
<> 144:ef7eb2e8f9f7 7426 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
mbed_official 74:9322579e4309 7427
mbed_official 74:9322579e4309 7428 /******************* Bit definition for TIM_RCR register ********************/
<> 144:ef7eb2e8f9f7 7429 #define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */
mbed_official 74:9322579e4309 7430
mbed_official 74:9322579e4309 7431 /******************* Bit definition for TIM_CCR1 register *******************/
<> 144:ef7eb2e8f9f7 7432 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
mbed_official 74:9322579e4309 7433
mbed_official 74:9322579e4309 7434 /******************* Bit definition for TIM_CCR2 register *******************/
<> 144:ef7eb2e8f9f7 7435 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
mbed_official 74:9322579e4309 7436
mbed_official 74:9322579e4309 7437 /******************* Bit definition for TIM_CCR3 register *******************/
<> 144:ef7eb2e8f9f7 7438 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
mbed_official 74:9322579e4309 7439
mbed_official 74:9322579e4309 7440 /******************* Bit definition for TIM_CCR4 register *******************/
<> 144:ef7eb2e8f9f7 7441 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
mbed_official 74:9322579e4309 7442
mbed_official 74:9322579e4309 7443 /******************* Bit definition for TIM_BDTR register *******************/
<> 144:ef7eb2e8f9f7 7444 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 144:ef7eb2e8f9f7 7445 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7446 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7447 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7448 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7449 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7450 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7451 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 7452 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 7453
<> 144:ef7eb2e8f9f7 7454 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 144:ef7eb2e8f9f7 7455 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7456 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7457
<> 144:ef7eb2e8f9f7 7458 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
<> 144:ef7eb2e8f9f7 7459 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
<> 144:ef7eb2e8f9f7 7460 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
<> 144:ef7eb2e8f9f7 7461 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
<> 144:ef7eb2e8f9f7 7462 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
<> 144:ef7eb2e8f9f7 7463 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
<> 144:ef7eb2e8f9f7 7464 #define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */
<> 144:ef7eb2e8f9f7 7465 #define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */
<> 144:ef7eb2e8f9f7 7466 #define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */
<> 144:ef7eb2e8f9f7 7467 #define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */
mbed_official 74:9322579e4309 7468
mbed_official 74:9322579e4309 7469 /******************* Bit definition for TIM_DCR register ********************/
<> 144:ef7eb2e8f9f7 7470 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 144:ef7eb2e8f9f7 7471 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7472 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7473 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7474 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7475 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7476
<> 144:ef7eb2e8f9f7 7477 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 144:ef7eb2e8f9f7 7478 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7479 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7480 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7481 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7482 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
mbed_official 74:9322579e4309 7483
mbed_official 74:9322579e4309 7484 /******************* Bit definition for TIM_DMAR register *******************/
<> 144:ef7eb2e8f9f7 7485 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 7486
<> 144:ef7eb2e8f9f7 7487 /******************* Bit definition for TIM_OR regiter *********************/
<> 144:ef7eb2e8f9f7 7488 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 144:ef7eb2e8f9f7 7489 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7490 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7491 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 144:ef7eb2e8f9f7 7492 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7493 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
mbed_official 74:9322579e4309 7494
mbed_official 74:9322579e4309 7495 /****************** Bit definition for TIM_CCMR3 register *******************/
<> 144:ef7eb2e8f9f7 7496 #define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */
<> 144:ef7eb2e8f9f7 7497 #define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */
<> 144:ef7eb2e8f9f7 7498
<> 144:ef7eb2e8f9f7 7499 #define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
<> 144:ef7eb2e8f9f7 7500 #define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7501 #define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7502 #define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7503 #define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7504
<> 144:ef7eb2e8f9f7 7505 #define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */
<> 144:ef7eb2e8f9f7 7506
<> 144:ef7eb2e8f9f7 7507 #define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */
<> 144:ef7eb2e8f9f7 7508 #define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */
<> 144:ef7eb2e8f9f7 7509
<> 144:ef7eb2e8f9f7 7510 #define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 144:ef7eb2e8f9f7 7511 #define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7512 #define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7513 #define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7514 #define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7515
<> 144:ef7eb2e8f9f7 7516 #define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */
mbed_official 74:9322579e4309 7517
mbed_official 74:9322579e4309 7518 /******************* Bit definition for TIM_CCR5 register *******************/
<> 144:ef7eb2e8f9f7 7519 #define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */
<> 144:ef7eb2e8f9f7 7520 #define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */
<> 144:ef7eb2e8f9f7 7521 #define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */
<> 144:ef7eb2e8f9f7 7522 #define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */
mbed_official 74:9322579e4309 7523
mbed_official 74:9322579e4309 7524 /******************* Bit definition for TIM_CCR6 register *******************/
<> 144:ef7eb2e8f9f7 7525 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
mbed_official 74:9322579e4309 7526
mbed_official 83:a036322b8637 7527
mbed_official 74:9322579e4309 7528 /******************************************************************************/
mbed_official 74:9322579e4309 7529 /* */
mbed_official 74:9322579e4309 7530 /* Low Power Timer (LPTIM) */
mbed_official 74:9322579e4309 7531 /* */
mbed_official 74:9322579e4309 7532 /******************************************************************************/
mbed_official 74:9322579e4309 7533 /****************** Bit definition for LPTIM_ISR register *******************/
<> 144:ef7eb2e8f9f7 7534 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
<> 144:ef7eb2e8f9f7 7535 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
<> 144:ef7eb2e8f9f7 7536 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
<> 144:ef7eb2e8f9f7 7537 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
<> 144:ef7eb2e8f9f7 7538 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
<> 144:ef7eb2e8f9f7 7539 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
<> 144:ef7eb2e8f9f7 7540 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
mbed_official 74:9322579e4309 7541
mbed_official 74:9322579e4309 7542 /****************** Bit definition for LPTIM_ICR register *******************/
<> 144:ef7eb2e8f9f7 7543 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
<> 144:ef7eb2e8f9f7 7544 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
<> 144:ef7eb2e8f9f7 7545 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
<> 144:ef7eb2e8f9f7 7546 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
<> 144:ef7eb2e8f9f7 7547 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
<> 144:ef7eb2e8f9f7 7548 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
<> 144:ef7eb2e8f9f7 7549 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
<> 144:ef7eb2e8f9f7 7550
<> 144:ef7eb2e8f9f7 7551 /****************** Bit definition for LPTIM_IER register *******************/
<> 144:ef7eb2e8f9f7 7552 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
<> 144:ef7eb2e8f9f7 7553 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
<> 144:ef7eb2e8f9f7 7554 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
<> 144:ef7eb2e8f9f7 7555 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
<> 144:ef7eb2e8f9f7 7556 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
<> 144:ef7eb2e8f9f7 7557 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
<> 144:ef7eb2e8f9f7 7558 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
<> 144:ef7eb2e8f9f7 7559
<> 144:ef7eb2e8f9f7 7560 /****************** Bit definition for LPTIM_CFGR register*******************/
<> 144:ef7eb2e8f9f7 7561 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
<> 144:ef7eb2e8f9f7 7562
<> 144:ef7eb2e8f9f7 7563 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
<> 144:ef7eb2e8f9f7 7564 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7565 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7566
<> 144:ef7eb2e8f9f7 7567 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 144:ef7eb2e8f9f7 7568 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7569 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7570
<> 144:ef7eb2e8f9f7 7571 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 144:ef7eb2e8f9f7 7572 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7573 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7574
<> 144:ef7eb2e8f9f7 7575 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
<> 144:ef7eb2e8f9f7 7576 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7577 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7578 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 7579
<> 144:ef7eb2e8f9f7 7580 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 144:ef7eb2e8f9f7 7581 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7582 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7583 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 7584
<> 144:ef7eb2e8f9f7 7585 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 144:ef7eb2e8f9f7 7586 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7587 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7588
<> 144:ef7eb2e8f9f7 7589 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
<> 144:ef7eb2e8f9f7 7590 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
<> 144:ef7eb2e8f9f7 7591 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
<> 144:ef7eb2e8f9f7 7592 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
<> 144:ef7eb2e8f9f7 7593 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
<> 144:ef7eb2e8f9f7 7594 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
mbed_official 74:9322579e4309 7595
mbed_official 74:9322579e4309 7596 /****************** Bit definition for LPTIM_CR register ********************/
<> 144:ef7eb2e8f9f7 7597 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
<> 144:ef7eb2e8f9f7 7598 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
<> 144:ef7eb2e8f9f7 7599 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
<> 144:ef7eb2e8f9f7 7600
<> 144:ef7eb2e8f9f7 7601 /****************** Bit definition for LPTIM_CMP register *******************/
<> 144:ef7eb2e8f9f7 7602 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
<> 144:ef7eb2e8f9f7 7603
<> 144:ef7eb2e8f9f7 7604 /****************** Bit definition for LPTIM_ARR register *******************/
<> 144:ef7eb2e8f9f7 7605 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
<> 144:ef7eb2e8f9f7 7606
<> 144:ef7eb2e8f9f7 7607 /****************** Bit definition for LPTIM_CNT register *******************/
<> 144:ef7eb2e8f9f7 7608 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
mbed_official 74:9322579e4309 7609 /******************************************************************************/
mbed_official 74:9322579e4309 7610 /* */
mbed_official 74:9322579e4309 7611 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 74:9322579e4309 7612 /* */
mbed_official 74:9322579e4309 7613 /******************************************************************************/
mbed_official 74:9322579e4309 7614 /****************** Bit definition for USART_CR1 register *******************/
<> 144:ef7eb2e8f9f7 7615 #define USART_CR1_UE 0x00000001U /*!< USART Enable */
<> 144:ef7eb2e8f9f7 7616 #define USART_CR1_RE 0x00000004U /*!< Receiver Enable */
<> 144:ef7eb2e8f9f7 7617 #define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */
<> 144:ef7eb2e8f9f7 7618 #define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */
<> 144:ef7eb2e8f9f7 7619 #define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */
<> 144:ef7eb2e8f9f7 7620 #define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */
<> 144:ef7eb2e8f9f7 7621 #define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */
<> 144:ef7eb2e8f9f7 7622 #define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */
<> 144:ef7eb2e8f9f7 7623 #define USART_CR1_PS 0x00000200U /*!< Parity Selection */
<> 144:ef7eb2e8f9f7 7624 #define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */
<> 144:ef7eb2e8f9f7 7625 #define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */
<> 144:ef7eb2e8f9f7 7626 #define USART_CR1_M 0x10001000U /*!< Word length */
<> 144:ef7eb2e8f9f7 7627 #define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */
<> 144:ef7eb2e8f9f7 7628 #define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */
<> 144:ef7eb2e8f9f7 7629 #define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */
<> 144:ef7eb2e8f9f7 7630 #define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */
<> 144:ef7eb2e8f9f7 7631 #define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 144:ef7eb2e8f9f7 7632 #define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7633 #define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7634 #define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 7635 #define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 7636 #define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 7637 #define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 144:ef7eb2e8f9f7 7638 #define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7639 #define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7640 #define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */
<> 144:ef7eb2e8f9f7 7641 #define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */
<> 144:ef7eb2e8f9f7 7642 #define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */
<> 144:ef7eb2e8f9f7 7643 #define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */
<> 144:ef7eb2e8f9f7 7644 #define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */
<> 144:ef7eb2e8f9f7 7645 #define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */
mbed_official 74:9322579e4309 7646
mbed_official 74:9322579e4309 7647 /****************** Bit definition for USART_CR2 register *******************/
<> 144:ef7eb2e8f9f7 7648 #define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */
<> 144:ef7eb2e8f9f7 7649 #define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */
<> 144:ef7eb2e8f9f7 7650 #define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */
<> 144:ef7eb2e8f9f7 7651 #define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */
<> 144:ef7eb2e8f9f7 7652 #define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */
<> 144:ef7eb2e8f9f7 7653 #define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */
<> 144:ef7eb2e8f9f7 7654 #define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */
<> 144:ef7eb2e8f9f7 7655 #define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */
<> 144:ef7eb2e8f9f7 7656 #define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7657 #define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7658 #define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */
<> 144:ef7eb2e8f9f7 7659 #define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */
<> 144:ef7eb2e8f9f7 7660 #define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */
<> 144:ef7eb2e8f9f7 7661 #define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */
<> 144:ef7eb2e8f9f7 7662 #define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */
<> 144:ef7eb2e8f9f7 7663 #define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */
<> 144:ef7eb2e8f9f7 7664 #define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */
<> 144:ef7eb2e8f9f7 7665 #define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 144:ef7eb2e8f9f7 7666 #define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7667 #define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7668 #define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */
<> 144:ef7eb2e8f9f7 7669 #define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */
mbed_official 74:9322579e4309 7670
mbed_official 74:9322579e4309 7671 /****************** Bit definition for USART_CR3 register *******************/
<> 144:ef7eb2e8f9f7 7672 #define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 7673 #define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */
<> 144:ef7eb2e8f9f7 7674 #define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */
<> 144:ef7eb2e8f9f7 7675 #define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */
<> 144:ef7eb2e8f9f7 7676 #define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */
<> 144:ef7eb2e8f9f7 7677 #define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */
<> 144:ef7eb2e8f9f7 7678 #define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */
<> 144:ef7eb2e8f9f7 7679 #define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */
<> 144:ef7eb2e8f9f7 7680 #define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */
<> 144:ef7eb2e8f9f7 7681 #define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */
<> 144:ef7eb2e8f9f7 7682 #define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */
<> 144:ef7eb2e8f9f7 7683 #define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */
<> 144:ef7eb2e8f9f7 7684 #define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */
<> 144:ef7eb2e8f9f7 7685 #define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */
<> 144:ef7eb2e8f9f7 7686 #define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */
<> 144:ef7eb2e8f9f7 7687 #define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */
<> 144:ef7eb2e8f9f7 7688 #define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 144:ef7eb2e8f9f7 7689 #define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */
<> 144:ef7eb2e8f9f7 7690 #define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */
<> 144:ef7eb2e8f9f7 7691 #define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */
mbed_official 74:9322579e4309 7692
mbed_official 83:a036322b8637 7693
mbed_official 74:9322579e4309 7694 /****************** Bit definition for USART_BRR register *******************/
<> 144:ef7eb2e8f9f7 7695 #define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */
<> 144:ef7eb2e8f9f7 7696 #define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */
mbed_official 74:9322579e4309 7697
mbed_official 74:9322579e4309 7698 /****************** Bit definition for USART_GTPR register ******************/
<> 144:ef7eb2e8f9f7 7699 #define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */
<> 144:ef7eb2e8f9f7 7700 #define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */
mbed_official 74:9322579e4309 7701
mbed_official 74:9322579e4309 7702
mbed_official 74:9322579e4309 7703 /******************* Bit definition for USART_RTOR register *****************/
<> 144:ef7eb2e8f9f7 7704 #define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */
<> 144:ef7eb2e8f9f7 7705 #define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */
mbed_official 74:9322579e4309 7706
mbed_official 74:9322579e4309 7707 /******************* Bit definition for USART_RQR register ******************/
<> 144:ef7eb2e8f9f7 7708 #define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */
<> 144:ef7eb2e8f9f7 7709 #define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */
<> 144:ef7eb2e8f9f7 7710 #define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */
<> 144:ef7eb2e8f9f7 7711 #define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 7712 #define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */
mbed_official 74:9322579e4309 7713
mbed_official 74:9322579e4309 7714 /******************* Bit definition for USART_ISR register ******************/
<> 144:ef7eb2e8f9f7 7715 #define USART_ISR_PE 0x00000001U /*!< Parity Error */
<> 144:ef7eb2e8f9f7 7716 #define USART_ISR_FE 0x00000002U /*!< Framing Error */
<> 144:ef7eb2e8f9f7 7717 #define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */
<> 144:ef7eb2e8f9f7 7718 #define USART_ISR_ORE 0x00000008U /*!< OverRun Error */
<> 144:ef7eb2e8f9f7 7719 #define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */
<> 144:ef7eb2e8f9f7 7720 #define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */
<> 144:ef7eb2e8f9f7 7721 #define USART_ISR_TC 0x00000040U /*!< Transmission Complete */
<> 144:ef7eb2e8f9f7 7722 #define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */
<> 144:ef7eb2e8f9f7 7723 #define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */
<> 144:ef7eb2e8f9f7 7724 #define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */
<> 144:ef7eb2e8f9f7 7725 #define USART_ISR_CTS 0x00000400U /*!< CTS flag */
<> 144:ef7eb2e8f9f7 7726 #define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */
<> 144:ef7eb2e8f9f7 7727 #define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */
<> 144:ef7eb2e8f9f7 7728 #define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */
<> 144:ef7eb2e8f9f7 7729 #define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */
<> 144:ef7eb2e8f9f7 7730 #define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */
<> 144:ef7eb2e8f9f7 7731 #define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */
<> 144:ef7eb2e8f9f7 7732 #define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */
<> 144:ef7eb2e8f9f7 7733 #define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */
<> 144:ef7eb2e8f9f7 7734 #define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */
<> 144:ef7eb2e8f9f7 7735 #define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */
<> 144:ef7eb2e8f9f7 7736 #define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */
<> 144:ef7eb2e8f9f7 7737
<> 144:ef7eb2e8f9f7 7738 /* Legacy define */
<> 144:ef7eb2e8f9f7 7739 #define USART_ISR_LBD USART_ISR_LBDF
mbed_official 74:9322579e4309 7740
mbed_official 74:9322579e4309 7741 /******************* Bit definition for USART_ICR register ******************/
<> 144:ef7eb2e8f9f7 7742 #define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */
<> 144:ef7eb2e8f9f7 7743 #define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */
<> 144:ef7eb2e8f9f7 7744 #define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */
<> 144:ef7eb2e8f9f7 7745 #define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */
<> 144:ef7eb2e8f9f7 7746 #define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */
<> 144:ef7eb2e8f9f7 7747 #define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 7748 #define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */
<> 144:ef7eb2e8f9f7 7749 #define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */
<> 144:ef7eb2e8f9f7 7750 #define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */
<> 144:ef7eb2e8f9f7 7751 #define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */
<> 144:ef7eb2e8f9f7 7752 #define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */
<> 144:ef7eb2e8f9f7 7753 #define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */
mbed_official 74:9322579e4309 7754
mbed_official 74:9322579e4309 7755 /******************* Bit definition for USART_RDR register ******************/
<> 144:ef7eb2e8f9f7 7756 #define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 74:9322579e4309 7757
mbed_official 74:9322579e4309 7758 /******************* Bit definition for USART_TDR register ******************/
<> 144:ef7eb2e8f9f7 7759 #define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 74:9322579e4309 7760
mbed_official 74:9322579e4309 7761 /******************************************************************************/
mbed_official 74:9322579e4309 7762 /* */
mbed_official 74:9322579e4309 7763 /* Window WATCHDOG */
mbed_official 74:9322579e4309 7764 /* */
mbed_official 74:9322579e4309 7765 /******************************************************************************/
mbed_official 74:9322579e4309 7766 /******************* Bit definition for WWDG_CR register ********************/
<> 144:ef7eb2e8f9f7 7767 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 144:ef7eb2e8f9f7 7768 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7769 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7770 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7771 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7772 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7773 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7774 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
mbed_official 83:a036322b8637 7775
mbed_official 83:a036322b8637 7776 /* Legacy defines */
mbed_official 83:a036322b8637 7777 #define WWDG_CR_T0 WWDG_CR_T_0 /*!<Bit 0 */
mbed_official 83:a036322b8637 7778 #define WWDG_CR_T1 WWDG_CR_T_1 /*!<Bit 1 */
mbed_official 83:a036322b8637 7779 #define WWDG_CR_T2 WWDG_CR_T_2 /*!<Bit 2 */
mbed_official 83:a036322b8637 7780 #define WWDG_CR_T3 WWDG_CR_T_3 /*!<Bit 3 */
mbed_official 83:a036322b8637 7781 #define WWDG_CR_T4 WWDG_CR_T_4 /*!<Bit 4 */
mbed_official 83:a036322b8637 7782 #define WWDG_CR_T5 WWDG_CR_T_5 /*!<Bit 5 */
mbed_official 83:a036322b8637 7783 #define WWDG_CR_T6 WWDG_CR_T_6 /*!<Bit 6 */
mbed_official 83:a036322b8637 7784
<> 144:ef7eb2e8f9f7 7785 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
mbed_official 74:9322579e4309 7786
mbed_official 74:9322579e4309 7787 /******************* Bit definition for WWDG_CFR register *******************/
<> 144:ef7eb2e8f9f7 7788 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
<> 144:ef7eb2e8f9f7 7789 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7790 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 7791 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 7792 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 7793 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 7794 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 7795 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
mbed_official 83:a036322b8637 7796
mbed_official 83:a036322b8637 7797 /* Legacy defines */
mbed_official 83:a036322b8637 7798 #define WWDG_CFR_W0 WWDG_CFR_W_0 /*!<Bit 0 */
mbed_official 83:a036322b8637 7799 #define WWDG_CFR_W1 WWDG_CFR_W_1 /*!<Bit 1 */
mbed_official 83:a036322b8637 7800 #define WWDG_CFR_W2 WWDG_CFR_W_2 /*!<Bit 2 */
mbed_official 83:a036322b8637 7801 #define WWDG_CFR_W3 WWDG_CFR_W_3 /*!<Bit 3 */
mbed_official 83:a036322b8637 7802 #define WWDG_CFR_W4 WWDG_CFR_W_4 /*!<Bit 4 */
mbed_official 83:a036322b8637 7803 #define WWDG_CFR_W5 WWDG_CFR_W_5 /*!<Bit 5 */
mbed_official 83:a036322b8637 7804 #define WWDG_CFR_W6 WWDG_CFR_W_6 /*!<Bit 6 */
mbed_official 83:a036322b8637 7805
<> 144:ef7eb2e8f9f7 7806 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 144:ef7eb2e8f9f7 7807 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7808 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
mbed_official 83:a036322b8637 7809
mbed_official 83:a036322b8637 7810 /* Legacy defines */
mbed_official 83:a036322b8637 7811 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /*!<Bit 0 */
mbed_official 83:a036322b8637 7812 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /*!<Bit 1 */
mbed_official 83:a036322b8637 7813
<> 144:ef7eb2e8f9f7 7814 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
mbed_official 74:9322579e4309 7815
mbed_official 74:9322579e4309 7816 /******************* Bit definition for WWDG_SR register ********************/
<> 144:ef7eb2e8f9f7 7817 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
mbed_official 74:9322579e4309 7818
mbed_official 74:9322579e4309 7819 /******************************************************************************/
mbed_official 74:9322579e4309 7820 /* */
mbed_official 74:9322579e4309 7821 /* DBG */
mbed_official 74:9322579e4309 7822 /* */
mbed_official 74:9322579e4309 7823 /******************************************************************************/
mbed_official 74:9322579e4309 7824 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 144:ef7eb2e8f9f7 7825 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 144:ef7eb2e8f9f7 7826 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
mbed_official 74:9322579e4309 7827
mbed_official 74:9322579e4309 7828 /******************** Bit definition for DBGMCU_CR register *****************/
<> 144:ef7eb2e8f9f7 7829 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 144:ef7eb2e8f9f7 7830 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 7831 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 144:ef7eb2e8f9f7 7832 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 144:ef7eb2e8f9f7 7833
<> 144:ef7eb2e8f9f7 7834 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 144:ef7eb2e8f9f7 7835 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 7836 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */
mbed_official 74:9322579e4309 7837
mbed_official 74:9322579e4309 7838 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 144:ef7eb2e8f9f7 7839 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 7840 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 7841 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
<> 144:ef7eb2e8f9f7 7842 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 144:ef7eb2e8f9f7 7843 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 144:ef7eb2e8f9f7 7844 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
<> 144:ef7eb2e8f9f7 7845 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
<> 144:ef7eb2e8f9f7 7846 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
<> 144:ef7eb2e8f9f7 7847 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
<> 144:ef7eb2e8f9f7 7848 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 144:ef7eb2e8f9f7 7849 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 144:ef7eb2e8f9f7 7850 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 144:ef7eb2e8f9f7 7851 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 144:ef7eb2e8f9f7 7852 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 144:ef7eb2e8f9f7 7853 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
<> 144:ef7eb2e8f9f7 7854 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 144:ef7eb2e8f9f7 7855 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
mbed_official 74:9322579e4309 7856
mbed_official 74:9322579e4309 7857 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 144:ef7eb2e8f9f7 7858 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 144:ef7eb2e8f9f7 7859 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
<> 144:ef7eb2e8f9f7 7860 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 144:ef7eb2e8f9f7 7861 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
<> 144:ef7eb2e8f9f7 7862 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
mbed_official 74:9322579e4309 7863
mbed_official 74:9322579e4309 7864 /******************************************************************************/
mbed_official 74:9322579e4309 7865 /* */
mbed_official 74:9322579e4309 7866 /* Ethernet MAC Registers bits definitions */
mbed_official 74:9322579e4309 7867 /* */
mbed_official 74:9322579e4309 7868 /******************************************************************************/
mbed_official 74:9322579e4309 7869 /* Bit definition for Ethernet MAC Control Register register */
<> 144:ef7eb2e8f9f7 7870 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
<> 144:ef7eb2e8f9f7 7871 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
<> 144:ef7eb2e8f9f7 7872 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
<> 144:ef7eb2e8f9f7 7873 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
<> 144:ef7eb2e8f9f7 7874 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
<> 144:ef7eb2e8f9f7 7875 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
<> 144:ef7eb2e8f9f7 7876 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
<> 144:ef7eb2e8f9f7 7877 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
<> 144:ef7eb2e8f9f7 7878 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
<> 144:ef7eb2e8f9f7 7879 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
<> 144:ef7eb2e8f9f7 7880 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
<> 144:ef7eb2e8f9f7 7881 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
<> 144:ef7eb2e8f9f7 7882 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
<> 144:ef7eb2e8f9f7 7883 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
<> 144:ef7eb2e8f9f7 7884 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
<> 144:ef7eb2e8f9f7 7885 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
<> 144:ef7eb2e8f9f7 7886 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
<> 144:ef7eb2e8f9f7 7887 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
<> 144:ef7eb2e8f9f7 7888 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
<> 144:ef7eb2e8f9f7 7889 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
mbed_official 74:9322579e4309 7890 a transmission attempt during retries after a collision: 0 =< r <2^k */
<> 144:ef7eb2e8f9f7 7891 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
<> 144:ef7eb2e8f9f7 7892 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
<> 144:ef7eb2e8f9f7 7893 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
<> 144:ef7eb2e8f9f7 7894 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
<> 144:ef7eb2e8f9f7 7895 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
<> 144:ef7eb2e8f9f7 7896 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
<> 144:ef7eb2e8f9f7 7897 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
mbed_official 74:9322579e4309 7898
mbed_official 74:9322579e4309 7899 /* Bit definition for Ethernet MAC Frame Filter Register */
<> 144:ef7eb2e8f9f7 7900 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
<> 144:ef7eb2e8f9f7 7901 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
<> 144:ef7eb2e8f9f7 7902 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
<> 144:ef7eb2e8f9f7 7903 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
<> 144:ef7eb2e8f9f7 7904 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
<> 144:ef7eb2e8f9f7 7905 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
<> 144:ef7eb2e8f9f7 7906 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
<> 144:ef7eb2e8f9f7 7907 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
<> 144:ef7eb2e8f9f7 7908 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
<> 144:ef7eb2e8f9f7 7909 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
<> 144:ef7eb2e8f9f7 7910 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
<> 144:ef7eb2e8f9f7 7911 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
<> 144:ef7eb2e8f9f7 7912 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
<> 144:ef7eb2e8f9f7 7913 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
mbed_official 74:9322579e4309 7914
mbed_official 74:9322579e4309 7915 /* Bit definition for Ethernet MAC Hash Table High Register */
<> 144:ef7eb2e8f9f7 7916 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
mbed_official 74:9322579e4309 7917
mbed_official 74:9322579e4309 7918 /* Bit definition for Ethernet MAC Hash Table Low Register */
<> 144:ef7eb2e8f9f7 7919 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
mbed_official 74:9322579e4309 7920
mbed_official 74:9322579e4309 7921 /* Bit definition for Ethernet MAC MII Address Register */
<> 144:ef7eb2e8f9f7 7922 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
<> 144:ef7eb2e8f9f7 7923 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
<> 144:ef7eb2e8f9f7 7924 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
<> 144:ef7eb2e8f9f7 7925 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
<> 144:ef7eb2e8f9f7 7926 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
<> 144:ef7eb2e8f9f7 7927 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
<> 144:ef7eb2e8f9f7 7928 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
<> 144:ef7eb2e8f9f7 7929 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
<> 144:ef7eb2e8f9f7 7930 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
<> 144:ef7eb2e8f9f7 7931 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
mbed_official 74:9322579e4309 7932
mbed_official 74:9322579e4309 7933 /* Bit definition for Ethernet MAC MII Data Register */
<> 144:ef7eb2e8f9f7 7934 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
mbed_official 74:9322579e4309 7935
mbed_official 74:9322579e4309 7936 /* Bit definition for Ethernet MAC Flow Control Register */
<> 144:ef7eb2e8f9f7 7937 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
<> 144:ef7eb2e8f9f7 7938 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
<> 144:ef7eb2e8f9f7 7939 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
<> 144:ef7eb2e8f9f7 7940 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
<> 144:ef7eb2e8f9f7 7941 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
<> 144:ef7eb2e8f9f7 7942 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
<> 144:ef7eb2e8f9f7 7943 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
<> 144:ef7eb2e8f9f7 7944 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
<> 144:ef7eb2e8f9f7 7945 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
<> 144:ef7eb2e8f9f7 7946 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
<> 144:ef7eb2e8f9f7 7947 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
mbed_official 74:9322579e4309 7948
mbed_official 74:9322579e4309 7949 /* Bit definition for Ethernet MAC VLAN Tag Register */
<> 144:ef7eb2e8f9f7 7950 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
<> 144:ef7eb2e8f9f7 7951 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
mbed_official 74:9322579e4309 7952
mbed_official 74:9322579e4309 7953 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
<> 144:ef7eb2e8f9f7 7954 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
mbed_official 74:9322579e4309 7955 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
mbed_official 74:9322579e4309 7956 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
mbed_official 74:9322579e4309 7957 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
mbed_official 74:9322579e4309 7958 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
mbed_official 74:9322579e4309 7959 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
mbed_official 74:9322579e4309 7960 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
mbed_official 74:9322579e4309 7961 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
mbed_official 74:9322579e4309 7962 RSVD - Filter1 Command - RSVD - Filter0 Command
mbed_official 74:9322579e4309 7963 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
mbed_official 74:9322579e4309 7964 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
mbed_official 74:9322579e4309 7965 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
mbed_official 74:9322579e4309 7966
mbed_official 74:9322579e4309 7967 /* Bit definition for Ethernet MAC PMT Control and Status Register */
<> 144:ef7eb2e8f9f7 7968 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
<> 144:ef7eb2e8f9f7 7969 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
<> 144:ef7eb2e8f9f7 7970 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
<> 144:ef7eb2e8f9f7 7971 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
<> 144:ef7eb2e8f9f7 7972 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
<> 144:ef7eb2e8f9f7 7973 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
<> 144:ef7eb2e8f9f7 7974 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
mbed_official 74:9322579e4309 7975
mbed_official 74:9322579e4309 7976 /* Bit definition for Ethernet MAC Status Register */
<> 144:ef7eb2e8f9f7 7977 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
<> 144:ef7eb2e8f9f7 7978 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
<> 144:ef7eb2e8f9f7 7979 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
<> 144:ef7eb2e8f9f7 7980 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
<> 144:ef7eb2e8f9f7 7981 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
mbed_official 74:9322579e4309 7982
mbed_official 74:9322579e4309 7983 /* Bit definition for Ethernet MAC Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 7984 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
<> 144:ef7eb2e8f9f7 7985 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
mbed_official 74:9322579e4309 7986
mbed_official 74:9322579e4309 7987 /* Bit definition for Ethernet MAC Address0 High Register */
<> 144:ef7eb2e8f9f7 7988 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
mbed_official 74:9322579e4309 7989
mbed_official 74:9322579e4309 7990 /* Bit definition for Ethernet MAC Address0 Low Register */
<> 144:ef7eb2e8f9f7 7991 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
mbed_official 74:9322579e4309 7992
mbed_official 74:9322579e4309 7993 /* Bit definition for Ethernet MAC Address1 High Register */
<> 144:ef7eb2e8f9f7 7994 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 7995 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 7996 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
<> 144:ef7eb2e8f9f7 7997 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 7998 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 7999 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 8000 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 8001 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 8002 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
<> 144:ef7eb2e8f9f7 8003 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
mbed_official 74:9322579e4309 8004
mbed_official 74:9322579e4309 8005 /* Bit definition for Ethernet MAC Address1 Low Register */
<> 144:ef7eb2e8f9f7 8006 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
mbed_official 74:9322579e4309 8007
mbed_official 74:9322579e4309 8008 /* Bit definition for Ethernet MAC Address2 High Register */
<> 144:ef7eb2e8f9f7 8009 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 8010 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 8011 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
<> 144:ef7eb2e8f9f7 8012 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 8013 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 8014 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 8015 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 8016 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 8017 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 8018 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
mbed_official 74:9322579e4309 8019
mbed_official 74:9322579e4309 8020 /* Bit definition for Ethernet MAC Address2 Low Register */
<> 144:ef7eb2e8f9f7 8021 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
mbed_official 74:9322579e4309 8022
mbed_official 74:9322579e4309 8023 /* Bit definition for Ethernet MAC Address3 High Register */
<> 144:ef7eb2e8f9f7 8024 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
<> 144:ef7eb2e8f9f7 8025 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
<> 144:ef7eb2e8f9f7 8026 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
<> 144:ef7eb2e8f9f7 8027 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 8028 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 8029 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 8030 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 8031 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 8032 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 8033 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
mbed_official 74:9322579e4309 8034
mbed_official 74:9322579e4309 8035 /* Bit definition for Ethernet MAC Address3 Low Register */
<> 144:ef7eb2e8f9f7 8036 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
mbed_official 74:9322579e4309 8037
mbed_official 74:9322579e4309 8038 /******************************************************************************/
mbed_official 74:9322579e4309 8039 /* Ethernet MMC Registers bits definition */
mbed_official 74:9322579e4309 8040 /******************************************************************************/
mbed_official 74:9322579e4309 8041
mbed_official 74:9322579e4309 8042 /* Bit definition for Ethernet MMC Contol Register */
<> 144:ef7eb2e8f9f7 8043 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
<> 144:ef7eb2e8f9f7 8044 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
<> 144:ef7eb2e8f9f7 8045 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
<> 144:ef7eb2e8f9f7 8046 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
<> 144:ef7eb2e8f9f7 8047 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
<> 144:ef7eb2e8f9f7 8048 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
mbed_official 74:9322579e4309 8049
mbed_official 74:9322579e4309 8050 /* Bit definition for Ethernet MMC Receive Interrupt Register */
<> 144:ef7eb2e8f9f7 8051 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8052 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8053 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
mbed_official 74:9322579e4309 8054
mbed_official 74:9322579e4309 8055 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
<> 144:ef7eb2e8f9f7 8056 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8057 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8058 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
mbed_official 74:9322579e4309 8059
mbed_official 74:9322579e4309 8060 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 8061 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8062 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8063 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
mbed_official 74:9322579e4309 8064
mbed_official 74:9322579e4309 8065 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 8066 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8067 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 8068 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
mbed_official 74:9322579e4309 8069
mbed_official 74:9322579e4309 8070 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
<> 144:ef7eb2e8f9f7 8071 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
mbed_official 74:9322579e4309 8072
mbed_official 74:9322579e4309 8073 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
<> 144:ef7eb2e8f9f7 8074 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
mbed_official 74:9322579e4309 8075
mbed_official 74:9322579e4309 8076 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
<> 144:ef7eb2e8f9f7 8077 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
mbed_official 74:9322579e4309 8078
mbed_official 74:9322579e4309 8079 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
<> 144:ef7eb2e8f9f7 8080 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
mbed_official 74:9322579e4309 8081
mbed_official 74:9322579e4309 8082 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
<> 144:ef7eb2e8f9f7 8083 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
mbed_official 74:9322579e4309 8084
mbed_official 74:9322579e4309 8085 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
<> 144:ef7eb2e8f9f7 8086 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
mbed_official 74:9322579e4309 8087
mbed_official 74:9322579e4309 8088 /******************************************************************************/
mbed_official 74:9322579e4309 8089 /* Ethernet PTP Registers bits definition */
mbed_official 74:9322579e4309 8090 /******************************************************************************/
mbed_official 74:9322579e4309 8091
mbed_official 74:9322579e4309 8092 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
<> 144:ef7eb2e8f9f7 8093 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
<> 144:ef7eb2e8f9f7 8094 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
<> 144:ef7eb2e8f9f7 8095 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
<> 144:ef7eb2e8f9f7 8096 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
<> 144:ef7eb2e8f9f7 8097 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
<> 144:ef7eb2e8f9f7 8098 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
<> 144:ef7eb2e8f9f7 8099 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
<> 144:ef7eb2e8f9f7 8100 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
<> 144:ef7eb2e8f9f7 8101 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
<> 144:ef7eb2e8f9f7 8102
<> 144:ef7eb2e8f9f7 8103 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
<> 144:ef7eb2e8f9f7 8104 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
<> 144:ef7eb2e8f9f7 8105 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
<> 144:ef7eb2e8f9f7 8106 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
<> 144:ef7eb2e8f9f7 8107 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
<> 144:ef7eb2e8f9f7 8108 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
mbed_official 74:9322579e4309 8109
mbed_official 74:9322579e4309 8110 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
<> 144:ef7eb2e8f9f7 8111 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
mbed_official 74:9322579e4309 8112
mbed_official 74:9322579e4309 8113 /* Bit definition for Ethernet PTP Time Stamp High Register */
<> 144:ef7eb2e8f9f7 8114 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
mbed_official 74:9322579e4309 8115
mbed_official 74:9322579e4309 8116 /* Bit definition for Ethernet PTP Time Stamp Low Register */
<> 144:ef7eb2e8f9f7 8117 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
<> 144:ef7eb2e8f9f7 8118 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
mbed_official 74:9322579e4309 8119
mbed_official 74:9322579e4309 8120 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
<> 144:ef7eb2e8f9f7 8121 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
mbed_official 74:9322579e4309 8122
mbed_official 74:9322579e4309 8123 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
<> 144:ef7eb2e8f9f7 8124 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
<> 144:ef7eb2e8f9f7 8125 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
mbed_official 74:9322579e4309 8126
mbed_official 74:9322579e4309 8127 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
<> 144:ef7eb2e8f9f7 8128 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
mbed_official 74:9322579e4309 8129
mbed_official 74:9322579e4309 8130 /* Bit definition for Ethernet PTP Target Time High Register */
<> 144:ef7eb2e8f9f7 8131 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
mbed_official 74:9322579e4309 8132
mbed_official 74:9322579e4309 8133 /* Bit definition for Ethernet PTP Target Time Low Register */
<> 144:ef7eb2e8f9f7 8134 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
mbed_official 74:9322579e4309 8135
mbed_official 74:9322579e4309 8136 /* Bit definition for Ethernet PTP Time Stamp Status Register */
<> 144:ef7eb2e8f9f7 8137 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
<> 144:ef7eb2e8f9f7 8138 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
mbed_official 74:9322579e4309 8139
mbed_official 74:9322579e4309 8140 /******************************************************************************/
mbed_official 74:9322579e4309 8141 /* Ethernet DMA Registers bits definition */
mbed_official 74:9322579e4309 8142 /******************************************************************************/
mbed_official 74:9322579e4309 8143
mbed_official 74:9322579e4309 8144 /* Bit definition for Ethernet DMA Bus Mode Register */
<> 144:ef7eb2e8f9f7 8145 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
<> 144:ef7eb2e8f9f7 8146 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
<> 144:ef7eb2e8f9f7 8147 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
<> 144:ef7eb2e8f9f7 8148 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
<> 144:ef7eb2e8f9f7 8149 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 144:ef7eb2e8f9f7 8150 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 144:ef7eb2e8f9f7 8151 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 8152 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 8153 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 8154 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 8155 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 8156 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 8157 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 8158 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 8159 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 144:ef7eb2e8f9f7 8160 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 144:ef7eb2e8f9f7 8161 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
<> 144:ef7eb2e8f9f7 8162 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 8163 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 8164 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 8165 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 8166 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
<> 144:ef7eb2e8f9f7 8167 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
<> 144:ef7eb2e8f9f7 8168 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 144:ef7eb2e8f9f7 8169 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 144:ef7eb2e8f9f7 8170 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 8171 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 8172 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 8173 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 8174 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 8175 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 8176 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 8177 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 8178 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 144:ef7eb2e8f9f7 8179 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 144:ef7eb2e8f9f7 8180 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
<> 144:ef7eb2e8f9f7 8181 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
<> 144:ef7eb2e8f9f7 8182 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
<> 144:ef7eb2e8f9f7 8183 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
mbed_official 74:9322579e4309 8184
mbed_official 74:9322579e4309 8185 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
<> 144:ef7eb2e8f9f7 8186 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
mbed_official 74:9322579e4309 8187
mbed_official 74:9322579e4309 8188 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
<> 144:ef7eb2e8f9f7 8189 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
mbed_official 74:9322579e4309 8190
mbed_official 74:9322579e4309 8191 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 8192 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
mbed_official 74:9322579e4309 8193
mbed_official 74:9322579e4309 8194 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
<> 144:ef7eb2e8f9f7 8195 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
mbed_official 74:9322579e4309 8196
mbed_official 74:9322579e4309 8197 /* Bit definition for Ethernet DMA Status Register */
<> 144:ef7eb2e8f9f7 8198 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
<> 144:ef7eb2e8f9f7 8199 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
<> 144:ef7eb2e8f9f7 8200 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
<> 144:ef7eb2e8f9f7 8201 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
mbed_official 74:9322579e4309 8202 /* combination with EBS[2:0] for GetFlagStatus function */
<> 144:ef7eb2e8f9f7 8203 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
<> 144:ef7eb2e8f9f7 8204 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
<> 144:ef7eb2e8f9f7 8205 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
<> 144:ef7eb2e8f9f7 8206 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
<> 144:ef7eb2e8f9f7 8207 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
<> 144:ef7eb2e8f9f7 8208 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
<> 144:ef7eb2e8f9f7 8209 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
<> 144:ef7eb2e8f9f7 8210 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
<> 144:ef7eb2e8f9f7 8211 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
<> 144:ef7eb2e8f9f7 8212 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
<> 144:ef7eb2e8f9f7 8213 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
<> 144:ef7eb2e8f9f7 8214 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
<> 144:ef7eb2e8f9f7 8215 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
<> 144:ef7eb2e8f9f7 8216 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
<> 144:ef7eb2e8f9f7 8217 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 8218 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
<> 144:ef7eb2e8f9f7 8219 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
<> 144:ef7eb2e8f9f7 8220 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
<> 144:ef7eb2e8f9f7 8221 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
<> 144:ef7eb2e8f9f7 8222 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
<> 144:ef7eb2e8f9f7 8223 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
<> 144:ef7eb2e8f9f7 8224 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
<> 144:ef7eb2e8f9f7 8225 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
<> 144:ef7eb2e8f9f7 8226 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
<> 144:ef7eb2e8f9f7 8227 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
<> 144:ef7eb2e8f9f7 8228 #define ETH_DMASR_RS 0x00000040U /* Receive status */
<> 144:ef7eb2e8f9f7 8229 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
<> 144:ef7eb2e8f9f7 8230 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
<> 144:ef7eb2e8f9f7 8231 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
<> 144:ef7eb2e8f9f7 8232 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
<> 144:ef7eb2e8f9f7 8233 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
<> 144:ef7eb2e8f9f7 8234 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
mbed_official 74:9322579e4309 8235
mbed_official 74:9322579e4309 8236 /* Bit definition for Ethernet DMA Operation Mode Register */
<> 144:ef7eb2e8f9f7 8237 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
<> 144:ef7eb2e8f9f7 8238 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
<> 144:ef7eb2e8f9f7 8239 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
<> 144:ef7eb2e8f9f7 8240 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
<> 144:ef7eb2e8f9f7 8241 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
<> 144:ef7eb2e8f9f7 8242 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
<> 144:ef7eb2e8f9f7 8243 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 8244 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 8245 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 144:ef7eb2e8f9f7 8246 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 144:ef7eb2e8f9f7 8247 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 144:ef7eb2e8f9f7 8248 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 8249 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 144:ef7eb2e8f9f7 8250 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 144:ef7eb2e8f9f7 8251 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
<> 144:ef7eb2e8f9f7 8252 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
<> 144:ef7eb2e8f9f7 8253 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
<> 144:ef7eb2e8f9f7 8254 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
<> 144:ef7eb2e8f9f7 8255 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 8256 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 8257 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
<> 144:ef7eb2e8f9f7 8258 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 8259 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
<> 144:ef7eb2e8f9f7 8260 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
mbed_official 74:9322579e4309 8261
mbed_official 74:9322579e4309 8262 /* Bit definition for Ethernet DMA Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 8263 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
<> 144:ef7eb2e8f9f7 8264 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
<> 144:ef7eb2e8f9f7 8265 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
<> 144:ef7eb2e8f9f7 8266 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
<> 144:ef7eb2e8f9f7 8267 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
<> 144:ef7eb2e8f9f7 8268 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
<> 144:ef7eb2e8f9f7 8269 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
<> 144:ef7eb2e8f9f7 8270 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
<> 144:ef7eb2e8f9f7 8271 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
<> 144:ef7eb2e8f9f7 8272 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
<> 144:ef7eb2e8f9f7 8273 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
<> 144:ef7eb2e8f9f7 8274 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
<> 144:ef7eb2e8f9f7 8275 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
<> 144:ef7eb2e8f9f7 8276 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
<> 144:ef7eb2e8f9f7 8277 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
mbed_official 74:9322579e4309 8278
mbed_official 74:9322579e4309 8279 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
<> 144:ef7eb2e8f9f7 8280 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
<> 144:ef7eb2e8f9f7 8281 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
<> 144:ef7eb2e8f9f7 8282 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
<> 144:ef7eb2e8f9f7 8283 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
mbed_official 74:9322579e4309 8284
mbed_official 74:9322579e4309 8285 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
<> 144:ef7eb2e8f9f7 8286 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
mbed_official 74:9322579e4309 8287
mbed_official 74:9322579e4309 8288 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
<> 144:ef7eb2e8f9f7 8289 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
mbed_official 74:9322579e4309 8290
mbed_official 74:9322579e4309 8291 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
<> 144:ef7eb2e8f9f7 8292 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
mbed_official 74:9322579e4309 8293
mbed_official 74:9322579e4309 8294 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
<> 144:ef7eb2e8f9f7 8295 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
mbed_official 74:9322579e4309 8296
mbed_official 74:9322579e4309 8297 /******************************************************************************/
mbed_official 74:9322579e4309 8298 /* */
mbed_official 74:9322579e4309 8299 /* USB_OTG */
mbed_official 74:9322579e4309 8300 /* */
mbed_official 74:9322579e4309 8301 /******************************************************************************/
mbed_official 74:9322579e4309 8302 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
<> 144:ef7eb2e8f9f7 8303 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
<> 144:ef7eb2e8f9f7 8304 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
<> 144:ef7eb2e8f9f7 8305 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
<> 144:ef7eb2e8f9f7 8306 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
<> 144:ef7eb2e8f9f7 8307 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
<> 144:ef7eb2e8f9f7 8308 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
<> 144:ef7eb2e8f9f7 8309 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
<> 144:ef7eb2e8f9f7 8310 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
<> 144:ef7eb2e8f9f7 8311 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
<> 144:ef7eb2e8f9f7 8312 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
<> 144:ef7eb2e8f9f7 8313 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
<> 144:ef7eb2e8f9f7 8314 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
<> 144:ef7eb2e8f9f7 8315 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
<> 144:ef7eb2e8f9f7 8316 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
<> 144:ef7eb2e8f9f7 8317 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
<> 144:ef7eb2e8f9f7 8318 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
<> 144:ef7eb2e8f9f7 8319 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
<> 144:ef7eb2e8f9f7 8320 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
mbed_official 74:9322579e4309 8321
mbed_official 74:9322579e4309 8322 /******************** Bit definition for USB_OTG_HCFG register ********************/
<> 144:ef7eb2e8f9f7 8323 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
<> 144:ef7eb2e8f9f7 8324 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8325 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8326 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
mbed_official 74:9322579e4309 8327
mbed_official 74:9322579e4309 8328 /******************** Bit definition for USB_OTG_DCFG register ********************/
<> 144:ef7eb2e8f9f7 8329 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
<> 144:ef7eb2e8f9f7 8330 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8331 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8332 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
<> 144:ef7eb2e8f9f7 8333
<> 144:ef7eb2e8f9f7 8334 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
<> 144:ef7eb2e8f9f7 8335 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8336 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8337 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8338 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8339 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8340 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8341 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8342
<> 144:ef7eb2e8f9f7 8343 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
<> 144:ef7eb2e8f9f7 8344 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8345 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8346
<> 144:ef7eb2e8f9f7 8347 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
<> 144:ef7eb2e8f9f7 8348 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8349 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 8350
mbed_official 74:9322579e4309 8351 /******************** Bit definition for USB_OTG_PCGCR register ********************/
<> 144:ef7eb2e8f9f7 8352 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
<> 144:ef7eb2e8f9f7 8353 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
<> 144:ef7eb2e8f9f7 8354 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
mbed_official 74:9322579e4309 8355
mbed_official 74:9322579e4309 8356 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
<> 144:ef7eb2e8f9f7 8357 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
<> 144:ef7eb2e8f9f7 8358 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
<> 144:ef7eb2e8f9f7 8359 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
<> 144:ef7eb2e8f9f7 8360 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
<> 144:ef7eb2e8f9f7 8361 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
<> 144:ef7eb2e8f9f7 8362 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
<> 144:ef7eb2e8f9f7 8363 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
mbed_official 74:9322579e4309 8364
mbed_official 74:9322579e4309 8365 /******************** Bit definition for USB_OTG_DCTL register ********************/
<> 144:ef7eb2e8f9f7 8366 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
<> 144:ef7eb2e8f9f7 8367 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
<> 144:ef7eb2e8f9f7 8368 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
<> 144:ef7eb2e8f9f7 8369 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
<> 144:ef7eb2e8f9f7 8370
<> 144:ef7eb2e8f9f7 8371 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
<> 144:ef7eb2e8f9f7 8372 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8373 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8374 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8375 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
<> 144:ef7eb2e8f9f7 8376 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
<> 144:ef7eb2e8f9f7 8377 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
<> 144:ef7eb2e8f9f7 8378 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
<> 144:ef7eb2e8f9f7 8379 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
mbed_official 74:9322579e4309 8380
mbed_official 74:9322579e4309 8381 /******************** Bit definition for USB_OTG_HFIR register ********************/
<> 144:ef7eb2e8f9f7 8382 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
mbed_official 74:9322579e4309 8383
mbed_official 74:9322579e4309 8384 /******************** Bit definition for USB_OTG_HFNUM register ********************/
<> 144:ef7eb2e8f9f7 8385 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
<> 144:ef7eb2e8f9f7 8386 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
mbed_official 74:9322579e4309 8387
mbed_official 74:9322579e4309 8388 /******************** Bit definition for USB_OTG_DSTS register ********************/
<> 144:ef7eb2e8f9f7 8389 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
<> 144:ef7eb2e8f9f7 8390
<> 144:ef7eb2e8f9f7 8391 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
<> 144:ef7eb2e8f9f7 8392 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8393 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8394 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
<> 144:ef7eb2e8f9f7 8395 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
mbed_official 74:9322579e4309 8396
mbed_official 74:9322579e4309 8397 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
<> 144:ef7eb2e8f9f7 8398 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
<> 144:ef7eb2e8f9f7 8399 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
<> 144:ef7eb2e8f9f7 8400 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8401 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8402 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8403 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8404 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
<> 144:ef7eb2e8f9f7 8405 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
<> 144:ef7eb2e8f9f7 8406 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
mbed_official 74:9322579e4309 8407
mbed_official 74:9322579e4309 8408 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
<> 144:ef7eb2e8f9f7 8409 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
<> 144:ef7eb2e8f9f7 8410 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8411 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8412 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8413 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 144:ef7eb2e8f9f7 8414 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
<> 144:ef7eb2e8f9f7 8415 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
<> 144:ef7eb2e8f9f7 8416 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
<> 144:ef7eb2e8f9f7 8417 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8418 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8419 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8420 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8421 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
<> 144:ef7eb2e8f9f7 8422 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
<> 144:ef7eb2e8f9f7 8423 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
<> 144:ef7eb2e8f9f7 8424 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
<> 144:ef7eb2e8f9f7 8425 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
<> 144:ef7eb2e8f9f7 8426 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
<> 144:ef7eb2e8f9f7 8427 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
<> 144:ef7eb2e8f9f7 8428 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
<> 144:ef7eb2e8f9f7 8429 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
<> 144:ef7eb2e8f9f7 8430 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
<> 144:ef7eb2e8f9f7 8431 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
<> 144:ef7eb2e8f9f7 8432 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
<> 144:ef7eb2e8f9f7 8433 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
mbed_official 74:9322579e4309 8434
mbed_official 74:9322579e4309 8435 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
<> 144:ef7eb2e8f9f7 8436 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
<> 144:ef7eb2e8f9f7 8437 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
<> 144:ef7eb2e8f9f7 8438 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
<> 144:ef7eb2e8f9f7 8439 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
<> 144:ef7eb2e8f9f7 8440 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
<> 144:ef7eb2e8f9f7 8441 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 8442 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8443 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8444 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8445 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8446 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8447 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
<> 144:ef7eb2e8f9f7 8448 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
mbed_official 74:9322579e4309 8449
mbed_official 74:9322579e4309 8450 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
<> 144:ef7eb2e8f9f7 8451 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 8452 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 8453 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 8454 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 8455 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 8456 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 8457 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 8458 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
mbed_official 74:9322579e4309 8459
mbed_official 74:9322579e4309 8460 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 8461 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
<> 144:ef7eb2e8f9f7 8462 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 8463 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8464 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8465 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8466 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8467 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8468 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8469 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8470 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 8471
<> 144:ef7eb2e8f9f7 8472 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
<> 144:ef7eb2e8f9f7 8473 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8474 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8475 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8476 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8477 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8478 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8479 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8480 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
mbed_official 74:9322579e4309 8481
mbed_official 74:9322579e4309 8482 /******************** Bit definition for USB_OTG_HAINT register ********************/
<> 144:ef7eb2e8f9f7 8483 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
mbed_official 74:9322579e4309 8484
mbed_official 74:9322579e4309 8485 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
<> 144:ef7eb2e8f9f7 8486 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 8487 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 8488 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
<> 144:ef7eb2e8f9f7 8489 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
<> 144:ef7eb2e8f9f7 8490 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
<> 144:ef7eb2e8f9f7 8491 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
<> 144:ef7eb2e8f9f7 8492 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 8493 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
mbed_official 74:9322579e4309 8494
mbed_official 74:9322579e4309 8495 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
<> 144:ef7eb2e8f9f7 8496 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
<> 144:ef7eb2e8f9f7 8497 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
<> 144:ef7eb2e8f9f7 8498 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
<> 144:ef7eb2e8f9f7 8499 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
<> 144:ef7eb2e8f9f7 8500 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
<> 144:ef7eb2e8f9f7 8501 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 8502 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
<> 144:ef7eb2e8f9f7 8503 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
<> 144:ef7eb2e8f9f7 8504 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
<> 144:ef7eb2e8f9f7 8505 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
<> 144:ef7eb2e8f9f7 8506 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
<> 144:ef7eb2e8f9f7 8507 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
<> 144:ef7eb2e8f9f7 8508 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
<> 144:ef7eb2e8f9f7 8509 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
<> 144:ef7eb2e8f9f7 8510 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
<> 144:ef7eb2e8f9f7 8511 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
<> 144:ef7eb2e8f9f7 8512 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
<> 144:ef7eb2e8f9f7 8513 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
<> 144:ef7eb2e8f9f7 8514 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
<> 144:ef7eb2e8f9f7 8515 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
<> 144:ef7eb2e8f9f7 8516 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
<> 144:ef7eb2e8f9f7 8517 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
<> 144:ef7eb2e8f9f7 8518 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
<> 144:ef7eb2e8f9f7 8519 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
<> 144:ef7eb2e8f9f7 8520 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
<> 144:ef7eb2e8f9f7 8521 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
<> 144:ef7eb2e8f9f7 8522 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
<> 144:ef7eb2e8f9f7 8523 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
mbed_official 74:9322579e4309 8524
mbed_official 74:9322579e4309 8525 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
<> 144:ef7eb2e8f9f7 8526 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 8527 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
<> 144:ef7eb2e8f9f7 8528 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
<> 144:ef7eb2e8f9f7 8529 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
<> 144:ef7eb2e8f9f7 8530 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 8531 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
<> 144:ef7eb2e8f9f7 8532 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
<> 144:ef7eb2e8f9f7 8533 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
<> 144:ef7eb2e8f9f7 8534 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
<> 144:ef7eb2e8f9f7 8535 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
<> 144:ef7eb2e8f9f7 8536 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
<> 144:ef7eb2e8f9f7 8537 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
<> 144:ef7eb2e8f9f7 8538 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
<> 144:ef7eb2e8f9f7 8539 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
<> 144:ef7eb2e8f9f7 8540 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 8541 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
<> 144:ef7eb2e8f9f7 8542 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
<> 144:ef7eb2e8f9f7 8543 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
<> 144:ef7eb2e8f9f7 8544 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
<> 144:ef7eb2e8f9f7 8545 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
<> 144:ef7eb2e8f9f7 8546 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
<> 144:ef7eb2e8f9f7 8547 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
<> 144:ef7eb2e8f9f7 8548 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 8549 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
<> 144:ef7eb2e8f9f7 8550 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
<> 144:ef7eb2e8f9f7 8551 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
<> 144:ef7eb2e8f9f7 8552 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
<> 144:ef7eb2e8f9f7 8553 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 74:9322579e4309 8554
mbed_official 74:9322579e4309 8555 /******************** Bit definition for USB_OTG_DAINT register ********************/
<> 144:ef7eb2e8f9f7 8556 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
<> 144:ef7eb2e8f9f7 8557 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
mbed_official 74:9322579e4309 8558
mbed_official 74:9322579e4309 8559 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 8560 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
mbed_official 74:9322579e4309 8561
mbed_official 74:9322579e4309 8562 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 144:ef7eb2e8f9f7 8563 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 8564 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 8565 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 8566 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
mbed_official 74:9322579e4309 8567
mbed_official 74:9322579e4309 8568 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
<> 144:ef7eb2e8f9f7 8569 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 8570 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
mbed_official 74:9322579e4309 8571
mbed_official 74:9322579e4309 8572 /******************** Bit definition for OTG register ********************/
mbed_official 74:9322579e4309 8573
<> 144:ef7eb2e8f9f7 8574 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 8575 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8576 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8577 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8578 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8579 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 8580
<> 144:ef7eb2e8f9f7 8581 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 8582 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8583 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8584
<> 144:ef7eb2e8f9f7 8585 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 8586 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8587 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8588 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8589 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8590
<> 144:ef7eb2e8f9f7 8591 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 8592 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8593 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8594 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8595 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8596
<> 144:ef7eb2e8f9f7 8597 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 8598 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8599 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8600 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8601 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
mbed_official 74:9322579e4309 8602
mbed_official 74:9322579e4309 8603 /******************** Bit definition for OTG register ********************/
mbed_official 74:9322579e4309 8604
<> 144:ef7eb2e8f9f7 8605 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 144:ef7eb2e8f9f7 8606 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8607 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8608 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8609 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8610 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 144:ef7eb2e8f9f7 8611
<> 144:ef7eb2e8f9f7 8612 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 8613 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8614 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8615
<> 144:ef7eb2e8f9f7 8616 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 144:ef7eb2e8f9f7 8617 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8618 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8619 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8620 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8621
<> 144:ef7eb2e8f9f7 8622 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 8623 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8624 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8625 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8626 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8627
<> 144:ef7eb2e8f9f7 8628 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 144:ef7eb2e8f9f7 8629 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8630 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8631 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8632 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
mbed_official 74:9322579e4309 8633
mbed_official 74:9322579e4309 8634 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 8635 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
mbed_official 74:9322579e4309 8636
mbed_official 74:9322579e4309 8637 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
<> 144:ef7eb2e8f9f7 8638 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
mbed_official 74:9322579e4309 8639
mbed_official 74:9322579e4309 8640 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 8641 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
<> 144:ef7eb2e8f9f7 8642 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
<> 144:ef7eb2e8f9f7 8643 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
<> 144:ef7eb2e8f9f7 8644 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
mbed_official 74:9322579e4309 8645
mbed_official 74:9322579e4309 8646 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
<> 144:ef7eb2e8f9f7 8647 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
mbed_official 74:9322579e4309 8648
mbed_official 74:9322579e4309 8649 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
<> 144:ef7eb2e8f9f7 8650 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
<> 144:ef7eb2e8f9f7 8651
<> 144:ef7eb2e8f9f7 8652 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
<> 144:ef7eb2e8f9f7 8653 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8654 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8655 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8656 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8657 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8658 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8659 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8660 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 8661
<> 144:ef7eb2e8f9f7 8662 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
<> 144:ef7eb2e8f9f7 8663 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8664 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8665 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8666 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8667 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8668 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8669 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
mbed_official 74:9322579e4309 8670
mbed_official 74:9322579e4309 8671 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
<> 144:ef7eb2e8f9f7 8672 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
<> 144:ef7eb2e8f9f7 8673 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
<> 144:ef7eb2e8f9f7 8674
<> 144:ef7eb2e8f9f7 8675 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
<> 144:ef7eb2e8f9f7 8676 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8677 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8678 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8679 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8680 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8681 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8682 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8683 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 8684 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 8685 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
<> 144:ef7eb2e8f9f7 8686
<> 144:ef7eb2e8f9f7 8687 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
<> 144:ef7eb2e8f9f7 8688 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8689 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8690 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8691 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8692 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8693 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8694 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8695 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
<> 144:ef7eb2e8f9f7 8696 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
<> 144:ef7eb2e8f9f7 8697 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
mbed_official 74:9322579e4309 8698
mbed_official 74:9322579e4309 8699 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
<> 144:ef7eb2e8f9f7 8700 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 74:9322579e4309 8701
mbed_official 74:9322579e4309 8702 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
<> 144:ef7eb2e8f9f7 8703 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
<> 144:ef7eb2e8f9f7 8704 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
mbed_official 74:9322579e4309 8705
mbed_official 74:9322579e4309 8706 /******************** Bit definition for USB_OTG_GCCFG register ********************/
<> 144:ef7eb2e8f9f7 8707 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
<> 144:ef7eb2e8f9f7 8708 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
mbed_official 74:9322579e4309 8709
mbed_official 74:9322579e4309 8710 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
<> 144:ef7eb2e8f9f7 8711 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */
<> 144:ef7eb2e8f9f7 8712 #define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */
mbed_official 74:9322579e4309 8713
mbed_official 74:9322579e4309 8714 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
<> 144:ef7eb2e8f9f7 8715 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
<> 144:ef7eb2e8f9f7 8716 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 74:9322579e4309 8717
mbed_official 74:9322579e4309 8718 /******************** Bit definition for USB_OTG_CID register ********************/
<> 144:ef7eb2e8f9f7 8719 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
mbed_official 74:9322579e4309 8720
mbed_official 74:9322579e4309 8721 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
<> 144:ef7eb2e8f9f7 8722 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
<> 144:ef7eb2e8f9f7 8723 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
<> 144:ef7eb2e8f9f7 8724 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
<> 144:ef7eb2e8f9f7 8725 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
<> 144:ef7eb2e8f9f7 8726 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
<> 144:ef7eb2e8f9f7 8727 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
<> 144:ef7eb2e8f9f7 8728 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
<> 144:ef7eb2e8f9f7 8729 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
<> 144:ef7eb2e8f9f7 8730 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
<> 144:ef7eb2e8f9f7 8731 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
<> 144:ef7eb2e8f9f7 8732 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
<> 144:ef7eb2e8f9f7 8733 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
<> 144:ef7eb2e8f9f7 8734 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
<> 144:ef7eb2e8f9f7 8735 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
<> 144:ef7eb2e8f9f7 8736 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
mbed_official 74:9322579e4309 8737
mbed_official 74:9322579e4309 8738 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 8739 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 8740 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 8741 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 144:ef7eb2e8f9f7 8742 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 8743 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 8744 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 8745 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 144:ef7eb2e8f9f7 8746 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 8747 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
mbed_official 74:9322579e4309 8748
mbed_official 74:9322579e4309 8749 /******************** Bit definition for USB_OTG_HPRT register ********************/
<> 144:ef7eb2e8f9f7 8750 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
<> 144:ef7eb2e8f9f7 8751 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
<> 144:ef7eb2e8f9f7 8752 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
<> 144:ef7eb2e8f9f7 8753 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
<> 144:ef7eb2e8f9f7 8754 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
<> 144:ef7eb2e8f9f7 8755 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
<> 144:ef7eb2e8f9f7 8756 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
<> 144:ef7eb2e8f9f7 8757 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
<> 144:ef7eb2e8f9f7 8758 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
<> 144:ef7eb2e8f9f7 8759
<> 144:ef7eb2e8f9f7 8760 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
<> 144:ef7eb2e8f9f7 8761 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8762 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8763 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
<> 144:ef7eb2e8f9f7 8764
<> 144:ef7eb2e8f9f7 8765 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
<> 144:ef7eb2e8f9f7 8766 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8767 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8768 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8769 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8770
<> 144:ef7eb2e8f9f7 8771 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
<> 144:ef7eb2e8f9f7 8772 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8773 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
mbed_official 74:9322579e4309 8774
mbed_official 74:9322579e4309 8775 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
<> 144:ef7eb2e8f9f7 8776 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 144:ef7eb2e8f9f7 8777 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 144:ef7eb2e8f9f7 8778 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
<> 144:ef7eb2e8f9f7 8779 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 144:ef7eb2e8f9f7 8780 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 144:ef7eb2e8f9f7 8781 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 144:ef7eb2e8f9f7 8782 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
<> 144:ef7eb2e8f9f7 8783 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 144:ef7eb2e8f9f7 8784 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
<> 144:ef7eb2e8f9f7 8785 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 144:ef7eb2e8f9f7 8786 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
mbed_official 74:9322579e4309 8787
mbed_official 74:9322579e4309 8788 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
<> 144:ef7eb2e8f9f7 8789 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
<> 144:ef7eb2e8f9f7 8790 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
mbed_official 74:9322579e4309 8791
mbed_official 74:9322579e4309 8792 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
<> 144:ef7eb2e8f9f7 8793 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 8794 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 8795 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
<> 144:ef7eb2e8f9f7 8796 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 8797
<> 144:ef7eb2e8f9f7 8798 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 8799 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8800 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8801 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 8802
<> 144:ef7eb2e8f9f7 8803 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
<> 144:ef7eb2e8f9f7 8804 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8805 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8806 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8807 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8808 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 8809 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 8810 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 8811 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 8812 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 8813 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
mbed_official 74:9322579e4309 8814
mbed_official 74:9322579e4309 8815 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
<> 144:ef7eb2e8f9f7 8816 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 144:ef7eb2e8f9f7 8817
<> 144:ef7eb2e8f9f7 8818 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
<> 144:ef7eb2e8f9f7 8819 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8820 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8821 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8822 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8823 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
<> 144:ef7eb2e8f9f7 8824 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
<> 144:ef7eb2e8f9f7 8825
<> 144:ef7eb2e8f9f7 8826 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 8827 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8828 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8829
<> 144:ef7eb2e8f9f7 8830 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
<> 144:ef7eb2e8f9f7 8831 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8832 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8833
<> 144:ef7eb2e8f9f7 8834 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
<> 144:ef7eb2e8f9f7 8835 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8836 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8837 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8838 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8839 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8840 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8841 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8842 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
<> 144:ef7eb2e8f9f7 8843 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
<> 144:ef7eb2e8f9f7 8844 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
mbed_official 74:9322579e4309 8845
mbed_official 74:9322579e4309 8846 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
mbed_official 74:9322579e4309 8847
<> 144:ef7eb2e8f9f7 8848 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
<> 144:ef7eb2e8f9f7 8849 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8850 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8851 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8852 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8853 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8854 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8855 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8856
<> 144:ef7eb2e8f9f7 8857 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
<> 144:ef7eb2e8f9f7 8858 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8859 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8860 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
<> 144:ef7eb2e8f9f7 8861 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
<> 144:ef7eb2e8f9f7 8862 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
<> 144:ef7eb2e8f9f7 8863 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
<> 144:ef7eb2e8f9f7 8864 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
<> 144:ef7eb2e8f9f7 8865
<> 144:ef7eb2e8f9f7 8866 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
<> 144:ef7eb2e8f9f7 8867 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8868 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8869 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
<> 144:ef7eb2e8f9f7 8870 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
mbed_official 74:9322579e4309 8871
mbed_official 74:9322579e4309 8872 /******************** Bit definition for USB_OTG_HCINT register ********************/
<> 144:ef7eb2e8f9f7 8873 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
<> 144:ef7eb2e8f9f7 8874 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
<> 144:ef7eb2e8f9f7 8875 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 8876 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
<> 144:ef7eb2e8f9f7 8877 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
<> 144:ef7eb2e8f9f7 8878 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
<> 144:ef7eb2e8f9f7 8879 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
<> 144:ef7eb2e8f9f7 8880 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
<> 144:ef7eb2e8f9f7 8881 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
<> 144:ef7eb2e8f9f7 8882 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
<> 144:ef7eb2e8f9f7 8883 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
mbed_official 74:9322579e4309 8884
mbed_official 74:9322579e4309 8885 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
<> 144:ef7eb2e8f9f7 8886 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 8887 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 8888 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
<> 144:ef7eb2e8f9f7 8889 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
<> 144:ef7eb2e8f9f7 8890 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
<> 144:ef7eb2e8f9f7 8891 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
<> 144:ef7eb2e8f9f7 8892 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
<> 144:ef7eb2e8f9f7 8893 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
<> 144:ef7eb2e8f9f7 8894 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
<> 144:ef7eb2e8f9f7 8895 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
<> 144:ef7eb2e8f9f7 8896 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
mbed_official 74:9322579e4309 8897
mbed_official 74:9322579e4309 8898 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
<> 144:ef7eb2e8f9f7 8899 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
<> 144:ef7eb2e8f9f7 8900 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
<> 144:ef7eb2e8f9f7 8901 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
<> 144:ef7eb2e8f9f7 8902 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
<> 144:ef7eb2e8f9f7 8903 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
<> 144:ef7eb2e8f9f7 8904 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
<> 144:ef7eb2e8f9f7 8905 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
<> 144:ef7eb2e8f9f7 8906 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
<> 144:ef7eb2e8f9f7 8907 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
<> 144:ef7eb2e8f9f7 8908 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
<> 144:ef7eb2e8f9f7 8909 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
mbed_official 74:9322579e4309 8910
mbed_official 74:9322579e4309 8911 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 74:9322579e4309 8912
<> 144:ef7eb2e8f9f7 8913 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 8914 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 8915 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
mbed_official 74:9322579e4309 8916 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
<> 144:ef7eb2e8f9f7 8917 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 8918 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 8919 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
<> 144:ef7eb2e8f9f7 8920 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
<> 144:ef7eb2e8f9f7 8921 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8922 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 8923
mbed_official 74:9322579e4309 8924 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
<> 144:ef7eb2e8f9f7 8925 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
mbed_official 74:9322579e4309 8926
mbed_official 74:9322579e4309 8927 /******************** Bit definition for USB_OTG_HCDMA register ********************/
<> 144:ef7eb2e8f9f7 8928 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
mbed_official 74:9322579e4309 8929
mbed_official 74:9322579e4309 8930 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
<> 144:ef7eb2e8f9f7 8931 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
mbed_official 74:9322579e4309 8932
mbed_official 74:9322579e4309 8933 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
<> 144:ef7eb2e8f9f7 8934 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
<> 144:ef7eb2e8f9f7 8935 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
mbed_official 74:9322579e4309 8936
mbed_official 74:9322579e4309 8937 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
<> 144:ef7eb2e8f9f7 8938 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8939 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 144:ef7eb2e8f9f7 8940 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 144:ef7eb2e8f9f7 8941 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 144:ef7eb2e8f9f7 8942 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 144:ef7eb2e8f9f7 8943 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 144:ef7eb2e8f9f7 8944 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8945 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8946 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
<> 144:ef7eb2e8f9f7 8947 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 144:ef7eb2e8f9f7 8948 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 144:ef7eb2e8f9f7 8949 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 144:ef7eb2e8f9f7 8950 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 144:ef7eb2e8f9f7 8951 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
mbed_official 74:9322579e4309 8952
mbed_official 74:9322579e4309 8953 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
<> 144:ef7eb2e8f9f7 8954 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 144:ef7eb2e8f9f7 8955 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 144:ef7eb2e8f9f7 8956 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
<> 144:ef7eb2e8f9f7 8957 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
<> 144:ef7eb2e8f9f7 8958 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
<> 144:ef7eb2e8f9f7 8959 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
<> 144:ef7eb2e8f9f7 8960 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
mbed_official 74:9322579e4309 8961
mbed_official 74:9322579e4309 8962 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 8963 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 144:ef7eb2e8f9f7 8964 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 144:ef7eb2e8f9f7 8965
<> 144:ef7eb2e8f9f7 8966 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 8967 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8968 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
mbed_official 74:9322579e4309 8969
mbed_official 74:9322579e4309 8970 /******************** Bit definition for PCGCCTL register ********************/
<> 144:ef7eb2e8f9f7 8971 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
<> 144:ef7eb2e8f9f7 8972 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
<> 144:ef7eb2e8f9f7 8973 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 8974
<> 144:ef7eb2e8f9f7 8975
mbed_official 74:9322579e4309 8976
mbed_official 74:9322579e4309 8977 /**
mbed_official 74:9322579e4309 8978 * @}
mbed_official 74:9322579e4309 8979 */
mbed_official 74:9322579e4309 8980
mbed_official 74:9322579e4309 8981 /**
mbed_official 74:9322579e4309 8982 * @}
mbed_official 74:9322579e4309 8983 */
mbed_official 74:9322579e4309 8984
mbed_official 74:9322579e4309 8985 /** @addtogroup Exported_macros
mbed_official 74:9322579e4309 8986 * @{
mbed_official 74:9322579e4309 8987 */
mbed_official 74:9322579e4309 8988
mbed_official 74:9322579e4309 8989 /******************************* ADC Instances ********************************/
mbed_official 74:9322579e4309 8990 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
mbed_official 74:9322579e4309 8991 ((__INSTANCE__) == ADC2) || \
mbed_official 74:9322579e4309 8992 ((__INSTANCE__) == ADC3))
mbed_official 74:9322579e4309 8993
mbed_official 74:9322579e4309 8994 /******************************* CAN Instances ********************************/
mbed_official 74:9322579e4309 8995 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
<> 144:ef7eb2e8f9f7 8996 ((__INSTANCE__) == CAN2))
mbed_official 74:9322579e4309 8997 /******************************* CRC Instances ********************************/
mbed_official 74:9322579e4309 8998 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
mbed_official 74:9322579e4309 8999
mbed_official 74:9322579e4309 9000 /******************************* DAC Instances ********************************/
mbed_official 74:9322579e4309 9001 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
mbed_official 74:9322579e4309 9002
mbed_official 74:9322579e4309 9003 /******************************* DCMI Instances *******************************/
mbed_official 74:9322579e4309 9004 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
mbed_official 74:9322579e4309 9005
mbed_official 83:a036322b8637 9006
mbed_official 74:9322579e4309 9007 /******************************* DMA2D Instances *******************************/
mbed_official 74:9322579e4309 9008 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
mbed_official 74:9322579e4309 9009
mbed_official 74:9322579e4309 9010 /******************************** DMA Instances *******************************/
mbed_official 74:9322579e4309 9011 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
mbed_official 74:9322579e4309 9012 ((__INSTANCE__) == DMA1_Stream1) || \
mbed_official 74:9322579e4309 9013 ((__INSTANCE__) == DMA1_Stream2) || \
mbed_official 74:9322579e4309 9014 ((__INSTANCE__) == DMA1_Stream3) || \
mbed_official 74:9322579e4309 9015 ((__INSTANCE__) == DMA1_Stream4) || \
mbed_official 74:9322579e4309 9016 ((__INSTANCE__) == DMA1_Stream5) || \
mbed_official 74:9322579e4309 9017 ((__INSTANCE__) == DMA1_Stream6) || \
mbed_official 74:9322579e4309 9018 ((__INSTANCE__) == DMA1_Stream7) || \
mbed_official 74:9322579e4309 9019 ((__INSTANCE__) == DMA2_Stream0) || \
mbed_official 74:9322579e4309 9020 ((__INSTANCE__) == DMA2_Stream1) || \
mbed_official 74:9322579e4309 9021 ((__INSTANCE__) == DMA2_Stream2) || \
mbed_official 74:9322579e4309 9022 ((__INSTANCE__) == DMA2_Stream3) || \
mbed_official 74:9322579e4309 9023 ((__INSTANCE__) == DMA2_Stream4) || \
mbed_official 74:9322579e4309 9024 ((__INSTANCE__) == DMA2_Stream5) || \
mbed_official 74:9322579e4309 9025 ((__INSTANCE__) == DMA2_Stream6) || \
mbed_official 74:9322579e4309 9026 ((__INSTANCE__) == DMA2_Stream7))
mbed_official 74:9322579e4309 9027
mbed_official 74:9322579e4309 9028 /******************************* GPIO Instances *******************************/
mbed_official 74:9322579e4309 9029 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
mbed_official 74:9322579e4309 9030 ((__INSTANCE__) == GPIOB) || \
mbed_official 74:9322579e4309 9031 ((__INSTANCE__) == GPIOC) || \
mbed_official 74:9322579e4309 9032 ((__INSTANCE__) == GPIOD) || \
mbed_official 74:9322579e4309 9033 ((__INSTANCE__) == GPIOE) || \
mbed_official 74:9322579e4309 9034 ((__INSTANCE__) == GPIOF) || \
mbed_official 74:9322579e4309 9035 ((__INSTANCE__) == GPIOG) || \
mbed_official 74:9322579e4309 9036 ((__INSTANCE__) == GPIOH) || \
mbed_official 74:9322579e4309 9037 ((__INSTANCE__) == GPIOI) || \
mbed_official 74:9322579e4309 9038 ((__INSTANCE__) == GPIOJ) || \
mbed_official 74:9322579e4309 9039 ((__INSTANCE__) == GPIOK))
mbed_official 74:9322579e4309 9040
mbed_official 74:9322579e4309 9041 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
mbed_official 74:9322579e4309 9042 ((__INSTANCE__) == GPIOB) || \
mbed_official 74:9322579e4309 9043 ((__INSTANCE__) == GPIOC) || \
mbed_official 74:9322579e4309 9044 ((__INSTANCE__) == GPIOD) || \
mbed_official 74:9322579e4309 9045 ((__INSTANCE__) == GPIOE) || \
mbed_official 74:9322579e4309 9046 ((__INSTANCE__) == GPIOF) || \
mbed_official 74:9322579e4309 9047 ((__INSTANCE__) == GPIOG) || \
mbed_official 74:9322579e4309 9048 ((__INSTANCE__) == GPIOH) || \
mbed_official 74:9322579e4309 9049 ((__INSTANCE__) == GPIOI) || \
mbed_official 74:9322579e4309 9050 ((__INSTANCE__) == GPIOJ) || \
mbed_official 74:9322579e4309 9051 ((__INSTANCE__) == GPIOK))
mbed_official 74:9322579e4309 9052
mbed_official 74:9322579e4309 9053 /****************************** CEC Instances *********************************/
mbed_official 74:9322579e4309 9054 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
mbed_official 74:9322579e4309 9055
mbed_official 74:9322579e4309 9056 /****************************** QSPI Instances *********************************/
mbed_official 74:9322579e4309 9057 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
mbed_official 74:9322579e4309 9058
mbed_official 74:9322579e4309 9059
mbed_official 74:9322579e4309 9060 /******************************** I2C Instances *******************************/
mbed_official 74:9322579e4309 9061 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
mbed_official 74:9322579e4309 9062 ((__INSTANCE__) == I2C2) || \
mbed_official 74:9322579e4309 9063 ((__INSTANCE__) == I2C3) || \
mbed_official 74:9322579e4309 9064 ((__INSTANCE__) == I2C4))
mbed_official 74:9322579e4309 9065
mbed_official 74:9322579e4309 9066 /******************************** I2S Instances *******************************/
mbed_official 74:9322579e4309 9067 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
mbed_official 74:9322579e4309 9068 ((__INSTANCE__) == SPI2) || \
mbed_official 74:9322579e4309 9069 ((__INSTANCE__) == SPI3))
mbed_official 74:9322579e4309 9070
mbed_official 74:9322579e4309 9071 /******************************* LPTIM Instances ********************************/
mbed_official 74:9322579e4309 9072 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
mbed_official 74:9322579e4309 9073
mbed_official 74:9322579e4309 9074 /****************************** LTDC Instances ********************************/
mbed_official 74:9322579e4309 9075 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
mbed_official 74:9322579e4309 9076
mbed_official 83:a036322b8637 9077
<> 144:ef7eb2e8f9f7 9078
mbed_official 74:9322579e4309 9079 /******************************* RNG Instances ********************************/
mbed_official 74:9322579e4309 9080 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
mbed_official 74:9322579e4309 9081
mbed_official 74:9322579e4309 9082 /****************************** RTC Instances *********************************/
mbed_official 74:9322579e4309 9083 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
mbed_official 74:9322579e4309 9084
mbed_official 74:9322579e4309 9085 /******************************* SAI Instances ********************************/
<> 144:ef7eb2e8f9f7 9086 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
<> 144:ef7eb2e8f9f7 9087 ((__PERIPH__) == SAI1_Block_B) || \
<> 144:ef7eb2e8f9f7 9088 ((__PERIPH__) == SAI2_Block_A) || \
<> 144:ef7eb2e8f9f7 9089 ((__PERIPH__) == SAI2_Block_B))
<> 144:ef7eb2e8f9f7 9090 /* Legacy define */
<> 144:ef7eb2e8f9f7 9091 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
mbed_official 74:9322579e4309 9092
mbed_official 74:9322579e4309 9093 /******************************** SDMMC Instances *******************************/
mbed_official 74:9322579e4309 9094 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
mbed_official 74:9322579e4309 9095
mbed_official 74:9322579e4309 9096 /****************************** SPDIFRX Instances *********************************/
mbed_official 74:9322579e4309 9097 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
mbed_official 74:9322579e4309 9098
mbed_official 74:9322579e4309 9099 /******************************** SPI Instances *******************************/
mbed_official 74:9322579e4309 9100 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
mbed_official 74:9322579e4309 9101 ((__INSTANCE__) == SPI2) || \
mbed_official 74:9322579e4309 9102 ((__INSTANCE__) == SPI3) || \
mbed_official 74:9322579e4309 9103 ((__INSTANCE__) == SPI4) || \
mbed_official 74:9322579e4309 9104 ((__INSTANCE__) == SPI5) || \
mbed_official 74:9322579e4309 9105 ((__INSTANCE__) == SPI6))
mbed_official 74:9322579e4309 9106
mbed_official 74:9322579e4309 9107 /****************** TIM Instances : All supported instances *******************/
mbed_official 74:9322579e4309 9108 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9109 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9110 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9111 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9112 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9113 ((__INSTANCE__) == TIM6) || \
mbed_official 74:9322579e4309 9114 ((__INSTANCE__) == TIM7) || \
mbed_official 74:9322579e4309 9115 ((__INSTANCE__) == TIM8) || \
mbed_official 74:9322579e4309 9116 ((__INSTANCE__) == TIM9) || \
mbed_official 74:9322579e4309 9117 ((__INSTANCE__) == TIM10) || \
mbed_official 74:9322579e4309 9118 ((__INSTANCE__) == TIM11) || \
mbed_official 74:9322579e4309 9119 ((__INSTANCE__) == TIM12) || \
mbed_official 74:9322579e4309 9120 ((__INSTANCE__) == TIM13) || \
mbed_official 74:9322579e4309 9121 ((__INSTANCE__) == TIM14))
mbed_official 74:9322579e4309 9122
mbed_official 74:9322579e4309 9123 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 74:9322579e4309 9124 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9125 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9126 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9127 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9128 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9129 ((__INSTANCE__) == TIM8) || \
mbed_official 74:9322579e4309 9130 ((__INSTANCE__) == TIM9) || \
mbed_official 74:9322579e4309 9131 ((__INSTANCE__) == TIM10) || \
mbed_official 74:9322579e4309 9132 ((__INSTANCE__) == TIM11) || \
mbed_official 74:9322579e4309 9133 ((__INSTANCE__) == TIM12) || \
mbed_official 74:9322579e4309 9134 ((__INSTANCE__) == TIM13) || \
mbed_official 74:9322579e4309 9135 ((__INSTANCE__) == TIM14))
mbed_official 74:9322579e4309 9136
mbed_official 74:9322579e4309 9137 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 74:9322579e4309 9138 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9139 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9140 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9141 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9142 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9143 ((__INSTANCE__) == TIM8) || \
mbed_official 74:9322579e4309 9144 ((__INSTANCE__) == TIM9) || \
mbed_official 74:9322579e4309 9145 ((__INSTANCE__) == TIM12))
mbed_official 74:9322579e4309 9146
mbed_official 74:9322579e4309 9147 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 74:9322579e4309 9148 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9149 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9150 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9151 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9152 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9153 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9154
mbed_official 74:9322579e4309 9155 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 74:9322579e4309 9156 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9157 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9158 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9159 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9160 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9161 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9162
mbed_official 74:9322579e4309 9163 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
mbed_official 74:9322579e4309 9164 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
mbed_official 74:9322579e4309 9165 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9166 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9167
mbed_official 74:9322579e4309 9168 /****************** TIM Instances : supporting OCxREF clear *******************/
mbed_official 74:9322579e4309 9169 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9170 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9171 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9172 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9173 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9174 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9175
mbed_official 74:9322579e4309 9176 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 74:9322579e4309 9177 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9178 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9179 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9180 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9181 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9182 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9183 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9184
mbed_official 74:9322579e4309 9185 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 74:9322579e4309 9186 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9187 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9188 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9189 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9190 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9191 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9192 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9193 /****************** TIM Instances : at least 5 capture/compare channels *******/
mbed_official 74:9322579e4309 9194 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9195 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9196 ((__INSTANCE__) == TIM8) )
mbed_official 74:9322579e4309 9197
mbed_official 74:9322579e4309 9198 /****************** TIM Instances : at least 6 capture/compare channels *******/
mbed_official 74:9322579e4309 9199 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9200 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9201 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9202
mbed_official 74:9322579e4309 9203
mbed_official 74:9322579e4309 9204 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 74:9322579e4309 9205 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9206 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9207
mbed_official 74:9322579e4309 9208 /****************** TIM Instances : supporting 2 break inputs *****************/
mbed_official 74:9322579e4309 9209 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9210 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9211 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9212
mbed_official 74:9322579e4309 9213 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 74:9322579e4309 9214 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9215 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9216 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9217 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9218 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9219 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9220
mbed_official 74:9322579e4309 9221 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 74:9322579e4309 9222 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9223 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9224 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9225 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9226 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9227 ((__INSTANCE__) == TIM6) || \
mbed_official 74:9322579e4309 9228 ((__INSTANCE__) == TIM7) || \
mbed_official 74:9322579e4309 9229 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9230
mbed_official 74:9322579e4309 9231 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 74:9322579e4309 9232 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9233 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9234 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9235 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9236 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9237 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9238
mbed_official 74:9322579e4309 9239 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 74:9322579e4309 9240 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9241 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9242 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9243 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9244 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9245 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9246
mbed_official 74:9322579e4309 9247 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 74:9322579e4309 9248 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9249 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9250 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9251 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9252 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9253 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9254
mbed_official 74:9322579e4309 9255 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 74:9322579e4309 9256 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9257 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9258 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9259 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9260 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9261 ((__INSTANCE__) == TIM6) || \
mbed_official 74:9322579e4309 9262 ((__INSTANCE__) == TIM7) || \
mbed_official 74:9322579e4309 9263 ((__INSTANCE__) == TIM8) || \
mbed_official 74:9322579e4309 9264 ((__INSTANCE__) == TIM13) || \
mbed_official 74:9322579e4309 9265 ((__INSTANCE__) == TIM14))
mbed_official 74:9322579e4309 9266
mbed_official 74:9322579e4309 9267 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 74:9322579e4309 9268 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9269 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9270 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9271 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9272 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9273 ((__INSTANCE__) == TIM8) || \
mbed_official 74:9322579e4309 9274 ((__INSTANCE__) == TIM9) || \
mbed_official 74:9322579e4309 9275 ((__INSTANCE__) == TIM12))
mbed_official 74:9322579e4309 9276
mbed_official 74:9322579e4309 9277 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 74:9322579e4309 9278 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9279 ((__INSTANCE__) == TIM5))
mbed_official 74:9322579e4309 9280
mbed_official 74:9322579e4309 9281 /***************** TIM Instances : external trigger input available ************/
mbed_official 74:9322579e4309 9282 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9283 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9284 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9285 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9286 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9287 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9288
mbed_official 74:9322579e4309 9289 /****************** TIM Instances : remapping capability **********************/
mbed_official 74:9322579e4309 9290 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9291 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9292 ((__INSTANCE__) == TIM11))
mbed_official 74:9322579e4309 9293
mbed_official 74:9322579e4309 9294 /******************* TIM Instances : output(s) available **********************/
mbed_official 74:9322579e4309 9295 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
mbed_official 74:9322579e4309 9296 ((((__INSTANCE__) == TIM1) && \
mbed_official 74:9322579e4309 9297 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9298 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9299 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9300 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9301 || \
mbed_official 74:9322579e4309 9302 (((__INSTANCE__) == TIM2) && \
mbed_official 74:9322579e4309 9303 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9304 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9305 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9306 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9307 || \
mbed_official 74:9322579e4309 9308 (((__INSTANCE__) == TIM3) && \
mbed_official 74:9322579e4309 9309 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9310 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9311 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9312 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9313 || \
mbed_official 74:9322579e4309 9314 (((__INSTANCE__) == TIM4) && \
mbed_official 74:9322579e4309 9315 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9316 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9317 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9318 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9319 || \
mbed_official 74:9322579e4309 9320 (((__INSTANCE__) == TIM5) && \
mbed_official 74:9322579e4309 9321 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9322 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9323 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9324 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9325 || \
mbed_official 74:9322579e4309 9326 (((__INSTANCE__) == TIM8) && \
mbed_official 74:9322579e4309 9327 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9328 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9329 ((__CHANNEL__) == TIM_CHANNEL_3) || \
mbed_official 74:9322579e4309 9330 ((__CHANNEL__) == TIM_CHANNEL_4))) \
mbed_official 74:9322579e4309 9331 || \
mbed_official 74:9322579e4309 9332 (((__INSTANCE__) == TIM9) && \
mbed_official 74:9322579e4309 9333 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9334 ((__CHANNEL__) == TIM_CHANNEL_2))) \
mbed_official 74:9322579e4309 9335 || \
mbed_official 74:9322579e4309 9336 (((__INSTANCE__) == TIM10) && \
mbed_official 74:9322579e4309 9337 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 74:9322579e4309 9338 || \
mbed_official 74:9322579e4309 9339 (((__INSTANCE__) == TIM11) && \
mbed_official 74:9322579e4309 9340 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 74:9322579e4309 9341 || \
mbed_official 74:9322579e4309 9342 (((__INSTANCE__) == TIM12) && \
mbed_official 74:9322579e4309 9343 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9344 ((__CHANNEL__) == TIM_CHANNEL_2))) \
mbed_official 74:9322579e4309 9345 || \
mbed_official 74:9322579e4309 9346 (((__INSTANCE__) == TIM13) && \
mbed_official 74:9322579e4309 9347 (((__CHANNEL__) == TIM_CHANNEL_1))) \
mbed_official 74:9322579e4309 9348 || \
mbed_official 74:9322579e4309 9349 (((__INSTANCE__) == TIM14) && \
mbed_official 74:9322579e4309 9350 (((__CHANNEL__) == TIM_CHANNEL_1))))
mbed_official 74:9322579e4309 9351
mbed_official 74:9322579e4309 9352 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 74:9322579e4309 9353 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
mbed_official 74:9322579e4309 9354 ((((__INSTANCE__) == TIM1) && \
mbed_official 74:9322579e4309 9355 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9356 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9357 ((__CHANNEL__) == TIM_CHANNEL_3))) \
mbed_official 74:9322579e4309 9358 || \
mbed_official 74:9322579e4309 9359 (((__INSTANCE__) == TIM8) && \
mbed_official 74:9322579e4309 9360 (((__CHANNEL__) == TIM_CHANNEL_1) || \
mbed_official 74:9322579e4309 9361 ((__CHANNEL__) == TIM_CHANNEL_2) || \
mbed_official 74:9322579e4309 9362 ((__CHANNEL__) == TIM_CHANNEL_3))))
mbed_official 74:9322579e4309 9363
mbed_official 74:9322579e4309 9364 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
mbed_official 74:9322579e4309 9365 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9366 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9367 ((__INSTANCE__) == TIM8) )
mbed_official 74:9322579e4309 9368
mbed_official 74:9322579e4309 9369 /****************** TIM Instances : supporting synchronization ****************/
mbed_official 74:9322579e4309 9370 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
mbed_official 74:9322579e4309 9371 (((__INSTANCE__) == TIM1) || \
mbed_official 74:9322579e4309 9372 ((__INSTANCE__) == TIM2) || \
mbed_official 74:9322579e4309 9373 ((__INSTANCE__) == TIM3) || \
mbed_official 74:9322579e4309 9374 ((__INSTANCE__) == TIM4) || \
mbed_official 74:9322579e4309 9375 ((__INSTANCE__) == TIM5) || \
mbed_official 74:9322579e4309 9376 ((__INSTANCE__) == TIM6) || \
mbed_official 74:9322579e4309 9377 ((__INSTANCE__) == TIM7) || \
mbed_official 74:9322579e4309 9378 ((__INSTANCE__) == TIM8))
mbed_official 74:9322579e4309 9379
mbed_official 74:9322579e4309 9380 /******************** USART Instances : Synchronous mode **********************/
mbed_official 74:9322579e4309 9381 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 74:9322579e4309 9382 ((__INSTANCE__) == USART2) || \
mbed_official 74:9322579e4309 9383 ((__INSTANCE__) == USART3) || \
mbed_official 74:9322579e4309 9384 ((__INSTANCE__) == USART6))
mbed_official 74:9322579e4309 9385
mbed_official 74:9322579e4309 9386 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 74:9322579e4309 9387 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 74:9322579e4309 9388 ((__INSTANCE__) == USART2) || \
mbed_official 74:9322579e4309 9389 ((__INSTANCE__) == USART3) || \
mbed_official 74:9322579e4309 9390 ((__INSTANCE__) == UART4) || \
mbed_official 74:9322579e4309 9391 ((__INSTANCE__) == UART5) || \
mbed_official 74:9322579e4309 9392 ((__INSTANCE__) == USART6) || \
mbed_official 74:9322579e4309 9393 ((__INSTANCE__) == UART7) || \
mbed_official 74:9322579e4309 9394 ((__INSTANCE__) == UART8))
mbed_official 74:9322579e4309 9395
<> 144:ef7eb2e8f9f7 9396 /****************** UART Instances : Driver Enable *****************/
<> 144:ef7eb2e8f9f7 9397 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 144:ef7eb2e8f9f7 9398 ((__INSTANCE__) == USART2) || \
<> 144:ef7eb2e8f9f7 9399 ((__INSTANCE__) == USART3) || \
<> 144:ef7eb2e8f9f7 9400 ((__INSTANCE__) == UART4) || \
<> 144:ef7eb2e8f9f7 9401 ((__INSTANCE__) == UART5) || \
<> 144:ef7eb2e8f9f7 9402 ((__INSTANCE__) == USART6) || \
<> 144:ef7eb2e8f9f7 9403 ((__INSTANCE__) == UART7) || \
<> 144:ef7eb2e8f9f7 9404 ((__INSTANCE__) == UART8))
<> 144:ef7eb2e8f9f7 9405
mbed_official 74:9322579e4309 9406 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 74:9322579e4309 9407 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 74:9322579e4309 9408 ((__INSTANCE__) == USART2) || \
mbed_official 74:9322579e4309 9409 ((__INSTANCE__) == USART3) || \
mbed_official 74:9322579e4309 9410 ((__INSTANCE__) == UART4) || \
mbed_official 74:9322579e4309 9411 ((__INSTANCE__) == UART5) || \
mbed_official 74:9322579e4309 9412 ((__INSTANCE__) == USART6) || \
mbed_official 74:9322579e4309 9413 ((__INSTANCE__) == UART7) || \
mbed_official 74:9322579e4309 9414 ((__INSTANCE__) == UART8))
mbed_official 74:9322579e4309 9415
mbed_official 74:9322579e4309 9416 /********************* UART Instances : Smart card mode ***********************/
mbed_official 74:9322579e4309 9417 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 74:9322579e4309 9418 ((__INSTANCE__) == USART2) || \
mbed_official 74:9322579e4309 9419 ((__INSTANCE__) == USART3) || \
mbed_official 74:9322579e4309 9420 ((__INSTANCE__) == USART6))
mbed_official 74:9322579e4309 9421
mbed_official 74:9322579e4309 9422 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 74:9322579e4309 9423 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
mbed_official 74:9322579e4309 9424 ((__INSTANCE__) == USART2) || \
mbed_official 74:9322579e4309 9425 ((__INSTANCE__) == USART3) || \
mbed_official 74:9322579e4309 9426 ((__INSTANCE__) == UART4) || \
mbed_official 74:9322579e4309 9427 ((__INSTANCE__) == UART5) || \
mbed_official 74:9322579e4309 9428 ((__INSTANCE__) == USART6) || \
mbed_official 74:9322579e4309 9429 ((__INSTANCE__) == UART7) || \
mbed_official 74:9322579e4309 9430 ((__INSTANCE__) == UART8))
mbed_official 74:9322579e4309 9431
mbed_official 74:9322579e4309 9432 /****************************** IWDG Instances ********************************/
mbed_official 74:9322579e4309 9433 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
mbed_official 74:9322579e4309 9434
mbed_official 74:9322579e4309 9435 /****************************** WWDG Instances ********************************/
mbed_official 74:9322579e4309 9436 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
mbed_official 74:9322579e4309 9437
mbed_official 74:9322579e4309 9438
mbed_official 74:9322579e4309 9439 /******************************************************************************/
mbed_official 74:9322579e4309 9440 /* For a painless codes migration between the STM32F7xx device product */
mbed_official 74:9322579e4309 9441 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 74:9322579e4309 9442 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 74:9322579e4309 9443 /* No need to update developed interrupt code when moving across */
mbed_official 74:9322579e4309 9444 /* product lines within the same STM32F7 Family */
mbed_official 74:9322579e4309 9445 /******************************************************************************/
mbed_official 74:9322579e4309 9446
mbed_official 74:9322579e4309 9447 /* Aliases for __IRQn */
mbed_official 74:9322579e4309 9448 #define HASH_RNG_IRQn RNG_IRQn
mbed_official 74:9322579e4309 9449
mbed_official 74:9322579e4309 9450 /* Aliases for __IRQHandler */
mbed_official 74:9322579e4309 9451 #define HASH_RNG_IRQHandler RNG_IRQHandler
mbed_official 74:9322579e4309 9452
mbed_official 74:9322579e4309 9453 /**
mbed_official 74:9322579e4309 9454 * @}
mbed_official 74:9322579e4309 9455 */
mbed_official 74:9322579e4309 9456
mbed_official 74:9322579e4309 9457 /**
mbed_official 74:9322579e4309 9458 * @}
mbed_official 74:9322579e4309 9459 */
mbed_official 74:9322579e4309 9460
mbed_official 74:9322579e4309 9461 /**
mbed_official 74:9322579e4309 9462 * @}
mbed_official 74:9322579e4309 9463 */
mbed_official 74:9322579e4309 9464
mbed_official 74:9322579e4309 9465 #ifdef __cplusplus
mbed_official 74:9322579e4309 9466 }
mbed_official 74:9322579e4309 9467 #endif /* __cplusplus */
mbed_official 74:9322579e4309 9468
mbed_official 74:9322579e4309 9469 #endif /* __STM32F746xx_H */
mbed_official 74:9322579e4309 9470
mbed_official 74:9322579e4309 9471
mbed_official 74:9322579e4309 9472 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/