Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_GCC_ARM/startup_stm32f746xx.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file startup_stm32f746xx.s
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @Version V1.0.2
<> 144:ef7eb2e8f9f7 6 * @Date 21-September-2015
<> 144:ef7eb2e8f9f7 7 * @brief STM32F746xx Devices vector table for GCC based toolchain.
<> 144:ef7eb2e8f9f7 8 * This module performs:
<> 144:ef7eb2e8f9f7 9 * - Set the initial SP
<> 144:ef7eb2e8f9f7 10 * - Set the initial PC == Reset_Handler,
<> 144:ef7eb2e8f9f7 11 * - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 12 * - Branches to main in the C library (which eventually
<> 144:ef7eb2e8f9f7 13 * calls main()).
<> 144:ef7eb2e8f9f7 14 * After Reset the Cortex-M7 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 15 * priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 16 ******************************************************************************
<> 144:ef7eb2e8f9f7 17 * @attention
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 22 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 23 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 26 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 27 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 29 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 30 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 ******************************************************************************
<> 144:ef7eb2e8f9f7 44 */
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 .syntax unified
<> 144:ef7eb2e8f9f7 47 .cpu cortex-m7
<> 144:ef7eb2e8f9f7 48 .fpu softvfp
<> 144:ef7eb2e8f9f7 49 .thumb
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 .global g_pfnVectors
<> 144:ef7eb2e8f9f7 52 .global Default_Handler
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* start address for the initialization values of the .data section.
<> 144:ef7eb2e8f9f7 55 defined in linker script */
<> 144:ef7eb2e8f9f7 56 .word _sidata
<> 144:ef7eb2e8f9f7 57 /* start address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 58 .word _sdata
<> 144:ef7eb2e8f9f7 59 /* end address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 60 .word _edata
<> 144:ef7eb2e8f9f7 61 /* start address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 62 .word _sbss
<> 144:ef7eb2e8f9f7 63 /* end address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 64 .word _ebss
<> 144:ef7eb2e8f9f7 65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief This is the code that gets called when the processor first
<> 144:ef7eb2e8f9f7 69 * starts execution following a reset event. Only the absolutely
<> 144:ef7eb2e8f9f7 70 * necessary set is performed, after which the application
<> 144:ef7eb2e8f9f7 71 * supplied main() routine is called.
<> 144:ef7eb2e8f9f7 72 * @param None
<> 144:ef7eb2e8f9f7 73 * @retval : None
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 77 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 78 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 79 Reset_Handler:
<> 144:ef7eb2e8f9f7 80 ldr sp, =_estack /* set stack pointer */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* Copy the data segment initializers from flash to SRAM */
<> 144:ef7eb2e8f9f7 83 movs r1, #0
<> 144:ef7eb2e8f9f7 84 b LoopCopyDataInit
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 CopyDataInit:
<> 144:ef7eb2e8f9f7 87 ldr r3, =_sidata
<> 144:ef7eb2e8f9f7 88 ldr r3, [r3, r1]
<> 144:ef7eb2e8f9f7 89 str r3, [r0, r1]
<> 144:ef7eb2e8f9f7 90 adds r1, r1, #4
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 LoopCopyDataInit:
<> 144:ef7eb2e8f9f7 93 ldr r0, =_sdata
<> 144:ef7eb2e8f9f7 94 ldr r3, =_edata
<> 144:ef7eb2e8f9f7 95 adds r2, r0, r1
<> 144:ef7eb2e8f9f7 96 cmp r2, r3
<> 144:ef7eb2e8f9f7 97 bcc CopyDataInit
<> 144:ef7eb2e8f9f7 98 ldr r2, =_sbss
<> 144:ef7eb2e8f9f7 99 b LoopFillZerobss
<> 144:ef7eb2e8f9f7 100 /* Zero fill the bss segment. */
<> 144:ef7eb2e8f9f7 101 FillZerobss:
<> 144:ef7eb2e8f9f7 102 movs r3, #0
<> 144:ef7eb2e8f9f7 103 str r3, [r2], #4
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 LoopFillZerobss:
<> 144:ef7eb2e8f9f7 106 ldr r3, = _ebss
<> 144:ef7eb2e8f9f7 107 cmp r2, r3
<> 144:ef7eb2e8f9f7 108 bcc FillZerobss
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Call the clock system initialization function.*/
<> 144:ef7eb2e8f9f7 111 bl SystemInit
<> 144:ef7eb2e8f9f7 112 /* Call static constructors */
<> 144:ef7eb2e8f9f7 113 //bl __libc_init_array
<> 144:ef7eb2e8f9f7 114 /* Call the application's entry point.*/
<> 144:ef7eb2e8f9f7 115 //bl main
<> 144:ef7eb2e8f9f7 116 // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
<> 144:ef7eb2e8f9f7 117 // and when existing hardware_init_hook() and software_init_hook() before
<> 144:ef7eb2e8f9f7 118 // starting main(). software_init_hook() is available and has to be called due
<> 144:ef7eb2e8f9f7 119 // to initializsation when using rtos.
<> 144:ef7eb2e8f9f7 120 bl _start
<> 144:ef7eb2e8f9f7 121 bx lr
<> 144:ef7eb2e8f9f7 122 .size Reset_Handler, .-Reset_Handler
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief This is the code that gets called when the processor receives an
<> 144:ef7eb2e8f9f7 126 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 144:ef7eb2e8f9f7 127 * the system state for examination by a debugger.
<> 144:ef7eb2e8f9f7 128 * @param None
<> 144:ef7eb2e8f9f7 129 * @retval None
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 .section .text.Default_Handler,"ax",%progbits
<> 144:ef7eb2e8f9f7 132 Default_Handler:
<> 144:ef7eb2e8f9f7 133 Infinite_Loop:
<> 144:ef7eb2e8f9f7 134 b Infinite_Loop
<> 144:ef7eb2e8f9f7 135 .size Default_Handler, .-Default_Handler
<> 144:ef7eb2e8f9f7 136 /******************************************************************************
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 * The minimal vector table for a Cortex M7. Note that the proper constructs
<> 144:ef7eb2e8f9f7 139 * must be placed on this to ensure that it ends up at physical address
<> 144:ef7eb2e8f9f7 140 * 0x0000.0000.
<> 144:ef7eb2e8f9f7 141 *
<> 144:ef7eb2e8f9f7 142 *******************************************************************************/
<> 144:ef7eb2e8f9f7 143 .section .isr_vector,"a",%progbits
<> 144:ef7eb2e8f9f7 144 .type g_pfnVectors, %object
<> 144:ef7eb2e8f9f7 145 .size g_pfnVectors, .-g_pfnVectors
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 g_pfnVectors:
<> 144:ef7eb2e8f9f7 149 .word _estack
<> 144:ef7eb2e8f9f7 150 .word Reset_Handler
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 .word NMI_Handler
<> 144:ef7eb2e8f9f7 153 .word HardFault_Handler
<> 144:ef7eb2e8f9f7 154 .word MemManage_Handler
<> 144:ef7eb2e8f9f7 155 .word BusFault_Handler
<> 144:ef7eb2e8f9f7 156 .word UsageFault_Handler
<> 144:ef7eb2e8f9f7 157 .word 0
<> 144:ef7eb2e8f9f7 158 .word 0
<> 144:ef7eb2e8f9f7 159 .word 0
<> 144:ef7eb2e8f9f7 160 .word 0
<> 144:ef7eb2e8f9f7 161 .word SVC_Handler
<> 144:ef7eb2e8f9f7 162 .word DebugMon_Handler
<> 144:ef7eb2e8f9f7 163 .word 0
<> 144:ef7eb2e8f9f7 164 .word PendSV_Handler
<> 144:ef7eb2e8f9f7 165 .word SysTick_Handler
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* External Interrupts */
<> 144:ef7eb2e8f9f7 168 .word WWDG_IRQHandler /* Window WatchDog */
<> 144:ef7eb2e8f9f7 169 .word PVD_IRQHandler /* PVD through EXTI Line detection */
<> 144:ef7eb2e8f9f7 170 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
<> 144:ef7eb2e8f9f7 171 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
<> 144:ef7eb2e8f9f7 172 .word FLASH_IRQHandler /* FLASH */
<> 144:ef7eb2e8f9f7 173 .word RCC_IRQHandler /* RCC */
<> 144:ef7eb2e8f9f7 174 .word EXTI0_IRQHandler /* EXTI Line0 */
<> 144:ef7eb2e8f9f7 175 .word EXTI1_IRQHandler /* EXTI Line1 */
<> 144:ef7eb2e8f9f7 176 .word EXTI2_IRQHandler /* EXTI Line2 */
<> 144:ef7eb2e8f9f7 177 .word EXTI3_IRQHandler /* EXTI Line3 */
<> 144:ef7eb2e8f9f7 178 .word EXTI4_IRQHandler /* EXTI Line4 */
<> 144:ef7eb2e8f9f7 179 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
<> 144:ef7eb2e8f9f7 180 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
<> 144:ef7eb2e8f9f7 181 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
<> 144:ef7eb2e8f9f7 182 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
<> 144:ef7eb2e8f9f7 183 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
<> 144:ef7eb2e8f9f7 184 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
<> 144:ef7eb2e8f9f7 185 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
<> 144:ef7eb2e8f9f7 186 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
<> 144:ef7eb2e8f9f7 187 .word CAN1_TX_IRQHandler /* CAN1 TX */
<> 144:ef7eb2e8f9f7 188 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
<> 144:ef7eb2e8f9f7 189 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
<> 144:ef7eb2e8f9f7 190 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
<> 144:ef7eb2e8f9f7 191 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
<> 144:ef7eb2e8f9f7 192 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
<> 144:ef7eb2e8f9f7 193 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
<> 144:ef7eb2e8f9f7 194 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
<> 144:ef7eb2e8f9f7 195 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
<> 144:ef7eb2e8f9f7 196 .word TIM2_IRQHandler /* TIM2 */
<> 144:ef7eb2e8f9f7 197 .word TIM3_IRQHandler /* TIM3 */
<> 144:ef7eb2e8f9f7 198 .word TIM4_IRQHandler /* TIM4 */
<> 144:ef7eb2e8f9f7 199 .word I2C1_EV_IRQHandler /* I2C1 Event */
<> 144:ef7eb2e8f9f7 200 .word I2C1_ER_IRQHandler /* I2C1 Error */
<> 144:ef7eb2e8f9f7 201 .word I2C2_EV_IRQHandler /* I2C2 Event */
<> 144:ef7eb2e8f9f7 202 .word I2C2_ER_IRQHandler /* I2C2 Error */
<> 144:ef7eb2e8f9f7 203 .word SPI1_IRQHandler /* SPI1 */
<> 144:ef7eb2e8f9f7 204 .word SPI2_IRQHandler /* SPI2 */
<> 144:ef7eb2e8f9f7 205 .word USART1_IRQHandler /* USART1 */
<> 144:ef7eb2e8f9f7 206 .word USART2_IRQHandler /* USART2 */
<> 144:ef7eb2e8f9f7 207 .word USART3_IRQHandler /* USART3 */
<> 144:ef7eb2e8f9f7 208 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
<> 144:ef7eb2e8f9f7 209 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
<> 144:ef7eb2e8f9f7 210 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
<> 144:ef7eb2e8f9f7 211 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
<> 144:ef7eb2e8f9f7 212 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
<> 144:ef7eb2e8f9f7 213 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
<> 144:ef7eb2e8f9f7 214 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
<> 144:ef7eb2e8f9f7 215 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
<> 144:ef7eb2e8f9f7 216 .word FMC_IRQHandler /* FMC */
<> 144:ef7eb2e8f9f7 217 .word SDMMC1_IRQHandler /* SDMMC1 */
<> 144:ef7eb2e8f9f7 218 .word TIM5_IRQHandler /* TIM5 */
<> 144:ef7eb2e8f9f7 219 .word SPI3_IRQHandler /* SPI3 */
<> 144:ef7eb2e8f9f7 220 .word UART4_IRQHandler /* UART4 */
<> 144:ef7eb2e8f9f7 221 .word UART5_IRQHandler /* UART5 */
<> 144:ef7eb2e8f9f7 222 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
<> 144:ef7eb2e8f9f7 223 .word TIM7_IRQHandler /* TIM7 */
<> 144:ef7eb2e8f9f7 224 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
<> 144:ef7eb2e8f9f7 225 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
<> 144:ef7eb2e8f9f7 226 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
<> 144:ef7eb2e8f9f7 227 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
<> 144:ef7eb2e8f9f7 228 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
<> 144:ef7eb2e8f9f7 229 .word ETH_IRQHandler /* Ethernet */
<> 144:ef7eb2e8f9f7 230 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
<> 144:ef7eb2e8f9f7 231 .word CAN2_TX_IRQHandler /* CAN2 TX */
<> 144:ef7eb2e8f9f7 232 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
<> 144:ef7eb2e8f9f7 233 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
<> 144:ef7eb2e8f9f7 234 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
<> 144:ef7eb2e8f9f7 235 .word OTG_FS_IRQHandler /* USB OTG FS */
<> 144:ef7eb2e8f9f7 236 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
<> 144:ef7eb2e8f9f7 237 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
<> 144:ef7eb2e8f9f7 238 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
<> 144:ef7eb2e8f9f7 239 .word USART6_IRQHandler /* USART6 */
<> 144:ef7eb2e8f9f7 240 .word I2C3_EV_IRQHandler /* I2C3 event */
<> 144:ef7eb2e8f9f7 241 .word I2C3_ER_IRQHandler /* I2C3 error */
<> 144:ef7eb2e8f9f7 242 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
<> 144:ef7eb2e8f9f7 243 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
<> 144:ef7eb2e8f9f7 244 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
<> 144:ef7eb2e8f9f7 245 .word OTG_HS_IRQHandler /* USB OTG HS */
<> 144:ef7eb2e8f9f7 246 .word DCMI_IRQHandler /* DCMI */
<> 144:ef7eb2e8f9f7 247 .word 0 /* Reserved */
<> 144:ef7eb2e8f9f7 248 .word RNG_IRQHandler /* Rng */
<> 144:ef7eb2e8f9f7 249 .word FPU_IRQHandler /* FPU */
<> 144:ef7eb2e8f9f7 250 .word UART7_IRQHandler /* UART7 */
<> 144:ef7eb2e8f9f7 251 .word UART8_IRQHandler /* UART8 */
<> 144:ef7eb2e8f9f7 252 .word SPI4_IRQHandler /* SPI4 */
<> 144:ef7eb2e8f9f7 253 .word SPI5_IRQHandler /* SPI5 */
<> 144:ef7eb2e8f9f7 254 .word SPI6_IRQHandler /* SPI6 */
<> 144:ef7eb2e8f9f7 255 .word SAI1_IRQHandler /* SAI1 */
<> 144:ef7eb2e8f9f7 256 .word LTDC_IRQHandler /* LTDC */
<> 144:ef7eb2e8f9f7 257 .word LTDC_ER_IRQHandler /* LTDC error */
<> 144:ef7eb2e8f9f7 258 .word DMA2D_IRQHandler /* DMA2D */
<> 144:ef7eb2e8f9f7 259 .word SAI2_IRQHandler /* SAI2 */
<> 144:ef7eb2e8f9f7 260 .word QUADSPI_IRQHandler /* QUADSPI */
<> 144:ef7eb2e8f9f7 261 .word LPTIM1_IRQHandler /* LPTIM1 */
<> 144:ef7eb2e8f9f7 262 .word CEC_IRQHandler /* HDMI_CEC */
<> 144:ef7eb2e8f9f7 263 .word I2C4_EV_IRQHandler /* I2C4 Event */
<> 144:ef7eb2e8f9f7 264 .word I2C4_ER_IRQHandler /* I2C4 Error */
<> 144:ef7eb2e8f9f7 265 .word SPDIF_RX_IRQHandler /* SPDIF_RX */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /*******************************************************************************
<> 144:ef7eb2e8f9f7 268 *
<> 144:ef7eb2e8f9f7 269 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 144:ef7eb2e8f9f7 270 * As they are weak aliases, any function with the same name will override
<> 144:ef7eb2e8f9f7 271 * this definition.
<> 144:ef7eb2e8f9f7 272 *
<> 144:ef7eb2e8f9f7 273 *******************************************************************************/
<> 144:ef7eb2e8f9f7 274 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 275 .thumb_set NMI_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 278 .thumb_set HardFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 .weak MemManage_Handler
<> 144:ef7eb2e8f9f7 281 .thumb_set MemManage_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 .weak BusFault_Handler
<> 144:ef7eb2e8f9f7 284 .thumb_set BusFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 .weak UsageFault_Handler
<> 144:ef7eb2e8f9f7 287 .thumb_set UsageFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 290 .thumb_set SVC_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 .weak DebugMon_Handler
<> 144:ef7eb2e8f9f7 293 .thumb_set DebugMon_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 296 .thumb_set PendSV_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 299 .thumb_set SysTick_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 .weak WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 302 .thumb_set WWDG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 .weak PVD_IRQHandler
<> 144:ef7eb2e8f9f7 305 .thumb_set PVD_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 .weak TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 308 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 .weak RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 311 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 .weak FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 314 .thumb_set FLASH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 .weak RCC_IRQHandler
<> 144:ef7eb2e8f9f7 317 .thumb_set RCC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 .weak EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 320 .thumb_set EXTI0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 .weak EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 323 .thumb_set EXTI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 .weak EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 326 .thumb_set EXTI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 .weak EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 329 .thumb_set EXTI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 .weak EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 332 .thumb_set EXTI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 .weak DMA1_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 335 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 .weak DMA1_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 338 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 .weak DMA1_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 341 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 .weak DMA1_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 344 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 .weak DMA1_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 347 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 .weak DMA1_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 350 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 .weak DMA1_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 353 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 .weak ADC_IRQHandler
<> 144:ef7eb2e8f9f7 356 .thumb_set ADC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 .weak CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 359 .thumb_set CAN1_TX_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 .weak CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 362 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 .weak CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 365 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 .weak CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 368 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 .weak EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 371 .thumb_set EXTI9_5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 .weak TIM1_BRK_TIM9_IRQHandler
<> 144:ef7eb2e8f9f7 374 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 .weak TIM1_UP_TIM10_IRQHandler
<> 144:ef7eb2e8f9f7 377 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 .weak TIM1_TRG_COM_TIM11_IRQHandler
<> 144:ef7eb2e8f9f7 380 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 .weak TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 383 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 .weak TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 386 .thumb_set TIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 .weak TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 389 .thumb_set TIM3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 .weak TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 392 .thumb_set TIM4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 .weak I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 395 .thumb_set I2C1_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 .weak I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 398 .thumb_set I2C1_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 .weak I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 401 .thumb_set I2C2_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 .weak I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 404 .thumb_set I2C2_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 407 .thumb_set SPI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 .weak SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 410 .thumb_set SPI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 .weak USART1_IRQHandler
<> 144:ef7eb2e8f9f7 413 .thumb_set USART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 .weak USART2_IRQHandler
<> 144:ef7eb2e8f9f7 416 .thumb_set USART2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 .weak USART3_IRQHandler
<> 144:ef7eb2e8f9f7 419 .thumb_set USART3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 .weak EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 422 .thumb_set EXTI15_10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 .weak RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 425 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 .weak OTG_FS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 428 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 .weak TIM8_BRK_TIM12_IRQHandler
<> 144:ef7eb2e8f9f7 431 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 .weak TIM8_UP_TIM13_IRQHandler
<> 144:ef7eb2e8f9f7 434 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 .weak TIM8_TRG_COM_TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 437 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 .weak TIM8_CC_IRQHandler
<> 144:ef7eb2e8f9f7 440 .thumb_set TIM8_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 .weak DMA1_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 443 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 .weak FMC_IRQHandler
<> 144:ef7eb2e8f9f7 446 .thumb_set FMC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 .weak SDMMC1_IRQHandler
<> 144:ef7eb2e8f9f7 449 .thumb_set SDMMC1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 .weak TIM5_IRQHandler
<> 144:ef7eb2e8f9f7 452 .thumb_set TIM5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 .weak SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 455 .thumb_set SPI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 .weak UART4_IRQHandler
<> 144:ef7eb2e8f9f7 458 .thumb_set UART4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 .weak UART5_IRQHandler
<> 144:ef7eb2e8f9f7 461 .thumb_set UART5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 .weak TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 464 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 .weak TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 467 .thumb_set TIM7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 .weak DMA2_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 470 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 .weak DMA2_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 473 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 .weak DMA2_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 476 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 .weak DMA2_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 479 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 .weak DMA2_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 482 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 .weak DMA2_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 485 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 .weak ETH_IRQHandler
<> 144:ef7eb2e8f9f7 488 .thumb_set ETH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 .weak ETH_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 491 .thumb_set ETH_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 .weak CAN2_TX_IRQHandler
<> 144:ef7eb2e8f9f7 494 .thumb_set CAN2_TX_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 .weak CAN2_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 497 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 .weak CAN2_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 500 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 .weak CAN2_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 503 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 .weak OTG_FS_IRQHandler
<> 144:ef7eb2e8f9f7 506 .thumb_set OTG_FS_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 .weak DMA2_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 509 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 .weak DMA2_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 512 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 .weak DMA2_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 515 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 .weak USART6_IRQHandler
<> 144:ef7eb2e8f9f7 518 .thumb_set USART6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 .weak I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 521 .thumb_set I2C3_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 .weak I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 524 .thumb_set I2C3_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 .weak OTG_HS_EP1_OUT_IRQHandler
<> 144:ef7eb2e8f9f7 527 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 .weak OTG_HS_EP1_IN_IRQHandler
<> 144:ef7eb2e8f9f7 530 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 .weak OTG_HS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 533 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 .weak OTG_HS_IRQHandler
<> 144:ef7eb2e8f9f7 536 .thumb_set OTG_HS_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 .weak DCMI_IRQHandler
<> 144:ef7eb2e8f9f7 539 .thumb_set DCMI_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 .weak RNG_IRQHandler
<> 144:ef7eb2e8f9f7 542 .thumb_set RNG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 .weak FPU_IRQHandler
<> 144:ef7eb2e8f9f7 545 .thumb_set FPU_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 .weak UART7_IRQHandler
<> 144:ef7eb2e8f9f7 548 .thumb_set UART7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 .weak UART8_IRQHandler
<> 144:ef7eb2e8f9f7 551 .thumb_set UART8_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 .weak SPI4_IRQHandler
<> 144:ef7eb2e8f9f7 554 .thumb_set SPI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 .weak SPI5_IRQHandler
<> 144:ef7eb2e8f9f7 557 .thumb_set SPI5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 .weak SPI6_IRQHandler
<> 144:ef7eb2e8f9f7 560 .thumb_set SPI6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 .weak SAI1_IRQHandler
<> 144:ef7eb2e8f9f7 563 .thumb_set SAI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 .weak LTDC_IRQHandler
<> 144:ef7eb2e8f9f7 566 .thumb_set LTDC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 .weak LTDC_ER_IRQHandler
<> 144:ef7eb2e8f9f7 569 .thumb_set LTDC_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 .weak DMA2D_IRQHandler
<> 144:ef7eb2e8f9f7 572 .thumb_set DMA2D_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 .weak SAI2_IRQHandler
<> 144:ef7eb2e8f9f7 575 .thumb_set SAI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 .weak QUADSPI_IRQHandler
<> 144:ef7eb2e8f9f7 578 .thumb_set QUADSPI_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 .weak LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 581 .thumb_set LPTIM1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 .weak CEC_IRQHandler
<> 144:ef7eb2e8f9f7 584 .thumb_set CEC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 .weak I2C4_EV_IRQHandler
<> 144:ef7eb2e8f9f7 587 .thumb_set I2C4_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 .weak I2C4_ER_IRQHandler
<> 144:ef7eb2e8f9f7 590 .thumb_set I2C4_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 .weak SPDIF_RX_IRQHandler
<> 144:ef7eb2e8f9f7 593 .thumb_set SPDIF_RX_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 596