Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/TOOLCHAIN_ARM_MICRO/startup_stm32f746ng.S@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32f746xx.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Version : V1.0.2
<> 144:ef7eb2e8f9f7 5 ;* Date : 21-September-2015
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the CortexM7 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 16 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 17 ;
<> 144:ef7eb2e8f9f7 18 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 ;*
<> 144:ef7eb2e8f9f7 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 ;
<> 144:ef7eb2e8f9f7 40 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 ; Amount of memory (in bytes) allocated for Stack
<> 144:ef7eb2e8f9f7 43 ; Tailor this value to your application needs
<> 144:ef7eb2e8f9f7 44 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 46 ; </h>
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 51 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 54 __initial_sp EQU 0x20050000 ; Top of RAM
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 ; <h> Heap Configuration
<> 144:ef7eb2e8f9f7 58 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 59 ; </h>
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 Heap_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 64 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 65 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 __heap_base
<> 144:ef7eb2e8f9f7 68 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 69 __heap_limit EQU (__initial_sp - Stack_Size)
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 PRESERVE8
<> 144:ef7eb2e8f9f7 72 THUMB
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 76 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 77 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 78 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 79 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 82 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 83 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 84 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 85 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 86 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 87 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 91 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 92 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 93 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 94 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 95 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 96 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 ; External Interrupts
<> 144:ef7eb2e8f9f7 99 DCD WWDG_IRQHandler ; Window WatchDog
<> 144:ef7eb2e8f9f7 100 DCD PVD_IRQHandler ; PVD through EXTI Line detection
<> 144:ef7eb2e8f9f7 101 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
<> 144:ef7eb2e8f9f7 102 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
<> 144:ef7eb2e8f9f7 103 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 104 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 105 DCD EXTI0_IRQHandler ; EXTI Line0
<> 144:ef7eb2e8f9f7 106 DCD EXTI1_IRQHandler ; EXTI Line1
<> 144:ef7eb2e8f9f7 107 DCD EXTI2_IRQHandler ; EXTI Line2
<> 144:ef7eb2e8f9f7 108 DCD EXTI3_IRQHandler ; EXTI Line3
<> 144:ef7eb2e8f9f7 109 DCD EXTI4_IRQHandler ; EXTI Line4
<> 144:ef7eb2e8f9f7 110 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
<> 144:ef7eb2e8f9f7 111 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
<> 144:ef7eb2e8f9f7 112 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
<> 144:ef7eb2e8f9f7 113 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
<> 144:ef7eb2e8f9f7 114 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
<> 144:ef7eb2e8f9f7 115 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
<> 144:ef7eb2e8f9f7 116 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
<> 144:ef7eb2e8f9f7 117 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
<> 144:ef7eb2e8f9f7 118 DCD CAN1_TX_IRQHandler ; CAN1 TX
<> 144:ef7eb2e8f9f7 119 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
<> 144:ef7eb2e8f9f7 120 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
<> 144:ef7eb2e8f9f7 121 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
<> 144:ef7eb2e8f9f7 122 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
<> 144:ef7eb2e8f9f7 123 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
<> 144:ef7eb2e8f9f7 124 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
<> 144:ef7eb2e8f9f7 125 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
<> 144:ef7eb2e8f9f7 126 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
<> 144:ef7eb2e8f9f7 127 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 128 DCD TIM3_IRQHandler ; TIM3
<> 144:ef7eb2e8f9f7 129 DCD TIM4_IRQHandler ; TIM4
<> 144:ef7eb2e8f9f7 130 DCD I2C1_EV_IRQHandler ; I2C1 Event
<> 144:ef7eb2e8f9f7 131 DCD I2C1_ER_IRQHandler ; I2C1 Error
<> 144:ef7eb2e8f9f7 132 DCD I2C2_EV_IRQHandler ; I2C2 Event
<> 144:ef7eb2e8f9f7 133 DCD I2C2_ER_IRQHandler ; I2C2 Error
<> 144:ef7eb2e8f9f7 134 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 135 DCD SPI2_IRQHandler ; SPI2
<> 144:ef7eb2e8f9f7 136 DCD USART1_IRQHandler ; USART1
<> 144:ef7eb2e8f9f7 137 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 138 DCD USART3_IRQHandler ; USART3
<> 144:ef7eb2e8f9f7 139 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
<> 144:ef7eb2e8f9f7 140 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
<> 144:ef7eb2e8f9f7 141 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
<> 144:ef7eb2e8f9f7 142 DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
<> 144:ef7eb2e8f9f7 143 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
<> 144:ef7eb2e8f9f7 144 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
<> 144:ef7eb2e8f9f7 145 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
<> 144:ef7eb2e8f9f7 146 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
<> 144:ef7eb2e8f9f7 147 DCD FMC_IRQHandler ; FMC
<> 144:ef7eb2e8f9f7 148 DCD SDMMC1_IRQHandler ; SDMMC1
<> 144:ef7eb2e8f9f7 149 DCD TIM5_IRQHandler ; TIM5
<> 144:ef7eb2e8f9f7 150 DCD SPI3_IRQHandler ; SPI3
<> 144:ef7eb2e8f9f7 151 DCD UART4_IRQHandler ; UART4
<> 144:ef7eb2e8f9f7 152 DCD UART5_IRQHandler ; UART5
<> 144:ef7eb2e8f9f7 153 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
<> 144:ef7eb2e8f9f7 154 DCD TIM7_IRQHandler ; TIM7
<> 144:ef7eb2e8f9f7 155 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
<> 144:ef7eb2e8f9f7 156 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
<> 144:ef7eb2e8f9f7 157 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
<> 144:ef7eb2e8f9f7 158 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
<> 144:ef7eb2e8f9f7 159 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
<> 144:ef7eb2e8f9f7 160 DCD ETH_IRQHandler ; Ethernet
<> 144:ef7eb2e8f9f7 161 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
<> 144:ef7eb2e8f9f7 162 DCD CAN2_TX_IRQHandler ; CAN2 TX
<> 144:ef7eb2e8f9f7 163 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
<> 144:ef7eb2e8f9f7 164 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
<> 144:ef7eb2e8f9f7 165 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
<> 144:ef7eb2e8f9f7 166 DCD OTG_FS_IRQHandler ; USB OTG FS
<> 144:ef7eb2e8f9f7 167 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
<> 144:ef7eb2e8f9f7 168 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
<> 144:ef7eb2e8f9f7 169 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
<> 144:ef7eb2e8f9f7 170 DCD USART6_IRQHandler ; USART6
<> 144:ef7eb2e8f9f7 171 DCD I2C3_EV_IRQHandler ; I2C3 event
<> 144:ef7eb2e8f9f7 172 DCD I2C3_ER_IRQHandler ; I2C3 error
<> 144:ef7eb2e8f9f7 173 DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
<> 144:ef7eb2e8f9f7 174 DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
<> 144:ef7eb2e8f9f7 175 DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
<> 144:ef7eb2e8f9f7 176 DCD OTG_HS_IRQHandler ; USB OTG HS
<> 144:ef7eb2e8f9f7 177 DCD DCMI_IRQHandler ; DCMI
<> 144:ef7eb2e8f9f7 178 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 179 DCD RNG_IRQHandler ; Hash and Rng
<> 144:ef7eb2e8f9f7 180 DCD FPU_IRQHandler ; FPU
<> 144:ef7eb2e8f9f7 181 DCD UART7_IRQHandler ; UART7
<> 144:ef7eb2e8f9f7 182 DCD UART8_IRQHandler ; UART8
<> 144:ef7eb2e8f9f7 183 DCD SPI4_IRQHandler ; SPI4
<> 144:ef7eb2e8f9f7 184 DCD SPI5_IRQHandler ; SPI5
<> 144:ef7eb2e8f9f7 185 DCD SPI6_IRQHandler ; SPI6
<> 144:ef7eb2e8f9f7 186 DCD SAI1_IRQHandler ; SAI1
<> 144:ef7eb2e8f9f7 187 DCD LTDC_IRQHandler ; LTDC
<> 144:ef7eb2e8f9f7 188 DCD LTDC_ER_IRQHandler ; LTDC error
<> 144:ef7eb2e8f9f7 189 DCD DMA2D_IRQHandler ; DMA2D
<> 144:ef7eb2e8f9f7 190 DCD SAI2_IRQHandler ; SAI2
<> 144:ef7eb2e8f9f7 191 DCD QUADSPI_IRQHandler ; QUADSPI
<> 144:ef7eb2e8f9f7 192 DCD LPTIM1_IRQHandler ; LPTIM1
<> 144:ef7eb2e8f9f7 193 DCD CEC_IRQHandler ; HDMI_CEC
<> 144:ef7eb2e8f9f7 194 DCD I2C4_EV_IRQHandler ; I2C4 Event
<> 144:ef7eb2e8f9f7 195 DCD I2C4_ER_IRQHandler ; I2C4 Error
<> 144:ef7eb2e8f9f7 196 DCD SPDIF_RX_IRQHandler ; SPDIF_RX
<> 144:ef7eb2e8f9f7 197 __Vectors_End
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 ; Reset handler
<> 144:ef7eb2e8f9f7 204 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 205 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 206 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 207 IMPORT __main
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 210 BLX R0
<> 144:ef7eb2e8f9f7 211 LDR R0, =__main
<> 144:ef7eb2e8f9f7 212 BX R0
<> 144:ef7eb2e8f9f7 213 ENDP
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 218 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 219 B .
<> 144:ef7eb2e8f9f7 220 ENDP
<> 144:ef7eb2e8f9f7 221 HardFault_Handler\
<> 144:ef7eb2e8f9f7 222 PROC
<> 144:ef7eb2e8f9f7 223 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 224 B .
<> 144:ef7eb2e8f9f7 225 ENDP
<> 144:ef7eb2e8f9f7 226 MemManage_Handler\
<> 144:ef7eb2e8f9f7 227 PROC
<> 144:ef7eb2e8f9f7 228 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 229 B .
<> 144:ef7eb2e8f9f7 230 ENDP
<> 144:ef7eb2e8f9f7 231 BusFault_Handler\
<> 144:ef7eb2e8f9f7 232 PROC
<> 144:ef7eb2e8f9f7 233 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 234 B .
<> 144:ef7eb2e8f9f7 235 ENDP
<> 144:ef7eb2e8f9f7 236 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 237 PROC
<> 144:ef7eb2e8f9f7 238 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 239 B .
<> 144:ef7eb2e8f9f7 240 ENDP
<> 144:ef7eb2e8f9f7 241 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 242 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 243 B .
<> 144:ef7eb2e8f9f7 244 ENDP
<> 144:ef7eb2e8f9f7 245 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 246 PROC
<> 144:ef7eb2e8f9f7 247 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 248 B .
<> 144:ef7eb2e8f9f7 249 ENDP
<> 144:ef7eb2e8f9f7 250 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 251 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 252 B .
<> 144:ef7eb2e8f9f7 253 ENDP
<> 144:ef7eb2e8f9f7 254 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 255 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 256 B .
<> 144:ef7eb2e8f9f7 257 ENDP
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 Default_Handler PROC
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 262 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 263 EXPORT TAMP_STAMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 264 EXPORT RTC_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 265 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 266 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 267 EXPORT EXTI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 268 EXPORT EXTI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 269 EXPORT EXTI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 270 EXPORT EXTI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 271 EXPORT EXTI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 272 EXPORT DMA1_Stream0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 273 EXPORT DMA1_Stream1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 274 EXPORT DMA1_Stream2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 275 EXPORT DMA1_Stream3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 276 EXPORT DMA1_Stream4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 277 EXPORT DMA1_Stream5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 278 EXPORT DMA1_Stream6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 279 EXPORT ADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 280 EXPORT CAN1_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 281 EXPORT CAN1_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 282 EXPORT CAN1_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 283 EXPORT CAN1_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 284 EXPORT EXTI9_5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 285 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 286 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 287 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 288 EXPORT TIM1_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 289 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 290 EXPORT TIM3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 291 EXPORT TIM4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 292 EXPORT I2C1_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 293 EXPORT I2C1_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 294 EXPORT I2C2_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 295 EXPORT I2C2_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 296 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 297 EXPORT SPI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 298 EXPORT USART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 299 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 300 EXPORT USART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 EXPORT EXTI15_10_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 302 EXPORT RTC_Alarm_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 303 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 304 EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 305 EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 306 EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 307 EXPORT TIM8_CC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 EXPORT DMA1_Stream7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 309 EXPORT FMC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 310 EXPORT SDMMC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 311 EXPORT TIM5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 312 EXPORT SPI3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 313 EXPORT UART4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 314 EXPORT UART5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 315 EXPORT TIM6_DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 316 EXPORT TIM7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 317 EXPORT DMA2_Stream0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 318 EXPORT DMA2_Stream1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 319 EXPORT DMA2_Stream2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 320 EXPORT DMA2_Stream3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 321 EXPORT DMA2_Stream4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 322 EXPORT ETH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 323 EXPORT ETH_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 324 EXPORT CAN2_TX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 325 EXPORT CAN2_RX0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 326 EXPORT CAN2_RX1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 327 EXPORT CAN2_SCE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 328 EXPORT OTG_FS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 329 EXPORT DMA2_Stream5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 330 EXPORT DMA2_Stream6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 331 EXPORT DMA2_Stream7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 332 EXPORT USART6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 333 EXPORT I2C3_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 334 EXPORT I2C3_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 335 EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 336 EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 337 EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 338 EXPORT OTG_HS_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 339 EXPORT DCMI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 340 EXPORT RNG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 341 EXPORT FPU_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 342 EXPORT UART7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 343 EXPORT UART8_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 344 EXPORT SPI4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 345 EXPORT SPI5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 346 EXPORT SPI6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 347 EXPORT SAI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 348 EXPORT LTDC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 349 EXPORT LTDC_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 350 EXPORT DMA2D_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 351 EXPORT SAI2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 352 EXPORT QUADSPI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 353 EXPORT LPTIM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 354 EXPORT CEC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 355 EXPORT I2C4_EV_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 356 EXPORT I2C4_ER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 357 EXPORT SPDIF_RX_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 360 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 361 TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 362 RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 363 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 364 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 365 EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 366 EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 367 EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 368 EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 369 EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 370 DMA1_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 371 DMA1_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 372 DMA1_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 373 DMA1_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 374 DMA1_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 375 DMA1_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 376 DMA1_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 377 ADC_IRQHandler
<> 144:ef7eb2e8f9f7 378 CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 379 CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 380 CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 381 CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 382 EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 383 TIM1_BRK_TIM9_IRQHandler
<> 144:ef7eb2e8f9f7 384 TIM1_UP_TIM10_IRQHandler
<> 144:ef7eb2e8f9f7 385 TIM1_TRG_COM_TIM11_IRQHandler
<> 144:ef7eb2e8f9f7 386 TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 387 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 388 TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 389 TIM4_IRQHandler
<> 144:ef7eb2e8f9f7 390 I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 391 I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 392 I2C2_EV_IRQHandler
<> 144:ef7eb2e8f9f7 393 I2C2_ER_IRQHandler
<> 144:ef7eb2e8f9f7 394 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 395 SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 396 USART1_IRQHandler
<> 144:ef7eb2e8f9f7 397 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 398 USART3_IRQHandler
<> 144:ef7eb2e8f9f7 399 EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 400 RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 401 OTG_FS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 402 TIM8_BRK_TIM12_IRQHandler
<> 144:ef7eb2e8f9f7 403 TIM8_UP_TIM13_IRQHandler
<> 144:ef7eb2e8f9f7 404 TIM8_TRG_COM_TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 405 TIM8_CC_IRQHandler
<> 144:ef7eb2e8f9f7 406 DMA1_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 407 FMC_IRQHandler
<> 144:ef7eb2e8f9f7 408 SDMMC1_IRQHandler
<> 144:ef7eb2e8f9f7 409 TIM5_IRQHandler
<> 144:ef7eb2e8f9f7 410 SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 411 UART4_IRQHandler
<> 144:ef7eb2e8f9f7 412 UART5_IRQHandler
<> 144:ef7eb2e8f9f7 413 TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 414 TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 415 DMA2_Stream0_IRQHandler
<> 144:ef7eb2e8f9f7 416 DMA2_Stream1_IRQHandler
<> 144:ef7eb2e8f9f7 417 DMA2_Stream2_IRQHandler
<> 144:ef7eb2e8f9f7 418 DMA2_Stream3_IRQHandler
<> 144:ef7eb2e8f9f7 419 DMA2_Stream4_IRQHandler
<> 144:ef7eb2e8f9f7 420 ETH_IRQHandler
<> 144:ef7eb2e8f9f7 421 ETH_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 422 CAN2_TX_IRQHandler
<> 144:ef7eb2e8f9f7 423 CAN2_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 424 CAN2_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 425 CAN2_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 426 OTG_FS_IRQHandler
<> 144:ef7eb2e8f9f7 427 DMA2_Stream5_IRQHandler
<> 144:ef7eb2e8f9f7 428 DMA2_Stream6_IRQHandler
<> 144:ef7eb2e8f9f7 429 DMA2_Stream7_IRQHandler
<> 144:ef7eb2e8f9f7 430 USART6_IRQHandler
<> 144:ef7eb2e8f9f7 431 I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 432 I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 433 OTG_HS_EP1_OUT_IRQHandler
<> 144:ef7eb2e8f9f7 434 OTG_HS_EP1_IN_IRQHandler
<> 144:ef7eb2e8f9f7 435 OTG_HS_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 436 OTG_HS_IRQHandler
<> 144:ef7eb2e8f9f7 437 DCMI_IRQHandler
<> 144:ef7eb2e8f9f7 438 RNG_IRQHandler
<> 144:ef7eb2e8f9f7 439 FPU_IRQHandler
<> 144:ef7eb2e8f9f7 440 UART7_IRQHandler
<> 144:ef7eb2e8f9f7 441 UART8_IRQHandler
<> 144:ef7eb2e8f9f7 442 SPI4_IRQHandler
<> 144:ef7eb2e8f9f7 443 SPI5_IRQHandler
<> 144:ef7eb2e8f9f7 444 SPI6_IRQHandler
<> 144:ef7eb2e8f9f7 445 SAI1_IRQHandler
<> 144:ef7eb2e8f9f7 446 LTDC_IRQHandler
<> 144:ef7eb2e8f9f7 447 LTDC_ER_IRQHandler
<> 144:ef7eb2e8f9f7 448 DMA2D_IRQHandler
<> 144:ef7eb2e8f9f7 449 SAI2_IRQHandler
<> 144:ef7eb2e8f9f7 450 QUADSPI_IRQHandler
<> 144:ef7eb2e8f9f7 451 LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 452 CEC_IRQHandler
<> 144:ef7eb2e8f9f7 453 I2C4_EV_IRQHandler
<> 144:ef7eb2e8f9f7 454 I2C4_ER_IRQHandler
<> 144:ef7eb2e8f9f7 455 SPDIF_RX_IRQHandler
<> 144:ef7eb2e8f9f7 456 B .
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 ENDP
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 ALIGN
<> 144:ef7eb2e8f9f7 461 END
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****