Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_ll_sdmmc.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_ll_sdmmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.2
<> 144:ef7eb2e8f9f7 6 * @date 11-December-2015
<> 144:ef7eb2e8f9f7 7 * @brief SDMMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the SDMMC peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + I/O operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### SDMMC peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
<> 144:ef7eb2e8f9f7 21 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
<> 144:ef7eb2e8f9f7 22 devices.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 [..] The SDIO features include the following:
<> 144:ef7eb2e8f9f7 25 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
<> 144:ef7eb2e8f9f7 26 for three different databus modes: 1-bit (default), 4-bit and 8-bit
<> 144:ef7eb2e8f9f7 27 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
<> 144:ef7eb2e8f9f7 28 (+) Full compliance with SD Memory Card Specifications Version 2.0
<> 144:ef7eb2e8f9f7 29 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
<> 144:ef7eb2e8f9f7 30 different data bus modes: 1-bit (default) and 4-bit
<> 144:ef7eb2e8f9f7 31 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
<> 144:ef7eb2e8f9f7 32 Rev1.1)
<> 144:ef7eb2e8f9f7 33 (+) Data transfer up to 48 MHz for the 8 bit mode
<> 144:ef7eb2e8f9f7 34 (+) Data and command output enable signals to control external bidirectional drivers.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 38 ==============================================================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 This driver is a considered as a driver of service for external devices drivers
<> 144:ef7eb2e8f9f7 41 that interfaces with the SDIO peripheral.
<> 144:ef7eb2e8f9f7 42 According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
<> 144:ef7eb2e8f9f7 43 is used in the device's driver to perform SDIO operations and functionalities.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 This driver is almost transparent for the final user, it is only used to implement other
<> 144:ef7eb2e8f9f7 46 functionalities of the external device.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
<> 144:ef7eb2e8f9f7 50 (PLL48CLK). Before start working with SDIO peripheral make sure that the
<> 144:ef7eb2e8f9f7 51 PLL is well configured.
<> 144:ef7eb2e8f9f7 52 The SDIO peripheral uses two clock signals:
<> 144:ef7eb2e8f9f7 53 (++) SDIO adapter clock (SDIOCLK = 48 MHz)
<> 144:ef7eb2e8f9f7 54 (++) APB2 bus clock (PCLK2)
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
<> 144:ef7eb2e8f9f7 57 Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
<> 144:ef7eb2e8f9f7 60 peripheral.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
<> 144:ef7eb2e8f9f7 63 function and disable it using the function SDIO_PowerState_OFF(SDIOx).
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
<> 144:ef7eb2e8f9f7 68 and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 (+) When using the DMA mode
<> 144:ef7eb2e8f9f7 71 (++) Configure the DMA in the MSP layer of the external device
<> 144:ef7eb2e8f9f7 72 (++) Active the needed channel Request
<> 144:ef7eb2e8f9f7 73 (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
<> 144:ef7eb2e8f9f7 74 __SDIO_DMA_DISABLE().
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 (+) To control the CPSM (Command Path State Machine) and send
<> 144:ef7eb2e8f9f7 77 commands to the card use the SDIO_SendCommand(SDIOx),
<> 144:ef7eb2e8f9f7 78 SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
<> 144:ef7eb2e8f9f7 79 to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
<> 144:ef7eb2e8f9f7 80 to the selected command to be sent.
<> 144:ef7eb2e8f9f7 81 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 82 (++) Command Argument
<> 144:ef7eb2e8f9f7 83 (++) Command Index
<> 144:ef7eb2e8f9f7 84 (++) Command Response type
<> 144:ef7eb2e8f9f7 85 (++) Command Wait
<> 144:ef7eb2e8f9f7 86 (++) CPSM Status (Enable or Disable).
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 -@@- To check if the command is well received, read the SDIO_CMDRESP
<> 144:ef7eb2e8f9f7 89 register using the SDIO_GetCommandResponse().
<> 144:ef7eb2e8f9f7 90 The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
<> 144:ef7eb2e8f9f7 91 SDIO_GetResponse() function.
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (+) To control the DPSM (Data Path State Machine) and send/receive
<> 144:ef7eb2e8f9f7 94 data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
<> 144:ef7eb2e8f9f7 95 SDIO_ReadFIFO(), DIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 *** Read Operations ***
<> 144:ef7eb2e8f9f7 98 =======================
<> 144:ef7eb2e8f9f7 99 [..]
<> 144:ef7eb2e8f9f7 100 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 101 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 102 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 103 (++) Data Timeout
<> 144:ef7eb2e8f9f7 104 (++) Data Length
<> 144:ef7eb2e8f9f7 105 (++) Data Block size
<> 144:ef7eb2e8f9f7 106 (++) Data Transfer direction: should be from card (To SDIO)
<> 144:ef7eb2e8f9f7 107 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 108 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (#) Configure the SDIO resources to receive the data from the card
<> 144:ef7eb2e8f9f7 111 according to selected transfer mode (Refer to Step 8, 9 and 10).
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 (#) Send the selected Read command (refer to step 11).
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 (#) Use the SDIO flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 *** Write Operations ***
<> 144:ef7eb2e8f9f7 118 ========================
<> 144:ef7eb2e8f9f7 119 [..]
<> 144:ef7eb2e8f9f7 120 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 121 SDIO_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 122 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 123 (++) Data Timeout
<> 144:ef7eb2e8f9f7 124 (++) Data Length
<> 144:ef7eb2e8f9f7 125 (++) Data Block size
<> 144:ef7eb2e8f9f7 126 (++) Data Transfer direction: should be to card (To CARD)
<> 144:ef7eb2e8f9f7 127 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 128 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 (#) Configure the SDIO resources to send the data to the card according to
<> 144:ef7eb2e8f9f7 131 selected transfer mode.
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 (#) Send the selected Write command.
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 (#) Use the SDIO flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 @endverbatim
<> 144:ef7eb2e8f9f7 138 ******************************************************************************
<> 144:ef7eb2e8f9f7 139 * @attention
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 142 *
<> 144:ef7eb2e8f9f7 143 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 144 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 145 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 146 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 147 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 148 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 149 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 151 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 152 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 153 *
<> 144:ef7eb2e8f9f7 154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 164 *
<> 144:ef7eb2e8f9f7 165 ******************************************************************************
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup SDMMC_LL SDMMC Low Layer
<> 144:ef7eb2e8f9f7 176 * @brief Low layer module for SD and MMC driver
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 184 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 186 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 187 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 194 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 195 *
<> 144:ef7eb2e8f9f7 196 @verbatim
<> 144:ef7eb2e8f9f7 197 ===============================================================================
<> 144:ef7eb2e8f9f7 198 ##### Initialization/de-initialization functions #####
<> 144:ef7eb2e8f9f7 199 ===============================================================================
<> 144:ef7eb2e8f9f7 200 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 @endverbatim
<> 144:ef7eb2e8f9f7 203 * @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Initializes the SDIO according to the specified
<> 144:ef7eb2e8f9f7 208 * parameters in the SDIO_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 209 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 210 * @param Init: SDIO initialization structure
<> 144:ef7eb2e8f9f7 211 * @retval HAL status
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Check the parameters */
<> 144:ef7eb2e8f9f7 218 assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
<> 144:ef7eb2e8f9f7 222 assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
<> 144:ef7eb2e8f9f7 223 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
<> 144:ef7eb2e8f9f7 224 assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Set SDIO configuration parameters */
<> 144:ef7eb2e8f9f7 227 tmpreg |= (Init.ClockEdge |\
<> 144:ef7eb2e8f9f7 228 Init.ClockBypass |\
<> 144:ef7eb2e8f9f7 229 Init.ClockPowerSave |\
<> 144:ef7eb2e8f9f7 230 Init.BusWide |\
<> 144:ef7eb2e8f9f7 231 Init.HardwareFlowControl |\
<> 144:ef7eb2e8f9f7 232 Init.ClockDiv
<> 144:ef7eb2e8f9f7 233 );
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Write to SDIO CLKCR */
<> 144:ef7eb2e8f9f7 236 MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 return HAL_OK;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
<> 144:ef7eb2e8f9f7 246 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 247 *
<> 144:ef7eb2e8f9f7 248 @verbatim
<> 144:ef7eb2e8f9f7 249 ===============================================================================
<> 144:ef7eb2e8f9f7 250 ##### I/O operation functions #####
<> 144:ef7eb2e8f9f7 251 ===============================================================================
<> 144:ef7eb2e8f9f7 252 [..]
<> 144:ef7eb2e8f9f7 253 This subsection provides a set of functions allowing to manage the SDIO data
<> 144:ef7eb2e8f9f7 254 transfers.
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 @endverbatim
<> 144:ef7eb2e8f9f7 257 * @{
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 262 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 263 * @retval HAL status
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* Read data from Rx FIFO */
<> 144:ef7eb2e8f9f7 268 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 273 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 274 * @param pWriteData: pointer to data to write
<> 144:ef7eb2e8f9f7 275 * @retval HAL status
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 /* Write data to FIFO */
<> 144:ef7eb2e8f9f7 280 SDIOx->FIFO = *pWriteData;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 return HAL_OK;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 290 * @brief management functions
<> 144:ef7eb2e8f9f7 291 *
<> 144:ef7eb2e8f9f7 292 @verbatim
<> 144:ef7eb2e8f9f7 293 ===============================================================================
<> 144:ef7eb2e8f9f7 294 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 295 ===============================================================================
<> 144:ef7eb2e8f9f7 296 [..]
<> 144:ef7eb2e8f9f7 297 This subsection provides a set of functions allowing to control the SDIO data
<> 144:ef7eb2e8f9f7 298 transfers.
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 @endverbatim
<> 144:ef7eb2e8f9f7 301 * @{
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @brief Set SDIO Power state to ON.
<> 144:ef7eb2e8f9f7 306 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 307 * @retval HAL status
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 /* Set power state to ON */
<> 144:ef7eb2e8f9f7 312 SDIOx->POWER = SDIO_POWER_PWRCTRL;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 return HAL_OK;
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Set SDIO Power state to OFF.
<> 144:ef7eb2e8f9f7 319 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 320 * @retval HAL status
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Set power state to OFF */
<> 144:ef7eb2e8f9f7 325 SDIOx->POWER = (uint32_t)0x00000000;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 return HAL_OK;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @brief Get SDIO Power state.
<> 144:ef7eb2e8f9f7 332 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 333 * @retval Power status of the controller. The returned value can be one of the
<> 144:ef7eb2e8f9f7 334 * following values:
<> 144:ef7eb2e8f9f7 335 * - 0x00: Power OFF
<> 144:ef7eb2e8f9f7 336 * - 0x02: Power UP
<> 144:ef7eb2e8f9f7 337 * - 0x03: Power ON
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 340 {
<> 144:ef7eb2e8f9f7 341 return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Configure the SDIO command path according to the specified parameters in
<> 144:ef7eb2e8f9f7 346 * SDIO_CmdInitTypeDef structure and send the command
<> 144:ef7eb2e8f9f7 347 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 348 * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 349 * the configuration information for the SDIO command
<> 144:ef7eb2e8f9f7 350 * @retval HAL status
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Check the parameters */
<> 144:ef7eb2e8f9f7 357 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
<> 144:ef7eb2e8f9f7 358 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
<> 144:ef7eb2e8f9f7 359 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
<> 144:ef7eb2e8f9f7 360 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Set the SDIO Argument value */
<> 144:ef7eb2e8f9f7 363 SDIOx->ARG = SDIO_CmdInitStruct->Argument;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Set SDIO command parameters */
<> 144:ef7eb2e8f9f7 366 tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
<> 144:ef7eb2e8f9f7 367 SDIO_CmdInitStruct->Response |\
<> 144:ef7eb2e8f9f7 368 SDIO_CmdInitStruct->WaitForInterrupt |\
<> 144:ef7eb2e8f9f7 369 SDIO_CmdInitStruct->CPSM);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Write to SDIO CMD register */
<> 144:ef7eb2e8f9f7 372 MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 return HAL_OK;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /**
<> 144:ef7eb2e8f9f7 378 * @brief Return the command index of last command for which response received
<> 144:ef7eb2e8f9f7 379 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 380 * @retval Command index of the last command response received
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 return (uint8_t)(SDIOx->RESPCMD);
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Return the response received from the card for the last command
<> 144:ef7eb2e8f9f7 390 * @param SDIO_RESP: Specifies the SDIO response register.
<> 144:ef7eb2e8f9f7 391 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 392 * @arg SDIO_RESP1: Response Register 1
<> 144:ef7eb2e8f9f7 393 * @arg SDIO_RESP2: Response Register 2
<> 144:ef7eb2e8f9f7 394 * @arg SDIO_RESP3: Response Register 3
<> 144:ef7eb2e8f9f7 395 * @arg SDIO_RESP4: Response Register 4
<> 144:ef7eb2e8f9f7 396 * @retval The Corresponding response register value
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Check the parameters */
<> 144:ef7eb2e8f9f7 403 assert_param(IS_SDIO_RESP(SDIO_RESP));
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /* Get the response */
<> 144:ef7eb2e8f9f7 406 tmp = SDIO_RESP_ADDR + SDIO_RESP;
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 return (*(__IO uint32_t *) tmp);
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Configure the SDIO data path according to the specified
<> 144:ef7eb2e8f9f7 413 * parameters in the SDIO_DataInitTypeDef.
<> 144:ef7eb2e8f9f7 414 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 415 * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
<> 144:ef7eb2e8f9f7 416 * that contains the configuration information for the SDIO command.
<> 144:ef7eb2e8f9f7 417 * @retval HAL status
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Check the parameters */
<> 144:ef7eb2e8f9f7 424 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
<> 144:ef7eb2e8f9f7 425 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
<> 144:ef7eb2e8f9f7 426 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
<> 144:ef7eb2e8f9f7 427 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
<> 144:ef7eb2e8f9f7 428 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Set the SDIO Data Timeout value */
<> 144:ef7eb2e8f9f7 431 SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /* Set the SDIO DataLength value */
<> 144:ef7eb2e8f9f7 434 SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Set the SDIO data configuration parameters */
<> 144:ef7eb2e8f9f7 437 tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
<> 144:ef7eb2e8f9f7 438 SDIO_DataInitStruct->TransferDir |\
<> 144:ef7eb2e8f9f7 439 SDIO_DataInitStruct->TransferMode |\
<> 144:ef7eb2e8f9f7 440 SDIO_DataInitStruct->DPSM);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Write to SDIO DCTRL */
<> 144:ef7eb2e8f9f7 443 MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 return HAL_OK;
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @brief Returns number of remaining data bytes to be transferred.
<> 144:ef7eb2e8f9f7 451 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 452 * @retval Number of remaining data bytes to be transferred
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 return (SDIOx->DCOUNT);
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @brief Get the FIFO data
<> 144:ef7eb2e8f9f7 461 * @param SDIOx: Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 462 * @retval Data received
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 return (SDIOx->FIFO);
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @brief Sets one of the two options of inserting read wait interval.
<> 144:ef7eb2e8f9f7 472 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
<> 144:ef7eb2e8f9f7 473 * This parameter can be:
<> 144:ef7eb2e8f9f7 474 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
<> 144:ef7eb2e8f9f7 475 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
<> 144:ef7eb2e8f9f7 476 * @retval None
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 /* Check the parameters */
<> 144:ef7eb2e8f9f7 481 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 return HAL_OK;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @}
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @}
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @}
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/