Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_ll_fsmc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_ll_fsmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.2
<> 144:ef7eb2e8f9f7 6 * @date 11-December-2015
<> 144:ef7eb2e8f9f7 7 * @brief Header file of FSMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_LL_FSMC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_LL_FSMC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FSMC_LL
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief FSMC NORSRAM Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
<> 144:ef7eb2e8f9f7 71 multiplexed on the data bus or not.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
<> 144:ef7eb2e8f9f7 75 the corresponding memory device.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref FSMC_Memory_Type */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
<> 144:ef7eb2e8f9f7 82 valid only with synchronous burst Flash memories.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
<> 144:ef7eb2e8f9f7 86 the Flash memory in burst mode.
<> 144:ef7eb2e8f9f7 87 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
<> 144:ef7eb2e8f9f7 90 memory, valid only when accessing Flash memories in burst mode.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref FSMC_Wrap_Mode */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
<> 144:ef7eb2e8f9f7 94 clock cycle before the wait state or during the wait state,
<> 144:ef7eb2e8f9f7 95 valid only when accessing memories in burst mode.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref FSMC_Wait_Timing */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref FSMC_Write_Operation */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
<> 144:ef7eb2e8f9f7 102 signal, valid for Flash memory access in burst mode.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref FSMC_Wait_Signal */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref FSMC_Extended_Mode */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
<> 144:ef7eb2e8f9f7 109 valid only with asynchronous Flash memories.
<> 144:ef7eb2e8f9f7 110 This parameter can be a value of @ref FSMC_AsynchronousWait */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
<> 144:ef7eb2e8f9f7 113 This parameter can be a value of @ref FSMC_Write_Burst */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 }FSMC_NORSRAM_InitTypeDef;
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @brief FSMC NORSRAM Timing parameters structure definition
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 typedef struct
<> 144:ef7eb2e8f9f7 121 {
<> 144:ef7eb2e8f9f7 122 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 123 the duration of the address setup time.
<> 144:ef7eb2e8f9f7 124 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 125 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 128 the duration of the address hold time.
<> 144:ef7eb2e8f9f7 129 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 130 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 133 the duration of the data setup time.
<> 144:ef7eb2e8f9f7 134 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 135 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
<> 144:ef7eb2e8f9f7 136 NOR Flash memories. */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 139 the duration of the bus turnaround.
<> 144:ef7eb2e8f9f7 140 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 141 @note This parameter is only used for multiplexed NOR Flash memories. */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
<> 144:ef7eb2e8f9f7 144 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
<> 144:ef7eb2e8f9f7 145 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
<> 144:ef7eb2e8f9f7 146 accesses. */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
<> 144:ef7eb2e8f9f7 149 to the memory before getting the first data.
<> 144:ef7eb2e8f9f7 150 The parameter value depends on the memory type as shown below:
<> 144:ef7eb2e8f9f7 151 - It must be set to 0 in case of a CRAM
<> 144:ef7eb2e8f9f7 152 - It is don't care in asynchronous NOR, SRAM or ROM accesses
<> 144:ef7eb2e8f9f7 153 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
<> 144:ef7eb2e8f9f7 154 with synchronous burst mode enable */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
<> 144:ef7eb2e8f9f7 157 This parameter can be a value of @ref FSMC_Access_Mode */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 }FSMC_NORSRAM_TimingTypeDef;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @brief FSMC NAND Configuration Structure definition
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 typedef struct
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
<> 144:ef7eb2e8f9f7 167 This parameter can be a value of @ref FSMC_NAND_Bank */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
<> 144:ef7eb2e8f9f7 170 This parameter can be any value of @ref FSMC_Wait_feature */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 173 This parameter can be any value of @ref FSMC_NAND_Data_Width */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
<> 144:ef7eb2e8f9f7 176 This parameter can be any value of @ref FSMC_ECC */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
<> 144:ef7eb2e8f9f7 179 This parameter can be any value of @ref FSMC_ECC_Page_Size */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 182 delay between CLE low and RE low.
<> 144:ef7eb2e8f9f7 183 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 186 delay between ALE low and RE low.
<> 144:ef7eb2e8f9f7 187 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 }FSMC_NAND_InitTypeDef;
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief FSMC NAND/PCCARD Timing parameters structure definition
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 typedef struct
<> 144:ef7eb2e8f9f7 195 {
<> 144:ef7eb2e8f9f7 196 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
<> 144:ef7eb2e8f9f7 197 the command assertion for NAND-Flash read or write access
<> 144:ef7eb2e8f9f7 198 to common/Attribute or I/O memory space (depending on
<> 144:ef7eb2e8f9f7 199 the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 200 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
<> 144:ef7eb2e8f9f7 203 command for NAND-Flash read or write access to
<> 144:ef7eb2e8f9f7 204 common/Attribute or I/O memory space (depending on the
<> 144:ef7eb2e8f9f7 205 memory space timing to be configured).
<> 144:ef7eb2e8f9f7 206 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
<> 144:ef7eb2e8f9f7 209 (and data for write access) after the command de-assertion
<> 144:ef7eb2e8f9f7 210 for NAND-Flash read or write access to common/Attribute
<> 144:ef7eb2e8f9f7 211 or I/O memory space (depending on the memory space timing
<> 144:ef7eb2e8f9f7 212 to be configured).
<> 144:ef7eb2e8f9f7 213 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
<> 144:ef7eb2e8f9f7 216 data bus is kept in HiZ after the start of a NAND-Flash
<> 144:ef7eb2e8f9f7 217 write access to common/Attribute or I/O memory space (depending
<> 144:ef7eb2e8f9f7 218 on the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 219 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 }FSMC_NAND_PCC_TimingTypeDef;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief FSMC NAND Configuration Structure definition
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 typedef struct
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
<> 144:ef7eb2e8f9f7 229 This parameter can be any value of @ref FSMC_Wait_feature */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 232 delay between CLE low and RE low.
<> 144:ef7eb2e8f9f7 233 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 236 delay between ALE low and RE low.
<> 144:ef7eb2e8f9f7 237 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 }FSMC_PCCARD_InitTypeDef;
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @}
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 245 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
<> 144:ef7eb2e8f9f7 253 * @{
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 256 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 257 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 258 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 267 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 268 /**
<> 144:ef7eb2e8f9f7 269 * @}
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /** @defgroup FSMC_Memory_Type FSMC Memory Type
<> 144:ef7eb2e8f9f7 273 * @{
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 276 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 277 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 286 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 287 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @}
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 296 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 305 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @}
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 314 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 323 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 332 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @}
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /** @defgroup FSMC_Write_Operation FSMC Write Operation
<> 144:ef7eb2e8f9f7 338 * @{
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 341 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
<> 144:ef7eb2e8f9f7 342 /**
<> 144:ef7eb2e8f9f7 343 * @}
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
<> 144:ef7eb2e8f9f7 347 * @{
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 350 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 359 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
<> 144:ef7eb2e8f9f7 365 * @{
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 368 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @}
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @defgroup FSMC_Write_Burst FSMC Write Burst
<> 144:ef7eb2e8f9f7 374 * @{
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 377 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @}
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @defgroup FSMC_Continuous_Clock FSMC Continuous Clock
<> 144:ef7eb2e8f9f7 383 * @{
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 386 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @defgroup FSMC_Access_Mode FSMC Access Mode
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 395 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000)
<> 144:ef7eb2e8f9f7 396 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000)
<> 144:ef7eb2e8f9f7 397 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000)
<> 144:ef7eb2e8f9f7 398 /**
<> 144:ef7eb2e8f9f7 399 * @}
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 /**
<> 144:ef7eb2e8f9f7 402 * @}
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 412 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @}
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /** @defgroup FSMC_Wait_feature FSMC Wait feature
<> 144:ef7eb2e8f9f7 418 * @{
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 421 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @}
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
<> 144:ef7eb2e8f9f7 427 * @{
<> 144:ef7eb2e8f9f7 428 */
<> 144:ef7eb2e8f9f7 429 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 430 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
<> 144:ef7eb2e8f9f7 436 * @{
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 439 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** @defgroup FSMC_ECC FSMC ECC
<> 144:ef7eb2e8f9f7 445 * @{
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 448 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @}
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
<> 144:ef7eb2e8f9f7 454 * @{
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 457 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
<> 144:ef7eb2e8f9f7 458 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
<> 144:ef7eb2e8f9f7 459 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
<> 144:ef7eb2e8f9f7 460 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
<> 144:ef7eb2e8f9f7 461 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 473 #define FSMC_IT_LEVEL ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 474 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 475 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
<> 144:ef7eb2e8f9f7 481 * @{
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 484 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 485 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 486 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @}
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
<> 144:ef7eb2e8f9f7 492 * @{
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
<> 144:ef7eb2e8f9f7 495 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
<> 144:ef7eb2e8f9f7 496 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
<> 144:ef7eb2e8f9f7 497 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
<> 144:ef7eb2e8f9f7 500 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
<> 144:ef7eb2e8f9f7 501 #define FSMC_NAND_DEVICE FSMC_Bank2_3
<> 144:ef7eb2e8f9f7 502 #define FSMC_PCCARD_DEVICE FSMC_Bank4
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 513 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
<> 144:ef7eb2e8f9f7 514 * @{
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
<> 144:ef7eb2e8f9f7 518 * @brief macros to handle NOR device enable/disable and read/write operations
<> 144:ef7eb2e8f9f7 519 * @{
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 /**
<> 144:ef7eb2e8f9f7 522 * @brief Enable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 523 * @param __INSTANCE__: FSMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 524 * @param __BANK__: FSMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 525 * @retval none
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @brief Disable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 531 * @param __INSTANCE__: FSMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 532 * @param __BANK__: FSMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 533 * @retval none
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
<> 144:ef7eb2e8f9f7 541 * @brief macros to handle NAND device enable/disable
<> 144:ef7eb2e8f9f7 542 * @{
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief Enable the NAND device access.
<> 144:ef7eb2e8f9f7 546 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 547 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 548 * @retval none
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
<> 144:ef7eb2e8f9f7 551 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @brief Disable the NAND device access.
<> 144:ef7eb2e8f9f7 555 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 556 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 557 * @retval none
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
<> 144:ef7eb2e8f9f7 560 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @}
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
<> 144:ef7eb2e8f9f7 566 * @brief macros to handle SRAM read/write operations
<> 144:ef7eb2e8f9f7 567 * @{
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 /**
<> 144:ef7eb2e8f9f7 570 * @brief Enable the PCCARD device access.
<> 144:ef7eb2e8f9f7 571 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 572 * @retval none
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 /**
<> 144:ef7eb2e8f9f7 577 * @brief Disable the PCCARD device access.
<> 144:ef7eb2e8f9f7 578 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 579 * @retval none
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
<> 144:ef7eb2e8f9f7 587 * @brief macros to handle FSMC flags and interrupts
<> 144:ef7eb2e8f9f7 588 * @{
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590 /**
<> 144:ef7eb2e8f9f7 591 * @brief Enable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 592 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 593 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 594 * @param __INTERRUPT__: FSMC_NAND interrupt
<> 144:ef7eb2e8f9f7 595 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 596 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 597 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 598 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 599 * @retval None
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
<> 144:ef7eb2e8f9f7 602 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /**
<> 144:ef7eb2e8f9f7 605 * @brief Disable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 606 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 607 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 608 * @param __INTERRUPT__: FSMC_NAND interrupt
<> 144:ef7eb2e8f9f7 609 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 610 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 611 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 612 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 613 * @retval None
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
<> 144:ef7eb2e8f9f7 616 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Get flag status of the NAND device.
<> 144:ef7eb2e8f9f7 620 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 621 * @param __BANK__ : FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 622 * @param __FLAG__ : FSMC_NAND flag
<> 144:ef7eb2e8f9f7 623 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 624 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 625 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 626 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 627 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 628 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
<> 144:ef7eb2e8f9f7 631 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
<> 144:ef7eb2e8f9f7 632 /**
<> 144:ef7eb2e8f9f7 633 * @brief Clear flag status of the NAND device.
<> 144:ef7eb2e8f9f7 634 * @param __INSTANCE__: FSMC_NAND Instance
<> 144:ef7eb2e8f9f7 635 * @param __BANK__: FSMC_NAND Bank
<> 144:ef7eb2e8f9f7 636 * @param __FLAG__: FSMC_NAND flag
<> 144:ef7eb2e8f9f7 637 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 638 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 639 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 640 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 641 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 642 * @retval None
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
<> 144:ef7eb2e8f9f7 645 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
<> 144:ef7eb2e8f9f7 646 /**
<> 144:ef7eb2e8f9f7 647 * @brief Enable the PCCARD device interrupt.
<> 144:ef7eb2e8f9f7 648 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 649 * @param __INTERRUPT__: FSMC_PCCARD interrupt
<> 144:ef7eb2e8f9f7 650 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 651 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 652 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 653 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 654 * @retval None
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /**
<> 144:ef7eb2e8f9f7 659 * @brief Disable the PCCARD device interrupt.
<> 144:ef7eb2e8f9f7 660 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 661 * @param __INTERRUPT__: FSMC_PCCARD interrupt
<> 144:ef7eb2e8f9f7 662 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 663 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 664 * @arg FSMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 665 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 666 * @retval None
<> 144:ef7eb2e8f9f7 667 */
<> 144:ef7eb2e8f9f7 668 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Get flag status of the PCCARD device.
<> 144:ef7eb2e8f9f7 672 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 673 * @param __FLAG__: FSMC_PCCARD flag
<> 144:ef7eb2e8f9f7 674 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 675 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 676 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 677 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 678 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 679 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /**
<> 144:ef7eb2e8f9f7 684 * @brief Clear flag status of the PCCARD device.
<> 144:ef7eb2e8f9f7 685 * @param __INSTANCE__: FSMC_PCCARD Instance
<> 144:ef7eb2e8f9f7 686 * @param __FLAG__: FSMC_PCCARD flag
<> 144:ef7eb2e8f9f7 687 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 688 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 689 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 690 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 691 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 692 * @retval None
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
<> 144:ef7eb2e8f9f7 700 * @{
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
<> 144:ef7eb2e8f9f7 703 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
<> 144:ef7eb2e8f9f7 704 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
<> 144:ef7eb2e8f9f7 705 ((__BANK__) == FSMC_NORSRAM_BANK4))
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
<> 144:ef7eb2e8f9f7 708 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
<> 144:ef7eb2e8f9f7 711 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
<> 144:ef7eb2e8f9f7 712 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 715 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
<> 144:ef7eb2e8f9f7 716 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
<> 144:ef7eb2e8f9f7 719 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
<> 144:ef7eb2e8f9f7 720 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
<> 144:ef7eb2e8f9f7 721 ((__MODE__) == FSMC_ACCESS_MODE_D))
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
<> 144:ef7eb2e8f9f7 724 ((BANK) == FSMC_NAND_BANK3))
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
<> 144:ef7eb2e8f9f7 727 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
<> 144:ef7eb2e8f9f7 728
<> 144:ef7eb2e8f9f7 729 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 730 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
<> 144:ef7eb2e8f9f7 733 ((STATE) == FSMC_NAND_ECC_ENABLE))
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
<> 144:ef7eb2e8f9f7 736 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
<> 144:ef7eb2e8f9f7 737 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
<> 144:ef7eb2e8f9f7 738 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
<> 144:ef7eb2e8f9f7 739 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
<> 144:ef7eb2e8f9f7 740 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 763 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 766 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 769 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
<> 144:ef7eb2e8f9f7 772 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 775 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
<> 144:ef7eb2e8f9f7 778 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 781 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 784 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
<> 144:ef7eb2e8f9f7 789 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
<> 144:ef7eb2e8f9f7 800 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /**
<> 144:ef7eb2e8f9f7 805 * @}
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 /**
<> 144:ef7eb2e8f9f7 808 * @}
<> 144:ef7eb2e8f9f7 809 */
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 812 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
<> 144:ef7eb2e8f9f7 813 * @{
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
<> 144:ef7eb2e8f9f7 817 * @{
<> 144:ef7eb2e8f9f7 818 */
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 821 * @{
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 824 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 825 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
<> 144:ef7eb2e8f9f7 826 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @}
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
<> 144:ef7eb2e8f9f7 832 * @{
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 835 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 836 /**
<> 144:ef7eb2e8f9f7 837 * @}
<> 144:ef7eb2e8f9f7 838 */
<> 144:ef7eb2e8f9f7 839 /**
<> 144:ef7eb2e8f9f7 840 * @}
<> 144:ef7eb2e8f9f7 841 */
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /** @defgroup FSMC_LL_NAND NAND
<> 144:ef7eb2e8f9f7 844 * @{
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 847 * @{
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 850 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 851 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 852 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @}
<> 144:ef7eb2e8f9f7 855 */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
<> 144:ef7eb2e8f9f7 858 * @{
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 861 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 862 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 863 /**
<> 144:ef7eb2e8f9f7 864 * @}
<> 144:ef7eb2e8f9f7 865 */
<> 144:ef7eb2e8f9f7 866 /**
<> 144:ef7eb2e8f9f7 867 * @}
<> 144:ef7eb2e8f9f7 868 */
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /** @defgroup FSMC_LL_PCCARD PCCARD
<> 144:ef7eb2e8f9f7 871 * @{
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 874 * @{
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 877 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 878 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 879 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
<> 144:ef7eb2e8f9f7 880 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
<> 144:ef7eb2e8f9f7 881 /**
<> 144:ef7eb2e8f9f7 882 * @}
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884 /**
<> 144:ef7eb2e8f9f7 885 * @}
<> 144:ef7eb2e8f9f7 886 */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /**
<> 144:ef7eb2e8f9f7 889 * @}
<> 144:ef7eb2e8f9f7 890 */
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @}
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903 #endif
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #endif /* __STM32F2xx_LL_FSMC_H */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/