Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_tim.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_tim.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of TIM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_TIM_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_TIM_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup TIM
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup TIM_Exported_Types TIM Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief TIM Time base Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<> 144:ef7eb2e8f9f7 68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t CounterMode; /*!< Specifies the counter mode.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref TIM_Counter_Mode */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
<> 144:ef7eb2e8f9f7 74 Auto-Reload Register at the next update event.
<> 144:ef7eb2e8f9f7 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 uint32_t ClockDivision; /*!< Specifies the clock division.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref TIM_ClockDivision */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<> 144:ef7eb2e8f9f7 81 reaches zero, an update event is generated and counting restarts
<> 144:ef7eb2e8f9f7 82 from the RCR value (N).
<> 144:ef7eb2e8f9f7 83 This means in PWM mode that (N+1) corresponds to:
<> 144:ef7eb2e8f9f7 84 - the number of PWM periods in edge-aligned mode
<> 144:ef7eb2e8f9f7 85 - the number of half PWM period in center-aligned mode
<> 144:ef7eb2e8f9f7 86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<> 144:ef7eb2e8f9f7 87 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 88 } TIM_Base_InitTypeDef;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief TIM Output Compare Configuration Structure definition
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 typedef struct
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 144:ef7eb2e8f9f7 97 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 100 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<> 144:ef7eb2e8f9f7 107 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<> 144:ef7eb2e8f9f7 110 This parameter can be a value of @ref TIM_Output_Fast_State
<> 144:ef7eb2e8f9f7 111 @note This parameter is valid only in PWM1 and PWM2 mode. */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 115 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<> 144:ef7eb2e8f9f7 116 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 119 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<> 144:ef7eb2e8f9f7 120 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 121 } TIM_OC_InitTypeDef;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @brief TIM One Pulse Mode Configuration Structure definition
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 typedef struct
<> 144:ef7eb2e8f9f7 127 {
<> 144:ef7eb2e8f9f7 128 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 144:ef7eb2e8f9f7 129 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 132 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 144:ef7eb2e8f9f7 135 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<> 144:ef7eb2e8f9f7 138 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<> 144:ef7eb2e8f9f7 139 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 142 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<> 144:ef7eb2e8f9f7 143 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 144:ef7eb2e8f9f7 146 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<> 144:ef7eb2e8f9f7 147 @note This parameter is valid only for TIM1 and TIM8. */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 150 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 uint32_t ICSelection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 153 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 156 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 157 } TIM_OnePulse_InitTypeDef;
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @brief TIM Input Capture Configuration Structure definition
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 typedef struct
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 uint32_t ICSelection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 177 } TIM_IC_InitTypeDef;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief TIM Encoder Configuration Structure definition
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 typedef struct
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 186 This parameter can be a value of @ref TIM_Encoder_Mode */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 189 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 uint32_t IC1Selection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 192 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 uint32_t IC1Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 201 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 uint32_t IC2Selection; /*!< Specifies the input.
<> 144:ef7eb2e8f9f7 204 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 207 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 uint32_t IC2Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 210 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 211 } TIM_Encoder_InitTypeDef;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /**
<> 144:ef7eb2e8f9f7 214 * @brief Clock Configuration Handle Structure definition
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 typedef struct
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 uint32_t ClockSource; /*!< TIM clock sources.
<> 144:ef7eb2e8f9f7 219 This parameter can be a value of @ref TIM_Clock_Source */
<> 144:ef7eb2e8f9f7 220 uint32_t ClockPolarity; /*!< TIM clock polarity.
<> 144:ef7eb2e8f9f7 221 This parameter can be a value of @ref TIM_Clock_Polarity */
<> 144:ef7eb2e8f9f7 222 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
<> 144:ef7eb2e8f9f7 223 This parameter can be a value of @ref TIM_Clock_Prescaler */
<> 144:ef7eb2e8f9f7 224 uint32_t ClockFilter; /*!< TIM clock filter.
<> 144:ef7eb2e8f9f7 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 226 }TIM_ClockConfigTypeDef;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief Clear Input Configuration Handle Structure definition
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 typedef struct
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 uint32_t ClearInputState; /*!< TIM clear Input state.
<> 144:ef7eb2e8f9f7 234 This parameter can be ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 235 uint32_t ClearInputSource; /*!< TIM clear Input sources.
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref TIM_ClearInput_Source */
<> 144:ef7eb2e8f9f7 237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
<> 144:ef7eb2e8f9f7 238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
<> 144:ef7eb2e8f9f7 239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
<> 144:ef7eb2e8f9f7 240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<> 144:ef7eb2e8f9f7 241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
<> 144:ef7eb2e8f9f7 242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 243 }TIM_ClearInputConfigTypeDef;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief TIM Slave configuration Structure definition
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248 typedef struct {
<> 144:ef7eb2e8f9f7 249 uint32_t SlaveMode; /*!< Slave mode selection
<> 144:ef7eb2e8f9f7 250 This parameter can be a value of @ref TIM_Slave_Mode */
<> 144:ef7eb2e8f9f7 251 uint32_t InputTrigger; /*!< Input Trigger source
<> 144:ef7eb2e8f9f7 252 This parameter can be a value of @ref TIM_Trigger_Selection */
<> 144:ef7eb2e8f9f7 253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
<> 144:ef7eb2e8f9f7 254 This parameter can be a value of @ref TIM_Trigger_Polarity */
<> 144:ef7eb2e8f9f7 255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<> 144:ef7eb2e8f9f7 256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
<> 144:ef7eb2e8f9f7 257 uint32_t TriggerFilter; /*!< Input trigger filter
<> 144:ef7eb2e8f9f7 258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 }TIM_SlaveConfigTypeDef;
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 typedef enum
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 268 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 269 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
<> 144:ef7eb2e8f9f7 270 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 271 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 272 }HAL_TIM_StateTypeDef;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @brief HAL Active channel structures definition
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 typedef enum
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
<> 144:ef7eb2e8f9f7 280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
<> 144:ef7eb2e8f9f7 281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
<> 144:ef7eb2e8f9f7 282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
<> 144:ef7eb2e8f9f7 283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
<> 144:ef7eb2e8f9f7 284 }HAL_TIM_ActiveChannel;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @brief TIM Time Base Handle Structure definition
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 typedef struct
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 TIM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
<> 144:ef7eb2e8f9f7 293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
<> 144:ef7eb2e8f9f7 294 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
<> 144:ef7eb2e8f9f7 295 This array is accessed by a @ref DMA_Handle_index */
<> 144:ef7eb2e8f9f7 296 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
<> 144:ef7eb2e8f9f7 298 }TIM_HandleTypeDef;
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 304 /** @defgroup TIM_Exported_Constants TIM Exported Constants
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 312 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 313 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<> 144:ef7eb2e8f9f7 319 * @{
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
<> 144:ef7eb2e8f9f7 322 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<> 144:ef7eb2e8f9f7 328 * @{
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 331 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
<> 144:ef7eb2e8f9f7 332 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
<> 144:ef7eb2e8f9f7 333 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
<> 144:ef7eb2e8f9f7 334 /**
<> 144:ef7eb2e8f9f7 335 * @}
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /** @defgroup TIM_Counter_Mode TIM Counter Mode
<> 144:ef7eb2e8f9f7 339 * @{
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<> 144:ef7eb2e8f9f7 343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<> 144:ef7eb2e8f9f7 344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<> 144:ef7eb2e8f9f7 345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @}
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /** @defgroup TIM_ClockDivision TIM Clock Division
<> 144:ef7eb2e8f9f7 351 * @{
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<> 144:ef7eb2e8f9f7 355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @}
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
<> 144:ef7eb2e8f9f7 361 * @{
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 #define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 364 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 365 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 366 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 367 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 368 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<> 144:ef7eb2e8f9f7 369 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 370 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @}
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
<> 144:ef7eb2e8f9f7 377 * @{
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 380 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @}
<> 144:ef7eb2e8f9f7 383 */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<> 144:ef7eb2e8f9f7 386 * @{
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 389 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @}
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 398 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @}
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<> 144:ef7eb2e8f9f7 404 * @{
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
<> 144:ef7eb2e8f9f7 407 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 408 /**
<> 144:ef7eb2e8f9f7 409 * @}
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
<> 144:ef7eb2e8f9f7 413 * @{
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
<> 144:ef7eb2e8f9f7 416 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @}
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /** @defgroup TIM_Channel TIM Channel
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424 #define TIM_CHANNEL_1 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 425 #define TIM_CHANNEL_2 ((uint32_t)0x0004U)
<> 144:ef7eb2e8f9f7 426 #define TIM_CHANNEL_3 ((uint32_t)0x0008U)
<> 144:ef7eb2e8f9f7 427 #define TIM_CHANNEL_4 ((uint32_t)0x000CU)
<> 144:ef7eb2e8f9f7 428 #define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /**
<> 144:ef7eb2e8f9f7 431 * @}
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<> 144:ef7eb2e8f9f7 435 * @{
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<> 144:ef7eb2e8f9f7 438 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<> 144:ef7eb2e8f9f7 439 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<> 144:ef7eb2e8f9f7 445 * @{
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 144:ef7eb2e8f9f7 448 connected to IC1, IC2, IC3 or IC4, respectively */
<> 144:ef7eb2e8f9f7 449 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 144:ef7eb2e8f9f7 450 connected to IC2, IC1, IC4 or IC3, respectively */
<> 144:ef7eb2e8f9f7 451 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<> 144:ef7eb2e8f9f7 458 * @{
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
<> 144:ef7eb2e8f9f7 461 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
<> 144:ef7eb2e8f9f7 462 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
<> 144:ef7eb2e8f9f7 463 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<> 144:ef7eb2e8f9f7 469 * @{
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<> 144:ef7eb2e8f9f7 472 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 473 /**
<> 144:ef7eb2e8f9f7 474 * @}
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<> 144:ef7eb2e8f9f7 478 * @{
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<> 144:ef7eb2e8f9f7 481 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<> 144:ef7eb2e8f9f7 482 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @}
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
<> 144:ef7eb2e8f9f7 489 * @{
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 #define TIM_IT_UPDATE (TIM_DIER_UIE)
<> 144:ef7eb2e8f9f7 492 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
<> 144:ef7eb2e8f9f7 493 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
<> 144:ef7eb2e8f9f7 494 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
<> 144:ef7eb2e8f9f7 495 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
<> 144:ef7eb2e8f9f7 496 #define TIM_IT_COM (TIM_DIER_COMIE)
<> 144:ef7eb2e8f9f7 497 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
<> 144:ef7eb2e8f9f7 498 #define TIM_IT_BREAK (TIM_DIER_BIE)
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @}
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** @defgroup TIM_Commutation_Source TIM Commutation Source
<> 144:ef7eb2e8f9f7 504 * @{
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
<> 144:ef7eb2e8f9f7 507 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /** @defgroup TIM_DMA_sources TIM DMA sources
<> 144:ef7eb2e8f9f7 513 * @{
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
<> 144:ef7eb2e8f9f7 516 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<> 144:ef7eb2e8f9f7 517 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<> 144:ef7eb2e8f9f7 518 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<> 144:ef7eb2e8f9f7 519 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<> 144:ef7eb2e8f9f7 520 #define TIM_DMA_COM (TIM_DIER_COMDE)
<> 144:ef7eb2e8f9f7 521 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /** @defgroup TIM_Event_Source TIM Event Source
<> 144:ef7eb2e8f9f7 527 * @{
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<> 144:ef7eb2e8f9f7 530 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<> 144:ef7eb2e8f9f7 531 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<> 144:ef7eb2e8f9f7 532 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<> 144:ef7eb2e8f9f7 533 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<> 144:ef7eb2e8f9f7 534 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
<> 144:ef7eb2e8f9f7 535 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<> 144:ef7eb2e8f9f7 536 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @}
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /** @defgroup TIM_Flag_definition TIM Flag definition
<> 144:ef7eb2e8f9f7 543 * @{
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
<> 144:ef7eb2e8f9f7 546 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<> 144:ef7eb2e8f9f7 547 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<> 144:ef7eb2e8f9f7 548 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<> 144:ef7eb2e8f9f7 549 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<> 144:ef7eb2e8f9f7 550 #define TIM_FLAG_COM (TIM_SR_COMIF)
<> 144:ef7eb2e8f9f7 551 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<> 144:ef7eb2e8f9f7 552 #define TIM_FLAG_BREAK (TIM_SR_BIF)
<> 144:ef7eb2e8f9f7 553 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<> 144:ef7eb2e8f9f7 554 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<> 144:ef7eb2e8f9f7 555 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<> 144:ef7eb2e8f9f7 556 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @}
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /** @defgroup TIM_Clock_Source TIM Clock Source
<> 144:ef7eb2e8f9f7 562 * @{
<> 144:ef7eb2e8f9f7 563 */
<> 144:ef7eb2e8f9f7 564 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<> 144:ef7eb2e8f9f7 565 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<> 144:ef7eb2e8f9f7 566 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 567 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<> 144:ef7eb2e8f9f7 568 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<> 144:ef7eb2e8f9f7 569 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
<> 144:ef7eb2e8f9f7 570 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 571 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 572 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
<> 144:ef7eb2e8f9f7 573 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @}
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<> 144:ef7eb2e8f9f7 579 * @{
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
<> 144:ef7eb2e8f9f7 582 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
<> 144:ef7eb2e8f9f7 583 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 584 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 585 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
<> 144:ef7eb2e8f9f7 586 /**
<> 144:ef7eb2e8f9f7 587 * @}
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<> 144:ef7eb2e8f9f7 591 * @{
<> 144:ef7eb2e8f9f7 592 */
<> 144:ef7eb2e8f9f7 593 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 594 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 595 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 596 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 597 /**
<> 144:ef7eb2e8f9f7 598 * @}
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
<> 144:ef7eb2e8f9f7 602 * @{
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
<> 144:ef7eb2e8f9f7 605 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @}
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
<> 144:ef7eb2e8f9f7 611 * @{
<> 144:ef7eb2e8f9f7 612 */
<> 144:ef7eb2e8f9f7 613 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
<> 144:ef7eb2e8f9f7 614 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @}
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
<> 144:ef7eb2e8f9f7 620 * @{
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 623 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 624 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 625 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 626 /**
<> 144:ef7eb2e8f9f7 627 * @}
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
<> 144:ef7eb2e8f9f7 631 * @{
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
<> 144:ef7eb2e8f9f7 634 #define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @}
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
<> 144:ef7eb2e8f9f7 640 * @{
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
<> 144:ef7eb2e8f9f7 643 #define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @}
<> 144:ef7eb2e8f9f7 646 */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /** @defgroup TIM_Lock_level TIM Lock level
<> 144:ef7eb2e8f9f7 649 * @{
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 652 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
<> 144:ef7eb2e8f9f7 653 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
<> 144:ef7eb2e8f9f7 654 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * @}
<> 144:ef7eb2e8f9f7 657 */
<> 144:ef7eb2e8f9f7 658 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
<> 144:ef7eb2e8f9f7 659 * @{
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
<> 144:ef7eb2e8f9f7 662 #define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @}
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /** @defgroup TIM_Break_Polarity TIM Break Polarity
<> 144:ef7eb2e8f9f7 668 * @{
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 671 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
<> 144:ef7eb2e8f9f7 677 * @{
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
<> 144:ef7eb2e8f9f7 680 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @}
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<> 144:ef7eb2e8f9f7 686 * @{
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #define TIM_TRGO_RESET ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 689 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<> 144:ef7eb2e8f9f7 690 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<> 144:ef7eb2e8f9f7 691 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 692 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<> 144:ef7eb2e8f9f7 693 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 694 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
<> 144:ef7eb2e8f9f7 695 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @}
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /** @defgroup TIM_Slave_Mode TIM Slave Mode
<> 144:ef7eb2e8f9f7 701 * @{
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 704 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U)
<> 144:ef7eb2e8f9f7 705 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U)
<> 144:ef7eb2e8f9f7 706 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U)
<> 144:ef7eb2e8f9f7 707 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U)
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @}
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
<> 144:ef7eb2e8f9f7 713 * @{
<> 144:ef7eb2e8f9f7 714 */
<> 144:ef7eb2e8f9f7 715 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
<> 144:ef7eb2e8f9f7 716 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 717 /**
<> 144:ef7eb2e8f9f7 718 * @}
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<> 144:ef7eb2e8f9f7 722 * @{
<> 144:ef7eb2e8f9f7 723 */
<> 144:ef7eb2e8f9f7 724 #define TIM_TS_ITR0 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 725 #define TIM_TS_ITR1 ((uint32_t)0x0010U)
<> 144:ef7eb2e8f9f7 726 #define TIM_TS_ITR2 ((uint32_t)0x0020U)
<> 144:ef7eb2e8f9f7 727 #define TIM_TS_ITR3 ((uint32_t)0x0030U)
<> 144:ef7eb2e8f9f7 728 #define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
<> 144:ef7eb2e8f9f7 729 #define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
<> 144:ef7eb2e8f9f7 730 #define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
<> 144:ef7eb2e8f9f7 731 #define TIM_TS_ETRF ((uint32_t)0x0070U)
<> 144:ef7eb2e8f9f7 732 #define TIM_TS_NONE ((uint32_t)0xFFFFU)
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @}
<> 144:ef7eb2e8f9f7 735 */
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<> 144:ef7eb2e8f9f7 738 * @{
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
<> 144:ef7eb2e8f9f7 741 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
<> 144:ef7eb2e8f9f7 742 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 743 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 744 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @}
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<> 144:ef7eb2e8f9f7 750 * @{
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 144:ef7eb2e8f9f7 753 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
<> 144:ef7eb2e8f9f7 754 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
<> 144:ef7eb2e8f9f7 755 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
<> 144:ef7eb2e8f9f7 756 /**
<> 144:ef7eb2e8f9f7 757 * @}
<> 144:ef7eb2e8f9f7 758 */
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
<> 144:ef7eb2e8f9f7 762 * @{
<> 144:ef7eb2e8f9f7 763 */
<> 144:ef7eb2e8f9f7 764 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 765 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @}
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
<> 144:ef7eb2e8f9f7 771 * @{
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773 #define TIM_DMABASE_CR1 (0x00000000U)
<> 144:ef7eb2e8f9f7 774 #define TIM_DMABASE_CR2 (0x00000001U)
<> 144:ef7eb2e8f9f7 775 #define TIM_DMABASE_SMCR (0x00000002U)
<> 144:ef7eb2e8f9f7 776 #define TIM_DMABASE_DIER (0x00000003U)
<> 144:ef7eb2e8f9f7 777 #define TIM_DMABASE_SR (0x00000004U)
<> 144:ef7eb2e8f9f7 778 #define TIM_DMABASE_EGR (0x00000005U)
<> 144:ef7eb2e8f9f7 779 #define TIM_DMABASE_CCMR1 (0x00000006U)
<> 144:ef7eb2e8f9f7 780 #define TIM_DMABASE_CCMR2 (0x00000007U)
<> 144:ef7eb2e8f9f7 781 #define TIM_DMABASE_CCER (0x00000008U)
<> 144:ef7eb2e8f9f7 782 #define TIM_DMABASE_CNT (0x00000009U)
<> 144:ef7eb2e8f9f7 783 #define TIM_DMABASE_PSC (0x0000000AU)
<> 144:ef7eb2e8f9f7 784 #define TIM_DMABASE_ARR (0x0000000BU)
<> 144:ef7eb2e8f9f7 785 #define TIM_DMABASE_RCR (0x0000000CU)
<> 144:ef7eb2e8f9f7 786 #define TIM_DMABASE_CCR1 (0x0000000DU)
<> 144:ef7eb2e8f9f7 787 #define TIM_DMABASE_CCR2 (0x0000000EU)
<> 144:ef7eb2e8f9f7 788 #define TIM_DMABASE_CCR3 (0x0000000FU)
<> 144:ef7eb2e8f9f7 789 #define TIM_DMABASE_CCR4 (0x00000010U)
<> 144:ef7eb2e8f9f7 790 #define TIM_DMABASE_BDTR (0x00000011U)
<> 144:ef7eb2e8f9f7 791 #define TIM_DMABASE_DCR (0x00000012U)
<> 144:ef7eb2e8f9f7 792 #define TIM_DMABASE_OR (0x00000013U)
<> 144:ef7eb2e8f9f7 793 /**
<> 144:ef7eb2e8f9f7 794 * @}
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<> 144:ef7eb2e8f9f7 798 * @{
<> 144:ef7eb2e8f9f7 799 */
<> 144:ef7eb2e8f9f7 800 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
<> 144:ef7eb2e8f9f7 801 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
<> 144:ef7eb2e8f9f7 802 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
<> 144:ef7eb2e8f9f7 803 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
<> 144:ef7eb2e8f9f7 804 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
<> 144:ef7eb2e8f9f7 805 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
<> 144:ef7eb2e8f9f7 806 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
<> 144:ef7eb2e8f9f7 807 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
<> 144:ef7eb2e8f9f7 808 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
<> 144:ef7eb2e8f9f7 809 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
<> 144:ef7eb2e8f9f7 810 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
<> 144:ef7eb2e8f9f7 811 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
<> 144:ef7eb2e8f9f7 812 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
<> 144:ef7eb2e8f9f7 813 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
<> 144:ef7eb2e8f9f7 814 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
<> 144:ef7eb2e8f9f7 815 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
<> 144:ef7eb2e8f9f7 816 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
<> 144:ef7eb2e8f9f7 817 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @}
<> 144:ef7eb2e8f9f7 820 */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /** @defgroup DMA_Handle_index DMA Handle index
<> 144:ef7eb2e8f9f7 823 * @{
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
<> 144:ef7eb2e8f9f7 826 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
<> 144:ef7eb2e8f9f7 827 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
<> 144:ef7eb2e8f9f7 828 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
<> 144:ef7eb2e8f9f7 829 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
<> 144:ef7eb2e8f9f7 830 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
<> 144:ef7eb2e8f9f7 831 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
<> 144:ef7eb2e8f9f7 832 /**
<> 144:ef7eb2e8f9f7 833 * @}
<> 144:ef7eb2e8f9f7 834 */
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 /** @defgroup Channel_CC_State Channel CC State
<> 144:ef7eb2e8f9f7 837 * @{
<> 144:ef7eb2e8f9f7 838 */
<> 144:ef7eb2e8f9f7 839 #define TIM_CCx_ENABLE ((uint32_t)0x0001U)
<> 144:ef7eb2e8f9f7 840 #define TIM_CCx_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 841 #define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
<> 144:ef7eb2e8f9f7 842 #define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 852 /** @defgroup TIM_Exported_Macros TIM Exported Macros
<> 144:ef7eb2e8f9f7 853 * @{
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 /** @brief Reset TIM handle state
<> 144:ef7eb2e8f9f7 856 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 857 * @retval None
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @brief Enable the TIM peripheral.
<> 144:ef7eb2e8f9f7 863 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 864 * @retval None
<> 144:ef7eb2e8f9f7 865 */
<> 144:ef7eb2e8f9f7 866 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @brief Enable the TIM main Output.
<> 144:ef7eb2e8f9f7 870 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 871 * @retval None
<> 144:ef7eb2e8f9f7 872 */
<> 144:ef7eb2e8f9f7 873 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @brief Disable the TIM peripheral.
<> 144:ef7eb2e8f9f7 878 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 879 * @retval None
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881 #define __HAL_TIM_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 882 do { \
<> 144:ef7eb2e8f9f7 883 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<> 144:ef7eb2e8f9f7 884 { \
<> 144:ef7eb2e8f9f7 885 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<> 144:ef7eb2e8f9f7 886 { \
<> 144:ef7eb2e8f9f7 887 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<> 144:ef7eb2e8f9f7 888 } \
<> 144:ef7eb2e8f9f7 889 } \
<> 144:ef7eb2e8f9f7 890 } while(0)
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
<> 144:ef7eb2e8f9f7 893 channels have been disabled */
<> 144:ef7eb2e8f9f7 894 /**
<> 144:ef7eb2e8f9f7 895 * @brief Disable the TIM main Output.
<> 144:ef7eb2e8f9f7 896 * @param __HANDLE__: TIM handle
<> 144:ef7eb2e8f9f7 897 * @retval None
<> 144:ef7eb2e8f9f7 898 */
<> 144:ef7eb2e8f9f7 899 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 900 do { \
<> 144:ef7eb2e8f9f7 901 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<> 144:ef7eb2e8f9f7 902 { \
<> 144:ef7eb2e8f9f7 903 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<> 144:ef7eb2e8f9f7 904 { \
<> 144:ef7eb2e8f9f7 905 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
<> 144:ef7eb2e8f9f7 906 } \
<> 144:ef7eb2e8f9f7 907 } \
<> 144:ef7eb2e8f9f7 908 } while(0)
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 911 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
<> 144:ef7eb2e8f9f7 912 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 913 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<> 144:ef7eb2e8f9f7 914 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 915 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 918 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
<> 144:ef7eb2e8f9f7 921 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 144:ef7eb2e8f9f7 924 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
<> 144:ef7eb2e8f9f7 925 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
<> 144:ef7eb2e8f9f7 926 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
<> 144:ef7eb2e8f9f7 927 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 930 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
<> 144:ef7eb2e8f9f7 931 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
<> 144:ef7eb2e8f9f7 932 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
<> 144:ef7eb2e8f9f7 933 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 144:ef7eb2e8f9f7 936 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
<> 144:ef7eb2e8f9f7 937 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
<> 144:ef7eb2e8f9f7 938 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
<> 144:ef7eb2e8f9f7 939 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 942 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
<> 144:ef7eb2e8f9f7 943 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
<> 144:ef7eb2e8f9f7 944 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
<> 144:ef7eb2e8f9f7 945 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @brief Sets the TIM Capture Compare Register value on runtime without
<> 144:ef7eb2e8f9f7 949 * calling another time ConfigChannel function.
<> 144:ef7eb2e8f9f7 950 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 951 * @param __CHANNEL__ : TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 952 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 953 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 954 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 955 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 956 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 957 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 144:ef7eb2e8f9f7 958 * @retval None
<> 144:ef7eb2e8f9f7 959 */
<> 144:ef7eb2e8f9f7 960 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 144:ef7eb2e8f9f7 961 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /**
<> 144:ef7eb2e8f9f7 964 * @brief Gets the TIM Capture Compare Register value on runtime
<> 144:ef7eb2e8f9f7 965 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 966 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
<> 144:ef7eb2e8f9f7 967 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 968 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 144:ef7eb2e8f9f7 969 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 144:ef7eb2e8f9f7 970 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 144:ef7eb2e8f9f7 971 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 144:ef7eb2e8f9f7 972 * @retval None
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 975 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief Sets the TIM Counter Register value on runtime.
<> 144:ef7eb2e8f9f7 979 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 980 * @param __COUNTER__: specifies the Counter register new value.
<> 144:ef7eb2e8f9f7 981 * @retval None
<> 144:ef7eb2e8f9f7 982 */
<> 144:ef7eb2e8f9f7 983 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /**
<> 144:ef7eb2e8f9f7 986 * @brief Gets the TIM Counter Register value on runtime.
<> 144:ef7eb2e8f9f7 987 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 988 * @retval None
<> 144:ef7eb2e8f9f7 989 */
<> 144:ef7eb2e8f9f7 990 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /**
<> 144:ef7eb2e8f9f7 993 * @brief Sets the TIM Autoreload Register value on runtime without calling
<> 144:ef7eb2e8f9f7 994 * another time any Init function.
<> 144:ef7eb2e8f9f7 995 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 996 * @param __AUTORELOAD__: specifies the Counter register new value.
<> 144:ef7eb2e8f9f7 997 * @retval None
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<> 144:ef7eb2e8f9f7 1000 do{ \
<> 144:ef7eb2e8f9f7 1001 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<> 144:ef7eb2e8f9f7 1002 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<> 144:ef7eb2e8f9f7 1003 } while(0)
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @brief Gets the TIM Autoreload Register value on runtime
<> 144:ef7eb2e8f9f7 1006 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1007 * @retval None
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /**
<> 144:ef7eb2e8f9f7 1012 * @brief Sets the TIM Clock Division value on runtime without calling
<> 144:ef7eb2e8f9f7 1013 * another time any Init function.
<> 144:ef7eb2e8f9f7 1014 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1015 * @param __CKD__: specifies the clock division value.
<> 144:ef7eb2e8f9f7 1016 * This parameter can be one of the following value:
<> 144:ef7eb2e8f9f7 1017 * @arg TIM_CLOCKDIVISION_DIV1
<> 144:ef7eb2e8f9f7 1018 * @arg TIM_CLOCKDIVISION_DIV2
<> 144:ef7eb2e8f9f7 1019 * @arg TIM_CLOCKDIVISION_DIV4
<> 144:ef7eb2e8f9f7 1020 * @retval None
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<> 144:ef7eb2e8f9f7 1023 do{ \
<> 144:ef7eb2e8f9f7 1024 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<> 144:ef7eb2e8f9f7 1025 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
<> 144:ef7eb2e8f9f7 1026 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
<> 144:ef7eb2e8f9f7 1027 } while(0)
<> 144:ef7eb2e8f9f7 1028 /**
<> 144:ef7eb2e8f9f7 1029 * @brief Gets the TIM Clock Division value on runtime
<> 144:ef7eb2e8f9f7 1030 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1031 * @retval None
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @brief Sets the TIM Input Capture prescaler on runtime without calling
<> 144:ef7eb2e8f9f7 1037 * another time HAL_TIM_IC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 1038 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1039 * @param __CHANNEL__ : TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1040 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1041 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1042 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1043 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1044 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1045 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<> 144:ef7eb2e8f9f7 1046 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1047 * @arg TIM_ICPSC_DIV1: no prescaler
<> 144:ef7eb2e8f9f7 1048 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<> 144:ef7eb2e8f9f7 1049 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<> 144:ef7eb2e8f9f7 1050 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<> 144:ef7eb2e8f9f7 1051 * @retval None
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 144:ef7eb2e8f9f7 1054 do{ \
<> 144:ef7eb2e8f9f7 1055 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<> 144:ef7eb2e8f9f7 1056 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<> 144:ef7eb2e8f9f7 1057 } while(0)
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 /**
<> 144:ef7eb2e8f9f7 1060 * @brief Gets the TIM Input Capture prescaler on runtime
<> 144:ef7eb2e8f9f7 1061 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1062 * @param __CHANNEL__ : TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1063 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1064 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<> 144:ef7eb2e8f9f7 1065 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<> 144:ef7eb2e8f9f7 1066 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<> 144:ef7eb2e8f9f7 1067 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
<> 144:ef7eb2e8f9f7 1068 * @retval None
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 1071 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<> 144:ef7eb2e8f9f7 1072 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
<> 144:ef7eb2e8f9f7 1073 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<> 144:ef7eb2e8f9f7 1074 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<> 144:ef7eb2e8f9f7 1078 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1079 * @note When the USR bit of the TIMx_CR1 register is set, only counter
<> 144:ef7eb2e8f9f7 1080 * overflow/underflow generates an update interrupt or DMA request (if
<> 144:ef7eb2e8f9f7 1081 * enabled)
<> 144:ef7eb2e8f9f7 1082 * @retval None
<> 144:ef7eb2e8f9f7 1083 */
<> 144:ef7eb2e8f9f7 1084 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1085 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /**
<> 144:ef7eb2e8f9f7 1088 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<> 144:ef7eb2e8f9f7 1089 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1090 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
<> 144:ef7eb2e8f9f7 1091 * following events generate an update interrupt or DMA request (if
<> 144:ef7eb2e8f9f7 1092 * enabled):
<> 144:ef7eb2e8f9f7 1093 * _ Counter overflow/underflow
<> 144:ef7eb2e8f9f7 1094 * _ Setting the UG bit
<> 144:ef7eb2e8f9f7 1095 * _ Update generation through the slave mode controller
<> 144:ef7eb2e8f9f7 1096 * @retval None
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 1099 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /**
<> 144:ef7eb2e8f9f7 1102 * @brief Sets the TIM Capture x input polarity on runtime.
<> 144:ef7eb2e8f9f7 1103 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 1104 * @param __CHANNEL__: TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 1105 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1106 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1107 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1108 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1109 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1110 * @param __POLARITY__: Polarity for TIx source
<> 144:ef7eb2e8f9f7 1111 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<> 144:ef7eb2e8f9f7 1112 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<> 144:ef7eb2e8f9f7 1113 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<> 144:ef7eb2e8f9f7 1114 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<> 144:ef7eb2e8f9f7 1115 * @retval None
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 144:ef7eb2e8f9f7 1118 do{ \
<> 144:ef7eb2e8f9f7 1119 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<> 144:ef7eb2e8f9f7 1120 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<> 144:ef7eb2e8f9f7 1121 }while(0)
<> 144:ef7eb2e8f9f7 1122 /**
<> 144:ef7eb2e8f9f7 1123 * @}
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* Include TIM HAL Extension module */
<> 144:ef7eb2e8f9f7 1127 #include "stm32f2xx_hal_tim_ex.h"
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1130 /** @addtogroup TIM_Exported_Functions
<> 144:ef7eb2e8f9f7 1131 * @{
<> 144:ef7eb2e8f9f7 1132 */
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /** @addtogroup TIM_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1135 * @{
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /* Time Base functions ********************************************************/
<> 144:ef7eb2e8f9f7 1139 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1140 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1141 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1142 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1143 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1144 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1145 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1146 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1147 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1148 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1149 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1150 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1151 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @}
<> 144:ef7eb2e8f9f7 1154 */
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /** @addtogroup TIM_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 1157 * @{
<> 144:ef7eb2e8f9f7 1158 */
<> 144:ef7eb2e8f9f7 1159 /* Timer Output Compare functions **********************************************/
<> 144:ef7eb2e8f9f7 1160 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1161 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1162 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1163 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1164 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1165 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1166 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1167 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1168 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1169 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1170 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1171 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1172 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /**
<> 144:ef7eb2e8f9f7 1175 * @}
<> 144:ef7eb2e8f9f7 1176 */
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /** @addtogroup TIM_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1179 * @{
<> 144:ef7eb2e8f9f7 1180 */
<> 144:ef7eb2e8f9f7 1181 /* Timer PWM functions *********************************************************/
<> 144:ef7eb2e8f9f7 1182 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1183 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1184 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1185 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1186 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1187 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1188 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1189 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1190 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1191 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1192 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1193 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1194 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /**
<> 144:ef7eb2e8f9f7 1197 * @}
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /** @addtogroup TIM_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 1201 * @{
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203 /* Timer Input Capture functions ***********************************************/
<> 144:ef7eb2e8f9f7 1204 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1205 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1206 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1207 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1208 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1209 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1210 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1211 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1212 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1213 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1214 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1215 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 1216 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /**
<> 144:ef7eb2e8f9f7 1219 * @}
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /** @addtogroup TIM_Exported_Functions_Group5
<> 144:ef7eb2e8f9f7 1223 * @{
<> 144:ef7eb2e8f9f7 1224 */
<> 144:ef7eb2e8f9f7 1225 /* Timer One Pulse functions ***************************************************/
<> 144:ef7eb2e8f9f7 1226 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<> 144:ef7eb2e8f9f7 1227 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1228 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1229 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1230 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1231 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1232 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1235 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1236 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /**
<> 144:ef7eb2e8f9f7 1239 * @}
<> 144:ef7eb2e8f9f7 1240 */
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /** @addtogroup TIM_Exported_Functions_Group6
<> 144:ef7eb2e8f9f7 1243 * @{
<> 144:ef7eb2e8f9f7 1244 */
<> 144:ef7eb2e8f9f7 1245 /* Timer Encoder functions *****************************************************/
<> 144:ef7eb2e8f9f7 1246 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 1247 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1248 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1249 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1250 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 1251 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1252 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1253 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 1254 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1255 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1256 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 1257 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
<> 144:ef7eb2e8f9f7 1258 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /**
<> 144:ef7eb2e8f9f7 1261 * @}
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /** @addtogroup TIM_Exported_Functions_Group7
<> 144:ef7eb2e8f9f7 1265 * @{
<> 144:ef7eb2e8f9f7 1266 */
<> 144:ef7eb2e8f9f7 1267 /* Interrupt Handler functions **********************************************/
<> 144:ef7eb2e8f9f7 1268 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /**
<> 144:ef7eb2e8f9f7 1271 * @}
<> 144:ef7eb2e8f9f7 1272 */
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 /** @addtogroup TIM_Exported_Functions_Group8
<> 144:ef7eb2e8f9f7 1275 * @{
<> 144:ef7eb2e8f9f7 1276 */
<> 144:ef7eb2e8f9f7 1277 /* Control functions *********************************************************/
<> 144:ef7eb2e8f9f7 1278 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1279 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1280 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1281 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<> 144:ef7eb2e8f9f7 1282 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1283 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
<> 144:ef7eb2e8f9f7 1284 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<> 144:ef7eb2e8f9f7 1285 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 1286 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 1287 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 144:ef7eb2e8f9f7 1288 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 144:ef7eb2e8f9f7 1289 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 144:ef7eb2e8f9f7 1290 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 144:ef7eb2e8f9f7 1291 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 144:ef7eb2e8f9f7 1292 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 144:ef7eb2e8f9f7 1293 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<> 144:ef7eb2e8f9f7 1294 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @}
<> 144:ef7eb2e8f9f7 1298 */
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /** @addtogroup TIM_Exported_Functions_Group9
<> 144:ef7eb2e8f9f7 1301 * @{
<> 144:ef7eb2e8f9f7 1302 */
<> 144:ef7eb2e8f9f7 1303 /* Callback in non blocking modes (Interrupt and DMA) *************************/
<> 144:ef7eb2e8f9f7 1304 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1305 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1306 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1307 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1308 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1309 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /**
<> 144:ef7eb2e8f9f7 1312 * @}
<> 144:ef7eb2e8f9f7 1313 */
<> 144:ef7eb2e8f9f7 1314
<> 144:ef7eb2e8f9f7 1315 /** @addtogroup TIM_Exported_Functions_Group10
<> 144:ef7eb2e8f9f7 1316 * @{
<> 144:ef7eb2e8f9f7 1317 */
<> 144:ef7eb2e8f9f7 1318 /* Peripheral State functions **************************************************/
<> 144:ef7eb2e8f9f7 1319 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1320 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1321 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1322 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1323 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1324 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @}
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1335 /** @defgroup TIM_Private_Macros TIM Private Macros
<> 144:ef7eb2e8f9f7 1336 * @{
<> 144:ef7eb2e8f9f7 1337 */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
<> 144:ef7eb2e8f9f7 1340 * @{
<> 144:ef7eb2e8f9f7 1341 */
<> 144:ef7eb2e8f9f7 1342 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
<> 144:ef7eb2e8f9f7 1343 ((MODE) == TIM_COUNTERMODE_DOWN) || \
<> 144:ef7eb2e8f9f7 1344 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
<> 144:ef7eb2e8f9f7 1345 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
<> 144:ef7eb2e8f9f7 1346 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
<> 144:ef7eb2e8f9f7 1349 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
<> 144:ef7eb2e8f9f7 1350 ((DIV) == TIM_CLOCKDIVISION_DIV4))
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
<> 144:ef7eb2e8f9f7 1353 ((MODE) == TIM_OCMODE_PWM2))
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
<> 144:ef7eb2e8f9f7 1356 ((MODE) == TIM_OCMODE_ACTIVE) || \
<> 144:ef7eb2e8f9f7 1357 ((MODE) == TIM_OCMODE_INACTIVE) || \
<> 144:ef7eb2e8f9f7 1358 ((MODE) == TIM_OCMODE_TOGGLE) || \
<> 144:ef7eb2e8f9f7 1359 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 144:ef7eb2e8f9f7 1360 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
<> 144:ef7eb2e8f9f7 1363 ((STATE) == TIM_OCFAST_ENABLE))
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
<> 144:ef7eb2e8f9f7 1366 ((POLARITY) == TIM_OCPOLARITY_LOW))
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
<> 144:ef7eb2e8f9f7 1369 ((POLARITY) == TIM_OCNPOLARITY_LOW))
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
<> 144:ef7eb2e8f9f7 1372 ((STATE) == TIM_OCIDLESTATE_RESET))
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
<> 144:ef7eb2e8f9f7 1375 ((STATE) == TIM_OCNIDLESTATE_RESET))
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1378 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1379 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 1380 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 1381 ((CHANNEL) == TIM_CHANNEL_ALL))
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1384 ((CHANNEL) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 1387 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 1388 ((CHANNEL) == TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 1391 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
<> 144:ef7eb2e8f9f7 1392 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
<> 144:ef7eb2e8f9f7 1395 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
<> 144:ef7eb2e8f9f7 1396 ((SELECTION) == TIM_ICSELECTION_TRC))
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
<> 144:ef7eb2e8f9f7 1399 ((PRESCALER) == TIM_ICPSC_DIV2) || \
<> 144:ef7eb2e8f9f7 1400 ((PRESCALER) == TIM_ICPSC_DIV4) || \
<> 144:ef7eb2e8f9f7 1401 ((PRESCALER) == TIM_ICPSC_DIV8))
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
<> 144:ef7eb2e8f9f7 1404 ((MODE) == TIM_OPMODE_REPETITIVE))
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
<> 144:ef7eb2e8f9f7 1409 ((MODE) == TIM_ENCODERMODE_TI2) || \
<> 144:ef7eb2e8f9f7 1410 ((MODE) == TIM_ENCODERMODE_TI12))
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
<> 144:ef7eb2e8f9f7 1415 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
<> 144:ef7eb2e8f9f7 1416 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
<> 144:ef7eb2e8f9f7 1417 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
<> 144:ef7eb2e8f9f7 1418 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
<> 144:ef7eb2e8f9f7 1419 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
<> 144:ef7eb2e8f9f7 1420 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
<> 144:ef7eb2e8f9f7 1421 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
<> 144:ef7eb2e8f9f7 1422 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
<> 144:ef7eb2e8f9f7 1423 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
<> 144:ef7eb2e8f9f7 1426 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
<> 144:ef7eb2e8f9f7 1427 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
<> 144:ef7eb2e8f9f7 1428 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
<> 144:ef7eb2e8f9f7 1429 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1432 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1433 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1434 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
<> 144:ef7eb2e8f9f7 1439 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
<> 144:ef7eb2e8f9f7 1442 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1445 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1446 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1447 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
<> 144:ef7eb2e8f9f7 1452 ((STATE) == TIM_OSSR_DISABLE))
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
<> 144:ef7eb2e8f9f7 1455 ((STATE) == TIM_OSSI_DISABLE))
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
<> 144:ef7eb2e8f9f7 1458 ((LEVEL) == TIM_LOCKLEVEL_1) || \
<> 144:ef7eb2e8f9f7 1459 ((LEVEL) == TIM_LOCKLEVEL_2) || \
<> 144:ef7eb2e8f9f7 1460 ((LEVEL) == TIM_LOCKLEVEL_3))
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
<> 144:ef7eb2e8f9f7 1463 ((STATE) == TIM_BREAK_DISABLE))
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 1466 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 1469 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
<> 144:ef7eb2e8f9f7 1472 ((SOURCE) == TIM_TRGO_ENABLE) || \
<> 144:ef7eb2e8f9f7 1473 ((SOURCE) == TIM_TRGO_UPDATE) || \
<> 144:ef7eb2e8f9f7 1474 ((SOURCE) == TIM_TRGO_OC1) || \
<> 144:ef7eb2e8f9f7 1475 ((SOURCE) == TIM_TRGO_OC1REF) || \
<> 144:ef7eb2e8f9f7 1476 ((SOURCE) == TIM_TRGO_OC2REF) || \
<> 144:ef7eb2e8f9f7 1477 ((SOURCE) == TIM_TRGO_OC3REF) || \
<> 144:ef7eb2e8f9f7 1478 ((SOURCE) == TIM_TRGO_OC4REF))
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 1481 ((MODE) == TIM_SLAVEMODE_GATED) || \
<> 144:ef7eb2e8f9f7 1482 ((MODE) == TIM_SLAVEMODE_RESET) || \
<> 144:ef7eb2e8f9f7 1483 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 1484 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 1487 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
<> 144:ef7eb2e8f9f7 1490 ((SELECTION) == TIM_TS_ITR1) || \
<> 144:ef7eb2e8f9f7 1491 ((SELECTION) == TIM_TS_ITR2) || \
<> 144:ef7eb2e8f9f7 1492 ((SELECTION) == TIM_TS_ITR3) || \
<> 144:ef7eb2e8f9f7 1493 ((SELECTION) == TIM_TS_TI1F_ED) || \
<> 144:ef7eb2e8f9f7 1494 ((SELECTION) == TIM_TS_TI1FP1) || \
<> 144:ef7eb2e8f9f7 1495 ((SELECTION) == TIM_TS_TI2FP2) || \
<> 144:ef7eb2e8f9f7 1496 ((SELECTION) == TIM_TS_ETRF))
<> 144:ef7eb2e8f9f7 1497
<> 144:ef7eb2e8f9f7 1498 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
<> 144:ef7eb2e8f9f7 1499 ((SELECTION) == TIM_TS_ITR1) || \
<> 144:ef7eb2e8f9f7 1500 ((SELECTION) == TIM_TS_ITR2) || \
<> 144:ef7eb2e8f9f7 1501 ((SELECTION) == TIM_TS_ITR3) || \
<> 144:ef7eb2e8f9f7 1502 ((SELECTION) == TIM_TS_NONE))
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
<> 144:ef7eb2e8f9f7 1505 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
<> 144:ef7eb2e8f9f7 1506 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
<> 144:ef7eb2e8f9f7 1507 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
<> 144:ef7eb2e8f9f7 1508 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
<> 144:ef7eb2e8f9f7 1511 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
<> 144:ef7eb2e8f9f7 1512 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
<> 144:ef7eb2e8f9f7 1513 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
<> 144:ef7eb2e8f9f7 1518 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
<> 144:ef7eb2e8f9f7 1521 ((BASE) == TIM_DMABASE_CR2) || \
<> 144:ef7eb2e8f9f7 1522 ((BASE) == TIM_DMABASE_SMCR) || \
<> 144:ef7eb2e8f9f7 1523 ((BASE) == TIM_DMABASE_DIER) || \
<> 144:ef7eb2e8f9f7 1524 ((BASE) == TIM_DMABASE_SR) || \
<> 144:ef7eb2e8f9f7 1525 ((BASE) == TIM_DMABASE_EGR) || \
<> 144:ef7eb2e8f9f7 1526 ((BASE) == TIM_DMABASE_CCMR1) || \
<> 144:ef7eb2e8f9f7 1527 ((BASE) == TIM_DMABASE_CCMR2) || \
<> 144:ef7eb2e8f9f7 1528 ((BASE) == TIM_DMABASE_CCER) || \
<> 144:ef7eb2e8f9f7 1529 ((BASE) == TIM_DMABASE_CNT) || \
<> 144:ef7eb2e8f9f7 1530 ((BASE) == TIM_DMABASE_PSC) || \
<> 144:ef7eb2e8f9f7 1531 ((BASE) == TIM_DMABASE_ARR) || \
<> 144:ef7eb2e8f9f7 1532 ((BASE) == TIM_DMABASE_RCR) || \
<> 144:ef7eb2e8f9f7 1533 ((BASE) == TIM_DMABASE_CCR1) || \
<> 144:ef7eb2e8f9f7 1534 ((BASE) == TIM_DMABASE_CCR2) || \
<> 144:ef7eb2e8f9f7 1535 ((BASE) == TIM_DMABASE_CCR3) || \
<> 144:ef7eb2e8f9f7 1536 ((BASE) == TIM_DMABASE_CCR4) || \
<> 144:ef7eb2e8f9f7 1537 ((BASE) == TIM_DMABASE_BDTR) || \
<> 144:ef7eb2e8f9f7 1538 ((BASE) == TIM_DMABASE_DCR) || \
<> 144:ef7eb2e8f9f7 1539 ((BASE) == TIM_DMABASE_OR))
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
<> 144:ef7eb2e8f9f7 1542 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1543 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1544 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1545 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1546 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1547 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1548 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1549 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1550 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1551 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1552 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1553 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1554 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1555 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1556 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1557 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
<> 144:ef7eb2e8f9f7 1558 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
<> 144:ef7eb2e8f9f7 1559
<> 144:ef7eb2e8f9f7 1560 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<> 144:ef7eb2e8f9f7 1561 /**
<> 144:ef7eb2e8f9f7 1562 * @}
<> 144:ef7eb2e8f9f7 1563 */
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 /** @defgroup TIM_Mask_Definitions TIM Mask Definition
<> 144:ef7eb2e8f9f7 1566 * @{
<> 144:ef7eb2e8f9f7 1567 */
<> 144:ef7eb2e8f9f7 1568 /* The counter of a timer instance is disabled only if all the CCx and CCxN
<> 144:ef7eb2e8f9f7 1569 channels have been disabled */
<> 144:ef7eb2e8f9f7 1570 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
<> 144:ef7eb2e8f9f7 1571 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
<> 144:ef7eb2e8f9f7 1572 /**
<> 144:ef7eb2e8f9f7 1573 * @}
<> 144:ef7eb2e8f9f7 1574 */
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 /**
<> 144:ef7eb2e8f9f7 1577 * @}
<> 144:ef7eb2e8f9f7 1578 */
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1581 /** @defgroup TIM_Private_Functions TIM Private Functions
<> 144:ef7eb2e8f9f7 1582 * @{
<> 144:ef7eb2e8f9f7 1583 */
<> 144:ef7eb2e8f9f7 1584 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
<> 144:ef7eb2e8f9f7 1585 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 1586 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 1587 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1588 void TIM_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1589 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 1590 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<> 144:ef7eb2e8f9f7 1591 /**
<> 144:ef7eb2e8f9f7 1592 * @}
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /**
<> 144:ef7eb2e8f9f7 1596 * @}
<> 144:ef7eb2e8f9f7 1597 */
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 /**
<> 144:ef7eb2e8f9f7 1600 * @}
<> 144:ef7eb2e8f9f7 1601 */
<> 144:ef7eb2e8f9f7 1602
<> 144:ef7eb2e8f9f7 1603 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1604 }
<> 144:ef7eb2e8f9f7 1605 #endif
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 #endif /* __STM32F2xx_HAL_TIM_H */
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/