Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_rcc_ex.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_rcc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of RCC HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup RCCEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief PLLI2S Clock structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
<> 144:ef7eb2e8f9f7 67 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
<> 144:ef7eb2e8f9f7 68 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
<> 144:ef7eb2e8f9f7 71 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<> 144:ef7eb2e8f9f7 72 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 }RCC_PLLI2SInitTypeDef;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /**
<> 144:ef7eb2e8f9f7 77 * @brief RCC extended clocks structure definition
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 typedef struct
<> 144:ef7eb2e8f9f7 80 {
<> 144:ef7eb2e8f9f7 81 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
<> 144:ef7eb2e8f9f7 85 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 }RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 94 /**
<> 144:ef7eb2e8f9f7 95 * @}
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 107 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 108 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 109 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @}
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 119 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 /** @defgroup RCCEx_Exported_Macros RCC Exported Macros
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
<> 144:ef7eb2e8f9f7 134 * @brief Enables or disables the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 135 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 136 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 137 * using it.
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 141 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 142 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 143 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 144 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 145 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 146 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 147 } while(0)
<> 144:ef7eb2e8f9f7 148 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 149 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 150 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 151 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 152 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 153 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 154 } while(0)
<> 144:ef7eb2e8f9f7 155 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 156 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 157 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 158 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 159 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 160 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 161 } while(0)
<> 144:ef7eb2e8f9f7 162 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 163 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 164 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<> 144:ef7eb2e8f9f7 165 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 166 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<> 144:ef7eb2e8f9f7 167 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 168 } while(0)
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
<> 144:ef7eb2e8f9f7 171 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
<> 144:ef7eb2e8f9f7 172 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
<> 144:ef7eb2e8f9f7 173 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 176 * @brief Get the enable or disable status of the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 177 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 178 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 179 * using it.
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET)
<> 144:ef7eb2e8f9f7 183 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET)
<> 144:ef7eb2e8f9f7 184 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET)
<> 144:ef7eb2e8f9f7 185 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET)
<> 144:ef7eb2e8f9f7 186 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
<> 144:ef7eb2e8f9f7 187 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
<> 144:ef7eb2e8f9f7 188 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
<> 144:ef7eb2e8f9f7 189 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET)
<> 144:ef7eb2e8f9f7 190 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET)
<> 144:ef7eb2e8f9f7 191 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET)
<> 144:ef7eb2e8f9f7 192 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET)
<> 144:ef7eb2e8f9f7 193 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
<> 144:ef7eb2e8f9f7 194 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
<> 144:ef7eb2e8f9f7 195 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @}
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief Enable ETHERNET clock.
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 204 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 205 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 206 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 207 } while(0)
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Disable ETHERNET clock.
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
<> 144:ef7eb2e8f9f7 212 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 213 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 214 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 215 } while(0)
<> 144:ef7eb2e8f9f7 216 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
<> 144:ef7eb2e8f9f7 222 * @brief Enable or disable the AHB2 peripheral clock.
<> 144:ef7eb2e8f9f7 223 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 224 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 225 * using it.
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 229 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 230 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 231 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<> 144:ef7eb2e8f9f7 232 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 233 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<> 144:ef7eb2e8f9f7 234 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 235 } while(0)
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
<> 144:ef7eb2e8f9f7 238 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 241 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 242 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 243 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<> 144:ef7eb2e8f9f7 244 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 245 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<> 144:ef7eb2e8f9f7 246 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 247 } while(0)
<> 144:ef7eb2e8f9f7 248 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 249 __IO uint32_t tmpreg = 0x00; \
<> 144:ef7eb2e8f9f7 250 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<> 144:ef7eb2e8f9f7 251 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 252 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<> 144:ef7eb2e8f9f7 253 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 254 } while(0)
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
<> 144:ef7eb2e8f9f7 257 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
<> 144:ef7eb2e8f9f7 258 #endif /* STM32F215xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 259 /**
<> 144:ef7eb2e8f9f7 260 * @}
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 264 * @brief Get the enable or disable status of the AHB2 peripheral clock.
<> 144:ef7eb2e8f9f7 265 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 266 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 267 * using it.
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 271 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET)
<> 144:ef7eb2e8f9f7 272 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET)
<> 144:ef7eb2e8f9f7 273 #endif /* defined(STM32F207xx) || defined(STM32F217xx) */
<> 144:ef7eb2e8f9f7 274 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 275 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET)
<> 144:ef7eb2e8f9f7 276 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET)
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET)
<> 144:ef7eb2e8f9f7 279 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET)
<> 144:ef7eb2e8f9f7 280 #endif /* defined(STM32F215xx) || defined(STM32F217xx) */
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
<> 144:ef7eb2e8f9f7 286 * @brief Force or release AHB1 peripheral reset.
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 290 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
<> 144:ef7eb2e8f9f7 291 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
<> 144:ef7eb2e8f9f7 292 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
<> 144:ef7eb2e8f9f7 298 * @brief Force or release AHB2 peripheral reset.
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 302 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
<> 144:ef7eb2e8f9f7 303 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
<> 144:ef7eb2e8f9f7 304 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 307 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
<> 144:ef7eb2e8f9f7 308 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
<> 144:ef7eb2e8f9f7 311 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
<> 144:ef7eb2e8f9f7 312 #endif /* STM32F215xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
<> 144:ef7eb2e8f9f7 319 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 320 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 321 * power consumption.
<> 144:ef7eb2e8f9f7 322 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 323 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 327 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
<> 144:ef7eb2e8f9f7 328 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
<> 144:ef7eb2e8f9f7 329 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
<> 144:ef7eb2e8f9f7 330 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
<> 144:ef7eb2e8f9f7 333 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
<> 144:ef7eb2e8f9f7 334 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
<> 144:ef7eb2e8f9f7 335 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
<> 144:ef7eb2e8f9f7 336 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
<> 144:ef7eb2e8f9f7 342 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
<> 144:ef7eb2e8f9f7 343 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
<> 144:ef7eb2e8f9f7 344 * power consumption.
<> 144:ef7eb2e8f9f7 345 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<> 144:ef7eb2e8f9f7 346 * @note By default, all peripheral clocks are enabled during SLEEP mode.
<> 144:ef7eb2e8f9f7 347 * @{
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #if defined(STM32F207xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 350 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
<> 144:ef7eb2e8f9f7 351 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
<> 144:ef7eb2e8f9f7 352 #endif /* STM32F207xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 355 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
<> 144:ef7eb2e8f9f7 356 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
<> 144:ef7eb2e8f9f7 359 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
<> 144:ef7eb2e8f9f7 360 #endif /* STM32F215xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @}
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 370 /** @addtogroup RCCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 371 * @{
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /** @addtogroup RCCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 375 * @{
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 378 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @}
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @}
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 388 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 389 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 390 /** @defgroup RCCEx_Private_Constants RCC Private Constants
<> 144:ef7eb2e8f9f7 391 * @{
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
<> 144:ef7eb2e8f9f7 395 * @brief RCC registers bit address in the alias region
<> 144:ef7eb2e8f9f7 396 * @{
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
<> 144:ef7eb2e8f9f7 399 /**
<> 144:ef7eb2e8f9f7 400 * @}
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /**
<> 144:ef7eb2e8f9f7 404 * @}
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 408 /** @defgroup RCCEx_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
<> 144:ef7eb2e8f9f7 412 * @{
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F))
<> 144:ef7eb2e8f9f7 415 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
<> 144:ef7eb2e8f9f7 416 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @}
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /**
<> 144:ef7eb2e8f9f7 422 * @}
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @}
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434 #endif
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #endif /* __STM32F2xx_HAL_RCC_EX_H */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/