mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

Users » JojoS » Code » mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_rcc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:: JojoS
Date:: Sat Sep 10 15:32:04 2016 +0000
Revision:: 147:ba84b7dc41a7
Parent:: 144:ef7eb2e8f9f7

added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f2xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.3
<>	144:ef7eb2e8f9f7	6	* @date 29-June-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F2xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F2xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f2xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F2xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup RCC
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t PLLState; /*!< The new state of the PLL.
<>	144:ef7eb2e8f9f7	68	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
<>	144:ef7eb2e8f9f7	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
<>	144:ef7eb2e8f9f7	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
<>	144:ef7eb2e8f9f7	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
<>	144:ef7eb2e8f9f7	83	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
<>	144:ef7eb2e8f9f7	84
<>	144:ef7eb2e8f9f7	85	}RCC_PLLInitTypeDef;
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	/**
<>	144:ef7eb2e8f9f7	88	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	89	*/
<>	144:ef7eb2e8f9f7	90	typedef struct
<>	144:ef7eb2e8f9f7	91	{
<>	144:ef7eb2e8f9f7	92	uint32_t OscillatorType; /*!< The oscillators to be configured.
<>	144:ef7eb2e8f9f7	93	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	uint32_t HSEState; /*!< The new state of the HSE.
<>	144:ef7eb2e8f9f7	96	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	uint32_t LSEState; /*!< The new state of the LSE.
<>	144:ef7eb2e8f9f7	99	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	uint32_t HSIState; /*!< The new state of the HSI.
<>	144:ef7eb2e8f9f7	102	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	105	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<>	144:ef7eb2e8f9f7	106
<>	144:ef7eb2e8f9f7	107	uint32_t LSIState; /*!< The new state of the LSI.
<>	144:ef7eb2e8f9f7	108	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
<>	144:ef7eb2e8f9f7	111	}RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/**
<>	144:ef7eb2e8f9f7	114	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	115	*/
<>	144:ef7eb2e8f9f7	116	typedef struct
<>	144:ef7eb2e8f9f7	117	{
<>	144:ef7eb2e8f9f7	118	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	119	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	122	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	123
<>	144:ef7eb2e8f9f7	124	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	125	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	128	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	131	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	}RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/**
<>	144:ef7eb2e8f9f7	136	* @}
<>	144:ef7eb2e8f9f7	137	*/
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	140	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	141	* @{
<>	144:ef7eb2e8f9f7	142	*/
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	145	* @{
<>	144:ef7eb2e8f9f7	146	*/
<>	144:ef7eb2e8f9f7	147	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	148	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	149	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	150	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	151	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	152	/**
<>	144:ef7eb2e8f9f7	153	* @}
<>	144:ef7eb2e8f9f7	154	*/
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/** @defgroup RCC_HSE_Config HSE Config
<>	144:ef7eb2e8f9f7	157	* @{
<>	144:ef7eb2e8f9f7	158	*/
<>	144:ef7eb2e8f9f7	159	#define RCC_HSE_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	160	#define RCC_HSE_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	161	#define RCC_HSE_BYPASS ((uint8_t)0x05U)
<>	144:ef7eb2e8f9f7	162	/**
<>	144:ef7eb2e8f9f7	163	* @}
<>	144:ef7eb2e8f9f7	164	*/
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	/** @defgroup RCC_LSE_Config LSE Config
<>	144:ef7eb2e8f9f7	167	* @{
<>	144:ef7eb2e8f9f7	168	*/
<>	144:ef7eb2e8f9f7	169	#define RCC_LSE_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	170	#define RCC_LSE_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	171	#define RCC_LSE_BYPASS ((uint8_t)0x05U)
<>	144:ef7eb2e8f9f7	172	/**
<>	144:ef7eb2e8f9f7	173	* @}
<>	144:ef7eb2e8f9f7	174	*/
<>	144:ef7eb2e8f9f7	175
<>	144:ef7eb2e8f9f7	176	/** @defgroup RCC_HSI_Config HSI Config
<>	144:ef7eb2e8f9f7	177	* @{
<>	144:ef7eb2e8f9f7	178	*/
<>	144:ef7eb2e8f9f7	179	#define RCC_HSI_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	180	#define RCC_HSI_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	183	/**
<>	144:ef7eb2e8f9f7	184	* @}
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	/** @defgroup RCC_LSI_Config LSI Config
<>	144:ef7eb2e8f9f7	188	* @{
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190	#define RCC_LSI_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	191	#define RCC_LSI_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	192	/**
<>	144:ef7eb2e8f9f7	193	* @}
<>	144:ef7eb2e8f9f7	194	*/
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	/** @defgroup RCC_PLL_Config PLL Config
<>	144:ef7eb2e8f9f7	197	* @{
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199	#define RCC_PLL_NONE ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	200	#define RCC_PLL_OFF ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	201	#define RCC_PLL_ON ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	202	/**
<>	144:ef7eb2e8f9f7	203	* @}
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
<>	144:ef7eb2e8f9f7	207	* @{
<>	144:ef7eb2e8f9f7	208	*/
<>	144:ef7eb2e8f9f7	209	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	210	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	211	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
<>	144:ef7eb2e8f9f7	212	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @}
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	218	* @{
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
<>	144:ef7eb2e8f9f7	221	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
<>	144:ef7eb2e8f9f7	222	/**
<>	144:ef7eb2e8f9f7	223	* @}
<>	144:ef7eb2e8f9f7	224	*/
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226	/** @defgroup RCC_System_Clock_Type System Clock Type
<>	144:ef7eb2e8f9f7	227	* @{
<>	144:ef7eb2e8f9f7	228	*/
<>	144:ef7eb2e8f9f7	229	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	230	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	231	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	232	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	233	/**
<>	144:ef7eb2e8f9f7	234	* @}
<>	144:ef7eb2e8f9f7	235	*/
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/** @defgroup RCC_System_Clock_Source System Clock Source
<>	144:ef7eb2e8f9f7	238	* @{
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
<>	144:ef7eb2e8f9f7	241	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
<>	144:ef7eb2e8f9f7	242	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @}
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<>	144:ef7eb2e8f9f7	248	* @{
<>	144:ef7eb2e8f9f7	249	*/
<>	144:ef7eb2e8f9f7	250	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	251	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	252	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	253	/**
<>	144:ef7eb2e8f9f7	254	* @}
<>	144:ef7eb2e8f9f7	255	*/
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<>	144:ef7eb2e8f9f7	258	* @{
<>	144:ef7eb2e8f9f7	259	*/
<>	144:ef7eb2e8f9f7	260	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
<>	144:ef7eb2e8f9f7	261	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
<>	144:ef7eb2e8f9f7	262	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
<>	144:ef7eb2e8f9f7	263	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
<>	144:ef7eb2e8f9f7	264	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
<>	144:ef7eb2e8f9f7	265	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
<>	144:ef7eb2e8f9f7	266	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
<>	144:ef7eb2e8f9f7	267	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
<>	144:ef7eb2e8f9f7	268	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
<>	144:ef7eb2e8f9f7	269	/**
<>	144:ef7eb2e8f9f7	270	* @}
<>	144:ef7eb2e8f9f7	271	*/
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
<>	144:ef7eb2e8f9f7	274	* @{
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
<>	144:ef7eb2e8f9f7	277	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
<>	144:ef7eb2e8f9f7	278	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
<>	144:ef7eb2e8f9f7	279	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
<>	144:ef7eb2e8f9f7	280	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
<>	144:ef7eb2e8f9f7	281	/**
<>	144:ef7eb2e8f9f7	282	* @}
<>	144:ef7eb2e8f9f7	283	*/
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
<>	144:ef7eb2e8f9f7	286	* @{
<>	144:ef7eb2e8f9f7	287	*/
<>	144:ef7eb2e8f9f7	288	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	289	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	290	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
<>	144:ef7eb2e8f9f7	291	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
<>	144:ef7eb2e8f9f7	292	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
<>	144:ef7eb2e8f9f7	293	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
<>	144:ef7eb2e8f9f7	294	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
<>	144:ef7eb2e8f9f7	295	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
<>	144:ef7eb2e8f9f7	296	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
<>	144:ef7eb2e8f9f7	297	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
<>	144:ef7eb2e8f9f7	298	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
<>	144:ef7eb2e8f9f7	299	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
<>	144:ef7eb2e8f9f7	300	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
<>	144:ef7eb2e8f9f7	301	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
<>	144:ef7eb2e8f9f7	302	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
<>	144:ef7eb2e8f9f7	303	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
<>	144:ef7eb2e8f9f7	304	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
<>	144:ef7eb2e8f9f7	305	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
<>	144:ef7eb2e8f9f7	306	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
<>	144:ef7eb2e8f9f7	307	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
<>	144:ef7eb2e8f9f7	308	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
<>	144:ef7eb2e8f9f7	309	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
<>	144:ef7eb2e8f9f7	310	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
<>	144:ef7eb2e8f9f7	311	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
<>	144:ef7eb2e8f9f7	312	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
<>	144:ef7eb2e8f9f7	313	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
<>	144:ef7eb2e8f9f7	314	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
<>	144:ef7eb2e8f9f7	315	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
<>	144:ef7eb2e8f9f7	316	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
<>	144:ef7eb2e8f9f7	317	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
<>	144:ef7eb2e8f9f7	318	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
<>	144:ef7eb2e8f9f7	319	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @}
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/** @defgroup RCC_MCO_Index MCO Index
<>	144:ef7eb2e8f9f7	325	* @{
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327	#define RCC_MCO1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	328	#define RCC_MCO2 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	329	/**
<>	144:ef7eb2e8f9f7	330	* @}
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
<>	144:ef7eb2e8f9f7	334	* @{
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	337	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
<>	144:ef7eb2e8f9f7	338	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
<>	144:ef7eb2e8f9f7	339	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
<>	144:ef7eb2e8f9f7	340	/**
<>	144:ef7eb2e8f9f7	341	* @}
<>	144:ef7eb2e8f9f7	342	*/
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
<>	144:ef7eb2e8f9f7	345	* @{
<>	144:ef7eb2e8f9f7	346	*/
<>	144:ef7eb2e8f9f7	347	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	348	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
<>	144:ef7eb2e8f9f7	349	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
<>	144:ef7eb2e8f9f7	350	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
<>	144:ef7eb2e8f9f7	351	/**
<>	144:ef7eb2e8f9f7	352	* @}
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
<>	144:ef7eb2e8f9f7	356	* @{
<>	144:ef7eb2e8f9f7	357	*/
<>	144:ef7eb2e8f9f7	358	#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	359	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
<>	144:ef7eb2e8f9f7	360	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	361	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	362	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
<>	144:ef7eb2e8f9f7	363	/**
<>	144:ef7eb2e8f9f7	364	* @}
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366
<>	144:ef7eb2e8f9f7	367	/** @defgroup RCC_Interrupt Interrupts
<>	144:ef7eb2e8f9f7	368	* @{
<>	144:ef7eb2e8f9f7	369	*/
<>	144:ef7eb2e8f9f7	370	#define RCC_IT_LSIRDY ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	371	#define RCC_IT_LSERDY ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	372	#define RCC_IT_HSIRDY ((uint8_t)0x04U)
<>	144:ef7eb2e8f9f7	373	#define RCC_IT_HSERDY ((uint8_t)0x08U)
<>	144:ef7eb2e8f9f7	374	#define RCC_IT_PLLRDY ((uint8_t)0x10U)
<>	144:ef7eb2e8f9f7	375	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
<>	144:ef7eb2e8f9f7	376	#define RCC_IT_CSS ((uint8_t)0x80U)
<>	144:ef7eb2e8f9f7	377	/**
<>	144:ef7eb2e8f9f7	378	* @}
<>	144:ef7eb2e8f9f7	379	*/
<>	144:ef7eb2e8f9f7	380
<>	144:ef7eb2e8f9f7	381	/** @defgroup RCC_Flag Flags
<>	144:ef7eb2e8f9f7	382	* Elements values convention: 0XXYYYYYb
<>	144:ef7eb2e8f9f7	383	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	384	* - 0XX : Register index
<>	144:ef7eb2e8f9f7	385	* - 01: CR register
<>	144:ef7eb2e8f9f7	386	* - 10: BDCR register
<>	144:ef7eb2e8f9f7	387	* - 11: CSR register
<>	144:ef7eb2e8f9f7	388	* @{
<>	144:ef7eb2e8f9f7	389	*/
<>	144:ef7eb2e8f9f7	390	/* Flags in the CR register */
<>	144:ef7eb2e8f9f7	391	#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
<>	144:ef7eb2e8f9f7	392	#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
<>	144:ef7eb2e8f9f7	393	#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
<>	144:ef7eb2e8f9f7	394	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/* Flags in the BDCR register */
<>	144:ef7eb2e8f9f7	397	#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399	/* Flags in the CSR register */
<>	144:ef7eb2e8f9f7	400	#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
<>	144:ef7eb2e8f9f7	401	#define RCC_FLAG_BORRST ((uint8_t)0x79U)
<>	144:ef7eb2e8f9f7	402	#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
<>	144:ef7eb2e8f9f7	403	#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
<>	144:ef7eb2e8f9f7	404	#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
<>	144:ef7eb2e8f9f7	405	#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
<>	144:ef7eb2e8f9f7	406	#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
<>	144:ef7eb2e8f9f7	407	#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
<>	144:ef7eb2e8f9f7	408	/**
<>	144:ef7eb2e8f9f7	409	* @}
<>	144:ef7eb2e8f9f7	410	*/
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/**
<>	144:ef7eb2e8f9f7	413	* @}
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	417	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	418	* @{
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	422	* @brief Enable or disable the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	423	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	424	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	425	* using it.
<>	144:ef7eb2e8f9f7	426	* @{
<>	144:ef7eb2e8f9f7	427	*/
<>	144:ef7eb2e8f9f7	428	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	429	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	430	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	431	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	432	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	433	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	434	} while(0)
<>	144:ef7eb2e8f9f7	435	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	436	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	437	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	438	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	439	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	440	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	441	} while(0)
<>	144:ef7eb2e8f9f7	442	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	443	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	444	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	445	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	446	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	447	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	448	} while(0)
<>	144:ef7eb2e8f9f7	449	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	450	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	451	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<>	144:ef7eb2e8f9f7	452	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	453	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<>	144:ef7eb2e8f9f7	454	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	455	} while(0)
<>	144:ef7eb2e8f9f7	456	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	457	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	458	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<>	144:ef7eb2e8f9f7	459	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	460	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<>	144:ef7eb2e8f9f7	461	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	462	} while(0)
<>	144:ef7eb2e8f9f7	463	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	464	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	465	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<>	144:ef7eb2e8f9f7	466	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	467	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<>	144:ef7eb2e8f9f7	468	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	469	} while(0)
<>	144:ef7eb2e8f9f7	470	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	471	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	472	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<>	144:ef7eb2e8f9f7	473	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	474	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<>	144:ef7eb2e8f9f7	475	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	476	} while(0)
<>	144:ef7eb2e8f9f7	477	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	478	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	479	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	480	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	481	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	482	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	483	} while(0)
<>	144:ef7eb2e8f9f7	484	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	485	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	486	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<>	144:ef7eb2e8f9f7	487	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	488	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<>	144:ef7eb2e8f9f7	489	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	490	} while(0)
<>	144:ef7eb2e8f9f7	491	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	492	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	493	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
<>	144:ef7eb2e8f9f7	494	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	495	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
<>	144:ef7eb2e8f9f7	496	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	497	} while(0)
<>	144:ef7eb2e8f9f7	498	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	499	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	500	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<>	144:ef7eb2e8f9f7	501	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	502	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<>	144:ef7eb2e8f9f7	503	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	504	} while(0)
<>	144:ef7eb2e8f9f7	505	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	506	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	507	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	508	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	509	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	510	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	511	} while(0)
<>	144:ef7eb2e8f9f7	512	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	513	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	514	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	515	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	516	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	517	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	518	} while(0)
<>	144:ef7eb2e8f9f7	519	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	520	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	521	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<>	144:ef7eb2e8f9f7	522	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	523	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<>	144:ef7eb2e8f9f7	524	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	525	} while(0)
<>	144:ef7eb2e8f9f7	526	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	527	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	528	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<>	144:ef7eb2e8f9f7	529	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	530	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<>	144:ef7eb2e8f9f7	531	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	532	} while(0)
<>	144:ef7eb2e8f9f7	533	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
<>	144:ef7eb2e8f9f7	534	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
<>	144:ef7eb2e8f9f7	535	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
<>	144:ef7eb2e8f9f7	536	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
<>	144:ef7eb2e8f9f7	537	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
<>	144:ef7eb2e8f9f7	538	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
<>	144:ef7eb2e8f9f7	539	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
<>	144:ef7eb2e8f9f7	540	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
<>	144:ef7eb2e8f9f7	541	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
<>	144:ef7eb2e8f9f7	542	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
<>	144:ef7eb2e8f9f7	543	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
<>	144:ef7eb2e8f9f7	544	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
<>	144:ef7eb2e8f9f7	545	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
<>	144:ef7eb2e8f9f7	546	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
<>	144:ef7eb2e8f9f7	547	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
<>	144:ef7eb2e8f9f7	548	/**
<>	144:ef7eb2e8f9f7	549	* @}
<>	144:ef7eb2e8f9f7	550	*/
<>	144:ef7eb2e8f9f7	551	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	552	* @brief Get the enable or disable status of the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	553	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	554	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	555	* using it.
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
<>	144:ef7eb2e8f9f7	559	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
<>	144:ef7eb2e8f9f7	560	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
<>	144:ef7eb2e8f9f7	561	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET)
<>	144:ef7eb2e8f9f7	562	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET)
<>	144:ef7eb2e8f9f7	563	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET)
<>	144:ef7eb2e8f9f7	564	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET)
<>	144:ef7eb2e8f9f7	565	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
<>	144:ef7eb2e8f9f7	566	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET)
<>	144:ef7eb2e8f9f7	567	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET)
<>	144:ef7eb2e8f9f7	568	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET)
<>	144:ef7eb2e8f9f7	569	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
<>	144:ef7eb2e8f9f7	570	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
<>	144:ef7eb2e8f9f7	571	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET)
<>	144:ef7eb2e8f9f7	572	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
<>	144:ef7eb2e8f9f7	575	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
<>	144:ef7eb2e8f9f7	576	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
<>	144:ef7eb2e8f9f7	577	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET)
<>	144:ef7eb2e8f9f7	578	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET)
<>	144:ef7eb2e8f9f7	579	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET)
<>	144:ef7eb2e8f9f7	580	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET)
<>	144:ef7eb2e8f9f7	581	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
<>	144:ef7eb2e8f9f7	582	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET)
<>	144:ef7eb2e8f9f7	583	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET)
<>	144:ef7eb2e8f9f7	584	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET)
<>	144:ef7eb2e8f9f7	585	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
<>	144:ef7eb2e8f9f7	586	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
<>	144:ef7eb2e8f9f7	587	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET)
<>	144:ef7eb2e8f9f7	588	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
<>	144:ef7eb2e8f9f7	589	/**
<>	144:ef7eb2e8f9f7	590	* @}
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	594	* @brief Enable or disable the AHB2 peripheral clock.
<>	144:ef7eb2e8f9f7	595	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	596	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	597	* using it.
<>	144:ef7eb2e8f9f7	598	* @{
<>	144:ef7eb2e8f9f7	599	*/
<>	144:ef7eb2e8f9f7	600	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
<>	144:ef7eb2e8f9f7	601	__HAL_RCC_SYSCFG_CLK_ENABLE();\
<>	144:ef7eb2e8f9f7	602	}while(0)
<>	144:ef7eb2e8f9f7	603	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	604	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	605	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<>	144:ef7eb2e8f9f7	606	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	607	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<>	144:ef7eb2e8f9f7	608	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	609	} while(0)
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
<>	144:ef7eb2e8f9f7	612	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
<>	144:ef7eb2e8f9f7	613	/**
<>	144:ef7eb2e8f9f7	614	* @}
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616
<>	144:ef7eb2e8f9f7	617	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	618	* @brief Get the enable or disable status of the AHB2 peripheral clock.
<>	144:ef7eb2e8f9f7	619	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	620	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	621	* using it.
<>	144:ef7eb2e8f9f7	622	* @{
<>	144:ef7eb2e8f9f7	623	*/
<>	144:ef7eb2e8f9f7	624	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
<>	144:ef7eb2e8f9f7	625	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
<>	144:ef7eb2e8f9f7	628	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @}
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	634	* @brief Enables or disables the AHB3 peripheral clock.
<>	144:ef7eb2e8f9f7	635	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	636	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	637	* using it.
<>	144:ef7eb2e8f9f7	638	* @{
<>	144:ef7eb2e8f9f7	639	*/
<>	144:ef7eb2e8f9f7	640	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	641	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	642	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
<>	144:ef7eb2e8f9f7	643	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	644	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
<>	144:ef7eb2e8f9f7	645	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	646	} while(0)
<>	144:ef7eb2e8f9f7	647	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
<>	144:ef7eb2e8f9f7	648	/**
<>	144:ef7eb2e8f9f7	649	* @}
<>	144:ef7eb2e8f9f7	650	*/
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	653	* @brief Get the enable or disable status of the AHB3 peripheral clock.
<>	144:ef7eb2e8f9f7	654	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	655	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	656	* using it.
<>	144:ef7eb2e8f9f7	657	* @{
<>	144:ef7eb2e8f9f7	658	*/
<>	144:ef7eb2e8f9f7	659	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
<>	144:ef7eb2e8f9f7	660	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
<>	144:ef7eb2e8f9f7	661	/**
<>	144:ef7eb2e8f9f7	662	* @}
<>	144:ef7eb2e8f9f7	663	*/
<>	144:ef7eb2e8f9f7	664
<>	144:ef7eb2e8f9f7	665	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	666	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	667	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	668	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	669	* using it.
<>	144:ef7eb2e8f9f7	670	* @{
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	673	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	675	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	677	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	678	} while(0)
<>	144:ef7eb2e8f9f7	679	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	680	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	682	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	684	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	685	} while(0)
<>	144:ef7eb2e8f9f7	686	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	687	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<>	144:ef7eb2e8f9f7	689	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<>	144:ef7eb2e8f9f7	691	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	692	} while(0)
<>	144:ef7eb2e8f9f7	693	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	694	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	696	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	698	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	699	} while(0)
<>	144:ef7eb2e8f9f7	700	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	701	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<>	144:ef7eb2e8f9f7	703	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<>	144:ef7eb2e8f9f7	705	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	706	} while(0)
<>	144:ef7eb2e8f9f7	707	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	708	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<>	144:ef7eb2e8f9f7	710	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<>	144:ef7eb2e8f9f7	712	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	713	} while(0)
<>	144:ef7eb2e8f9f7	714	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	715	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<>	144:ef7eb2e8f9f7	717	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<>	144:ef7eb2e8f9f7	719	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	720	} while(0)
<>	144:ef7eb2e8f9f7	721	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	722	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<>	144:ef7eb2e8f9f7	724	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<>	144:ef7eb2e8f9f7	726	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	727	} while(0)
<>	144:ef7eb2e8f9f7	728	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	729	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<>	144:ef7eb2e8f9f7	731	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<>	144:ef7eb2e8f9f7	733	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	734	} while(0)
<>	144:ef7eb2e8f9f7	735	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	736	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	738	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	740	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	741	} while(0)
<>	144:ef7eb2e8f9f7	742	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	743	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	745	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	747	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	748	} while(0)
<>	144:ef7eb2e8f9f7	749	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	750	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	751	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<>	144:ef7eb2e8f9f7	752	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	753	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<>	144:ef7eb2e8f9f7	754	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	755	} while(0)
<>	144:ef7eb2e8f9f7	756	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	757	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	758	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	759	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	760	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	761	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	762	} while(0)
<>	144:ef7eb2e8f9f7	763	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	764	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	765	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<>	144:ef7eb2e8f9f7	766	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	767	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<>	144:ef7eb2e8f9f7	768	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	769	} while(0)
<>	144:ef7eb2e8f9f7	770	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	771	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	772	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<>	144:ef7eb2e8f9f7	773	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	774	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<>	144:ef7eb2e8f9f7	775	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	776	} while(0)
<>	144:ef7eb2e8f9f7	777	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	778	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	779	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<>	144:ef7eb2e8f9f7	780	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	781	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<>	144:ef7eb2e8f9f7	782	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	783	} while(0)
<>	144:ef7eb2e8f9f7	784	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	785	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	786	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	787	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	788	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	789	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	790	} while(0)
<>	144:ef7eb2e8f9f7	791	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	792	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	793	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	794	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	795	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	796	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	797	} while(0)
<>	144:ef7eb2e8f9f7	798	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	799	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	800	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<>	144:ef7eb2e8f9f7	801	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	802	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<>	144:ef7eb2e8f9f7	803	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	804	} while(0)
<>	144:ef7eb2e8f9f7	805	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	806	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	807	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<>	144:ef7eb2e8f9f7	808	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	809	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<>	144:ef7eb2e8f9f7	810	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	811	} while(0)
<>	144:ef7eb2e8f9f7	812	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	813	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	814	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<>	144:ef7eb2e8f9f7	815	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	816	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<>	144:ef7eb2e8f9f7	817	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	818	} while(0)
<>	144:ef7eb2e8f9f7	819	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	820	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	821	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	822	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	823	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	824	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	825	} while(0)
<>	144:ef7eb2e8f9f7	826	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	827	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	828	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<>	144:ef7eb2e8f9f7	829	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	830	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<>	144:ef7eb2e8f9f7	831	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	832	} while(0)
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<>	144:ef7eb2e8f9f7	835	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<>	144:ef7eb2e8f9f7	836	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<>	144:ef7eb2e8f9f7	837	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<>	144:ef7eb2e8f9f7	838	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<>	144:ef7eb2e8f9f7	839	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<>	144:ef7eb2e8f9f7	840	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<>	144:ef7eb2e8f9f7	841	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<>	144:ef7eb2e8f9f7	842	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<>	144:ef7eb2e8f9f7	843	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	844	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<>	144:ef7eb2e8f9f7	845	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<>	144:ef7eb2e8f9f7	846	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<>	144:ef7eb2e8f9f7	847	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<>	144:ef7eb2e8f9f7	848	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<>	144:ef7eb2e8f9f7	849	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<>	144:ef7eb2e8f9f7	850	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<>	144:ef7eb2e8f9f7	851	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<>	144:ef7eb2e8f9f7	852	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
<>	144:ef7eb2e8f9f7	853	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	854	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<>	144:ef7eb2e8f9f7	855	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<>	144:ef7eb2e8f9f7	856	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<>	144:ef7eb2e8f9f7	857	/**
<>	144:ef7eb2e8f9f7	858	* @}
<>	144:ef7eb2e8f9f7	859	*/
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	862	* @brief Get the enable or disable status of the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	863	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	864	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	865	* using it.
<>	144:ef7eb2e8f9f7	866	* @{
<>	144:ef7eb2e8f9f7	867	*/
<>	144:ef7eb2e8f9f7	868	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET)
<>	144:ef7eb2e8f9f7	869	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET)
<>	144:ef7eb2e8f9f7	870	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET)
<>	144:ef7eb2e8f9f7	871	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
<>	144:ef7eb2e8f9f7	872	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET)
<>	144:ef7eb2e8f9f7	873	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET)
<>	144:ef7eb2e8f9f7	874	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET)
<>	144:ef7eb2e8f9f7	875	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET)
<>	144:ef7eb2e8f9f7	876	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET)
<>	144:ef7eb2e8f9f7	877	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET)
<>	144:ef7eb2e8f9f7	878	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET)
<>	144:ef7eb2e8f9f7	879	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
<>	144:ef7eb2e8f9f7	880	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
<>	144:ef7eb2e8f9f7	881	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET)
<>	144:ef7eb2e8f9f7	882	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET)
<>	144:ef7eb2e8f9f7	883	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET)
<>	144:ef7eb2e8f9f7	884	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET)
<>	144:ef7eb2e8f9f7	885	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
<>	144:ef7eb2e8f9f7	886	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
<>	144:ef7eb2e8f9f7	887	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
<>	144:ef7eb2e8f9f7	888	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET)
<>	144:ef7eb2e8f9f7	889	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
<>	144:ef7eb2e8f9f7	890	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET)
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET)
<>	144:ef7eb2e8f9f7	893	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET)
<>	144:ef7eb2e8f9f7	894	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET)
<>	144:ef7eb2e8f9f7	895	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
<>	144:ef7eb2e8f9f7	896	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET)
<>	144:ef7eb2e8f9f7	897	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET)
<>	144:ef7eb2e8f9f7	898	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET)
<>	144:ef7eb2e8f9f7	899	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET)
<>	144:ef7eb2e8f9f7	900	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET)
<>	144:ef7eb2e8f9f7	901	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET)
<>	144:ef7eb2e8f9f7	902	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET)
<>	144:ef7eb2e8f9f7	903	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
<>	144:ef7eb2e8f9f7	904	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
<>	144:ef7eb2e8f9f7	905	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET)
<>	144:ef7eb2e8f9f7	906	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET)
<>	144:ef7eb2e8f9f7	907	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET)
<>	144:ef7eb2e8f9f7	908	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET)
<>	144:ef7eb2e8f9f7	909	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
<>	144:ef7eb2e8f9f7	910	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
<>	144:ef7eb2e8f9f7	911	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
<>	144:ef7eb2e8f9f7	912	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET)
<>	144:ef7eb2e8f9f7	913	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
<>	144:ef7eb2e8f9f7	914	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET)
<>	144:ef7eb2e8f9f7	915	/**
<>	144:ef7eb2e8f9f7	916	* @}
<>	144:ef7eb2e8f9f7	917	*/
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	920	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	921	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	922	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	923	* using it.
<>	144:ef7eb2e8f9f7	924	* @{
<>	144:ef7eb2e8f9f7	925	*/
<>	144:ef7eb2e8f9f7	926	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	927	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	928	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	929	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	930	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	931	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	932	} while(0)
<>	144:ef7eb2e8f9f7	933	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	934	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	935	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<>	144:ef7eb2e8f9f7	936	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	937	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<>	144:ef7eb2e8f9f7	938	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	939	} while(0)
<>	144:ef7eb2e8f9f7	940	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	941	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	942	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	943	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	944	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	945	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	946	} while(0)
<>	144:ef7eb2e8f9f7	947	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	948	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	949	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	950	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	951	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	952	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	953	} while(0)
<>	144:ef7eb2e8f9f7	954	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	955	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	956	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	957	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	958	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	959	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	960	} while(0)
<>	144:ef7eb2e8f9f7	961	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	962	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	963	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<>	144:ef7eb2e8f9f7	964	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	965	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<>	144:ef7eb2e8f9f7	966	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	967	} while(0)
<>	144:ef7eb2e8f9f7	968	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	969	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	970	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<>	144:ef7eb2e8f9f7	971	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	972	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<>	144:ef7eb2e8f9f7	973	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	974	} while(0)
<>	144:ef7eb2e8f9f7	975	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	976	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	977	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
<>	144:ef7eb2e8f9f7	978	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	979	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
<>	144:ef7eb2e8f9f7	980	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	981	} while(0)
<>	144:ef7eb2e8f9f7	982	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	983	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	984	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	985	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	986	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	987	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	988	} while(0)
<>	144:ef7eb2e8f9f7	989	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	990	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	991	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	992	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	993	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	994	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	995	} while(0)
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	998	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	999	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	1000	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1001	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	1002	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1003	} while(0)
<>	144:ef7eb2e8f9f7	1004	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1005	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	1006	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<>	144:ef7eb2e8f9f7	1007	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1008	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<>	144:ef7eb2e8f9f7	1009	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1010	} while(0)
<>	144:ef7eb2e8f9f7	1011	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1012	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	1013	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	1014	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1015	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	1016	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1017	} while(0)
<>	144:ef7eb2e8f9f7	1018	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<>	144:ef7eb2e8f9f7	1019	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
<>	144:ef7eb2e8f9f7	1020	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<>	144:ef7eb2e8f9f7	1021	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<>	144:ef7eb2e8f9f7	1022	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<>	144:ef7eb2e8f9f7	1023	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
<>	144:ef7eb2e8f9f7	1024	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
<>	144:ef7eb2e8f9f7	1025	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
<>	144:ef7eb2e8f9f7	1026	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<>	144:ef7eb2e8f9f7	1027	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	1028	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<>	144:ef7eb2e8f9f7	1029	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
<>	144:ef7eb2e8f9f7	1030	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<>	144:ef7eb2e8f9f7	1031	/**
<>	144:ef7eb2e8f9f7	1032	* @}
<>	144:ef7eb2e8f9f7	1033	*/
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	1036	* @brief Get the enable or disable status of the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	1037	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1038	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1039	* using it.
<>	144:ef7eb2e8f9f7	1040	* @{
<>	144:ef7eb2e8f9f7	1041	*/
<>	144:ef7eb2e8f9f7	1042	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
<>	144:ef7eb2e8f9f7	1043	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
<>	144:ef7eb2e8f9f7	1044	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
<>	144:ef7eb2e8f9f7	1045	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
<>	144:ef7eb2e8f9f7	1046	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
<>	144:ef7eb2e8f9f7	1047	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
<>	144:ef7eb2e8f9f7	1048	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
<>	144:ef7eb2e8f9f7	1049	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
<>	144:ef7eb2e8f9f7	1050	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
<>	144:ef7eb2e8f9f7	1051	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
<>	144:ef7eb2e8f9f7	1052	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
<>	144:ef7eb2e8f9f7	1053	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
<>	144:ef7eb2e8f9f7	1054	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
<>	144:ef7eb2e8f9f7	1055
<>	144:ef7eb2e8f9f7	1056	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
<>	144:ef7eb2e8f9f7	1057	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
<>	144:ef7eb2e8f9f7	1058	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
<>	144:ef7eb2e8f9f7	1059	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
<>	144:ef7eb2e8f9f7	1060	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
<>	144:ef7eb2e8f9f7	1061	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
<>	144:ef7eb2e8f9f7	1062	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
<>	144:ef7eb2e8f9f7	1063	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
<>	144:ef7eb2e8f9f7	1064	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
<>	144:ef7eb2e8f9f7	1065	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
<>	144:ef7eb2e8f9f7	1066	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
<>	144:ef7eb2e8f9f7	1067	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
<>	144:ef7eb2e8f9f7	1068	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)
<>	144:ef7eb2e8f9f7	1069	/**
<>	144:ef7eb2e8f9f7	1070	* @}
<>	144:ef7eb2e8f9f7	1071	*/
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
<>	144:ef7eb2e8f9f7	1074	* @brief Force or release AHB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1075	* @{
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1078	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	1079	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	1080	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	1081	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
<>	144:ef7eb2e8f9f7	1082	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
<>	144:ef7eb2e8f9f7	1083	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
<>	144:ef7eb2e8f9f7	1084	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
<>	144:ef7eb2e8f9f7	1085	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	1086	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
<>	144:ef7eb2e8f9f7	1087	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
<>	144:ef7eb2e8f9f7	1088	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	1089	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	1090	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
<>	144:ef7eb2e8f9f7	1091	#define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHSULPIRST))
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1094	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	1095	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	1096	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	1097	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
<>	144:ef7eb2e8f9f7	1098	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
<>	144:ef7eb2e8f9f7	1099	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
<>	144:ef7eb2e8f9f7	1100	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
<>	144:ef7eb2e8f9f7	1101	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	1102	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
<>	144:ef7eb2e8f9f7	1103	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
<>	144:ef7eb2e8f9f7	1104	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	1105	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	1106	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
<>	144:ef7eb2e8f9f7	1107	#define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
<>	144:ef7eb2e8f9f7	1108	/**
<>	144:ef7eb2e8f9f7	1109	* @}
<>	144:ef7eb2e8f9f7	1110	*/
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
<>	144:ef7eb2e8f9f7	1113	* @brief Force or release AHB2 peripheral reset.
<>	144:ef7eb2e8f9f7	1114	* @{
<>	144:ef7eb2e8f9f7	1115	*/
<>	144:ef7eb2e8f9f7	1116	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1117	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
<>	144:ef7eb2e8f9f7	1118	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1121	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
<>	144:ef7eb2e8f9f7	1122	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
<>	144:ef7eb2e8f9f7	1123	/**
<>	144:ef7eb2e8f9f7	1124	* @}
<>	144:ef7eb2e8f9f7	1125	*/
<>	144:ef7eb2e8f9f7	1126
<>	144:ef7eb2e8f9f7	1127	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
<>	144:ef7eb2e8f9f7	1128	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1129	* @{
<>	144:ef7eb2e8f9f7	1130	*/
<>	144:ef7eb2e8f9f7	1131	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1132	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	1133	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	1134	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
<>	144:ef7eb2e8f9f7	1135	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	1136	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
<>	144:ef7eb2e8f9f7	1137	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
<>	144:ef7eb2e8f9f7	1138	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
<>	144:ef7eb2e8f9f7	1139	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
<>	144:ef7eb2e8f9f7	1140	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
<>	144:ef7eb2e8f9f7	1141	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	1142	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	1143	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
<>	144:ef7eb2e8f9f7	1144	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	1145	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
<>	144:ef7eb2e8f9f7	1146	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
<>	144:ef7eb2e8f9f7	1147	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
<>	144:ef7eb2e8f9f7	1148	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	1149	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	1150	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
<>	144:ef7eb2e8f9f7	1151	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
<>	144:ef7eb2e8f9f7	1152	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
<>	144:ef7eb2e8f9f7	1153	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	1154	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1157	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	1158	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	1159	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<>	144:ef7eb2e8f9f7	1160	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	1161	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<>	144:ef7eb2e8f9f7	1162	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<>	144:ef7eb2e8f9f7	1163	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
<>	144:ef7eb2e8f9f7	1164	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
<>	144:ef7eb2e8f9f7	1165	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<>	144:ef7eb2e8f9f7	1166	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	1167	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	1168	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<>	144:ef7eb2e8f9f7	1169	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	1170	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<>	144:ef7eb2e8f9f7	1171	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<>	144:ef7eb2e8f9f7	1172	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<>	144:ef7eb2e8f9f7	1173	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	1174	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	1175	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
<>	144:ef7eb2e8f9f7	1176	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<>	144:ef7eb2e8f9f7	1177	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
<>	144:ef7eb2e8f9f7	1178	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	1179	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<>	144:ef7eb2e8f9f7	1180	/**
<>	144:ef7eb2e8f9f7	1181	* @}
<>	144:ef7eb2e8f9f7	1182	*/
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
<>	144:ef7eb2e8f9f7	1185	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	1186	* @{
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1189	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	1190	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
<>	144:ef7eb2e8f9f7	1191	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	1192	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	1193	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	1194	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
<>	144:ef7eb2e8f9f7	1195	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	1196	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	1197	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	1198	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
<>	144:ef7eb2e8f9f7	1199	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1202	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	1203	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<>	144:ef7eb2e8f9f7	1204	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	1205	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	1206	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	1207	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
<>	144:ef7eb2e8f9f7	1208	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	1209	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	1210	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	1211	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
<>	144:ef7eb2e8f9f7	1212	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	1213	/**
<>	144:ef7eb2e8f9f7	1214	* @}
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
<>	144:ef7eb2e8f9f7	1218	* @brief Force or release AHB3 peripheral reset.
<>	144:ef7eb2e8f9f7	1219	* @{
<>	144:ef7eb2e8f9f7	1220	*/
<>	144:ef7eb2e8f9f7	1221	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1222	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1225	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
<>	144:ef7eb2e8f9f7	1226	/**
<>	144:ef7eb2e8f9f7	1227	* @}
<>	144:ef7eb2e8f9f7	1228	*/
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	1231	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1233	* power consumption.
<>	144:ef7eb2e8f9f7	1234	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1236	* @{
<>	144:ef7eb2e8f9f7	1237	*/
<>	144:ef7eb2e8f9f7	1238	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	1239	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	1240	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	1241	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
<>	144:ef7eb2e8f9f7	1242	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
<>	144:ef7eb2e8f9f7	1243	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
<>	144:ef7eb2e8f9f7	1244	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
<>	144:ef7eb2e8f9f7	1245	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	1246	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
<>	144:ef7eb2e8f9f7	1247	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
<>	144:ef7eb2e8f9f7	1248	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
<>	144:ef7eb2e8f9f7	1249	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
<>	144:ef7eb2e8f9f7	1250	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
<>	144:ef7eb2e8f9f7	1251	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
<>	144:ef7eb2e8f9f7	1252	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	1253	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	1254	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
<>	144:ef7eb2e8f9f7	1255	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	1258	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	1259	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	1260	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
<>	144:ef7eb2e8f9f7	1261	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
<>	144:ef7eb2e8f9f7	1262	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
<>	144:ef7eb2e8f9f7	1263	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
<>	144:ef7eb2e8f9f7	1264	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	1265	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
<>	144:ef7eb2e8f9f7	1266	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
<>	144:ef7eb2e8f9f7	1267	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
<>	144:ef7eb2e8f9f7	1268	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
<>	144:ef7eb2e8f9f7	1269	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
<>	144:ef7eb2e8f9f7	1270	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
<>	144:ef7eb2e8f9f7	1271	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	1272	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	1273	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
<>	144:ef7eb2e8f9f7	1274	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
<>	144:ef7eb2e8f9f7	1275	/**
<>	144:ef7eb2e8f9f7	1276	* @}
<>	144:ef7eb2e8f9f7	1277	*/
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	1280	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1281	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1282	* power consumption.
<>	144:ef7eb2e8f9f7	1283	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1284	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1285	* @{
<>	144:ef7eb2e8f9f7	1286	*/
<>	144:ef7eb2e8f9f7	1287	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
<>	144:ef7eb2e8f9f7	1288	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
<>	144:ef7eb2e8f9f7	1289
<>	144:ef7eb2e8f9f7	1290	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
<>	144:ef7eb2e8f9f7	1291	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
<>	144:ef7eb2e8f9f7	1292	/**
<>	144:ef7eb2e8f9f7	1293	* @}
<>	144:ef7eb2e8f9f7	1294	*/
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	/** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	1297	* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1298	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1299	* power consumption.
<>	144:ef7eb2e8f9f7	1300	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1301	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1302	* @{
<>	144:ef7eb2e8f9f7	1303	*/
<>	144:ef7eb2e8f9f7	1304	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
<>	144:ef7eb2e8f9f7	1305	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
<>	144:ef7eb2e8f9f7	1306	/**
<>	144:ef7eb2e8f9f7	1307	* @}
<>	144:ef7eb2e8f9f7	1308	*/
<>	144:ef7eb2e8f9f7	1309
<>	144:ef7eb2e8f9f7	1310	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	1311	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1312	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1313	* power consumption.
<>	144:ef7eb2e8f9f7	1314	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1315	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1316	* @{
<>	144:ef7eb2e8f9f7	1317	*/
<>	144:ef7eb2e8f9f7	1318	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
<>	144:ef7eb2e8f9f7	1319	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
<>	144:ef7eb2e8f9f7	1320	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
<>	144:ef7eb2e8f9f7	1321	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	1322	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
<>	144:ef7eb2e8f9f7	1323	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
<>	144:ef7eb2e8f9f7	1324	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
<>	144:ef7eb2e8f9f7	1325	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
<>	144:ef7eb2e8f9f7	1326	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
<>	144:ef7eb2e8f9f7	1327	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	1328	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	1329	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
<>	144:ef7eb2e8f9f7	1330	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	1331	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
<>	144:ef7eb2e8f9f7	1332	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
<>	144:ef7eb2e8f9f7	1333	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
<>	144:ef7eb2e8f9f7	1334	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	1335	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	1336	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
<>	144:ef7eb2e8f9f7	1337	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	1338	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
<>	144:ef7eb2e8f9f7	1339	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
<>	144:ef7eb2e8f9f7	1340	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
<>	144:ef7eb2e8f9f7	1341	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
<>	144:ef7eb2e8f9f7	1342	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
<>	144:ef7eb2e8f9f7	1343	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
<>	144:ef7eb2e8f9f7	1344	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	1345	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
<>	144:ef7eb2e8f9f7	1346	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
<>	144:ef7eb2e8f9f7	1347	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
<>	144:ef7eb2e8f9f7	1348	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
<>	144:ef7eb2e8f9f7	1349	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
<>	144:ef7eb2e8f9f7	1350	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	1351	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	1352	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
<>	144:ef7eb2e8f9f7	1353	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	1354	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
<>	144:ef7eb2e8f9f7	1355	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
<>	144:ef7eb2e8f9f7	1356	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
<>	144:ef7eb2e8f9f7	1357	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	1358	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	1359	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
<>	144:ef7eb2e8f9f7	1360	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	1361	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
<>	144:ef7eb2e8f9f7	1362	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
<>	144:ef7eb2e8f9f7	1363	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
<>	144:ef7eb2e8f9f7	1364	/**
<>	144:ef7eb2e8f9f7	1365	* @}
<>	144:ef7eb2e8f9f7	1366	*/
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	1369	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1370	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1371	* power consumption.
<>	144:ef7eb2e8f9f7	1372	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1373	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1374	* @{
<>	144:ef7eb2e8f9f7	1375	*/
<>	144:ef7eb2e8f9f7	1376	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	1377	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	1378	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	1379	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	1380	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
<>	144:ef7eb2e8f9f7	1381	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	1382	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	1383	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
<>	144:ef7eb2e8f9f7	1384	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	1385	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
<>	144:ef7eb2e8f9f7	1386	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	1387	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
<>	144:ef7eb2e8f9f7	1388	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	1391	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	1392	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	1393	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	1394	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
<>	144:ef7eb2e8f9f7	1395	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	1396	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	1397	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
<>	144:ef7eb2e8f9f7	1398	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	1399	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
<>	144:ef7eb2e8f9f7	1400	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	1401	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
<>	144:ef7eb2e8f9f7	1402	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
<>	144:ef7eb2e8f9f7	1403	/**
<>	144:ef7eb2e8f9f7	1404	* @}
<>	144:ef7eb2e8f9f7	1405	*/
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/** @defgroup RCC_HSI_Configuration HSI Configuration
<>	144:ef7eb2e8f9f7	1408	* @{
<>	144:ef7eb2e8f9f7	1409	*/
<>	144:ef7eb2e8f9f7	1410
<>	144:ef7eb2e8f9f7	1411	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	1412	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1413	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	1414	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	1415	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	1416	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	1417	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	1418	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	1419	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	1420	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	1421	* system clock source.
<>	144:ef7eb2e8f9f7	1422	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	1423	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	1424	* clock cycles.
<>	144:ef7eb2e8f9f7	1425	*/
<>	144:ef7eb2e8f9f7	1426	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1427	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	1430	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	1431	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	1432	* @param __HSICalibrationValue__: specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	1433	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	1434	* This parameter must be a number between 0 and 0x1F.
<>	144:ef7eb2e8f9f7	1435	*/
<>	144:ef7eb2e8f9f7	1436	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
<>	144:ef7eb2e8f9f7	1437	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
<>	144:ef7eb2e8f9f7	1438	/**
<>	144:ef7eb2e8f9f7	1439	* @}
<>	144:ef7eb2e8f9f7	1440	*/
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442	/** @defgroup RCC_LSI_Configuration LSI Configuration
<>	144:ef7eb2e8f9f7	1443	* @{
<>	144:ef7eb2e8f9f7	1444	*/
<>	144:ef7eb2e8f9f7	1445
<>	144:ef7eb2e8f9f7	1446	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	1447	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	1448	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	1449	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	1450	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	1451	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	1452	* clock cycles.
<>	144:ef7eb2e8f9f7	1453	*/
<>	144:ef7eb2e8f9f7	1454	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1455	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1456	/**
<>	144:ef7eb2e8f9f7	1457	* @}
<>	144:ef7eb2e8f9f7	1458	*/
<>	144:ef7eb2e8f9f7	1459
<>	144:ef7eb2e8f9f7	1460	/** @defgroup RCC_HSE_Configuration HSE Configuration
<>	144:ef7eb2e8f9f7	1461	* @{
<>	144:ef7eb2e8f9f7	1462	*/
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/**
<>	144:ef7eb2e8f9f7	1465	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	1466	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	1467	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	1468	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	1469	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	1470	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	1471	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	1472	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	1473	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	1474	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1475	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	1476	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	1477	* function.
<>	144:ef7eb2e8f9f7	1478	* @param __STATE__: specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	1479	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1480	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1481	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	1482	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
<>	144:ef7eb2e8f9f7	1483	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	1484	*/
<>	144:ef7eb2e8f9f7	1485	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
<>	144:ef7eb2e8f9f7	1486	/**
<>	144:ef7eb2e8f9f7	1487	* @}
<>	144:ef7eb2e8f9f7	1488	*/
<>	144:ef7eb2e8f9f7	1489
<>	144:ef7eb2e8f9f7	1490	/** @defgroup RCC_LSE_Configuration LSE Configuration
<>	144:ef7eb2e8f9f7	1491	* @{
<>	144:ef7eb2e8f9f7	1492	*/
<>	144:ef7eb2e8f9f7	1493	/**
<>	144:ef7eb2e8f9f7	1494	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	1495	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	1496	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	1497	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	1498	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	1499	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	1500	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	1501	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	1502	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	1503	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	1504	* @param __STATE__: specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	1505	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1506	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1507	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	1508	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	1509	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	1510	*/
<>	144:ef7eb2e8f9f7	1511	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	/**
<>	144:ef7eb2e8f9f7	1514	* @}
<>	144:ef7eb2e8f9f7	1515	*/
<>	144:ef7eb2e8f9f7	1516
<>	144:ef7eb2e8f9f7	1517	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
<>	144:ef7eb2e8f9f7	1518	* @{
<>	144:ef7eb2e8f9f7	1519	*/
<>	144:ef7eb2e8f9f7	1520
<>	144:ef7eb2e8f9f7	1521	/** @brief Macros to enable or disable the RTC clock.
<>	144:ef7eb2e8f9f7	1522	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	1523	*/
<>	144:ef7eb2e8f9f7	1524	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1525	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/** @brief Macros to configure the RTC clock (RTCCLK).
<>	144:ef7eb2e8f9f7	1528	* @note As the RTC clock configuration bits are in the Backup domain and write
<>	144:ef7eb2e8f9f7	1529	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	1530	* access using the Power Backup Access macro before to configure
<>	144:ef7eb2e8f9f7	1531	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	1532	* @note Once the RTC clock is configured it can't be changed unless the
<>	144:ef7eb2e8f9f7	1533	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
<>	144:ef7eb2e8f9f7	1534	* a Power On Reset (POR).
<>	144:ef7eb2e8f9f7	1535	* @param __RTCCLKSource__: specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	1536	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1537	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
<>	144:ef7eb2e8f9f7	1538	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
<>	144:ef7eb2e8f9f7	1539	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
<>	144:ef7eb2e8f9f7	1540	* as RTC clock, where x:[2,31]
<>	144:ef7eb2e8f9f7	1541	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	1542	* work in STOP and STANDBY modes, and can be used as wake-up source.
<>	144:ef7eb2e8f9f7	1543	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	1544	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1545	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	1546	* RTC clock source).
<>	144:ef7eb2e8f9f7	1547	*/
<>	144:ef7eb2e8f9f7	1548	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
<>	144:ef7eb2e8f9f7	1549	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
<>	144:ef7eb2e8f9f7	1550
<>	144:ef7eb2e8f9f7	1551	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
<>	144:ef7eb2e8f9f7	1552	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFFU); \
<>	144:ef7eb2e8f9f7	1553	} while (0)
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	/** @brief Macros to force or release the Backup domain reset.
<>	144:ef7eb2e8f9f7	1556	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	1557	* and the RTC clock source selection in RCC_CSR register.
<>	144:ef7eb2e8f9f7	1558	* @note The BKPSRAM is not affected by this reset.
<>	144:ef7eb2e8f9f7	1559	*/
<>	144:ef7eb2e8f9f7	1560	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1561	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1562	/**
<>	144:ef7eb2e8f9f7	1563	* @}
<>	144:ef7eb2e8f9f7	1564	*/
<>	144:ef7eb2e8f9f7	1565
<>	144:ef7eb2e8f9f7	1566	/** @defgroup RCC_PLL_Configuration PLL Configuration
<>	144:ef7eb2e8f9f7	1567	* @{
<>	144:ef7eb2e8f9f7	1568	*/
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570	/** @brief Macros to enable or disable the main PLL.
<>	144:ef7eb2e8f9f7	1571	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	1572	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	1573	* be used as system clock source.
<>	144:ef7eb2e8f9f7	1574	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	1575	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1576	*/
<>	144:ef7eb2e8f9f7	1577	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1578	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1579
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	1582	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1583	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	1584	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1585	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1586	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1587	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
<>	144:ef7eb2e8f9f7	1588	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	1589	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	1590	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	1591	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	1592	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	1593	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
<>	144:ef7eb2e8f9f7	1594	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	1595	* @note You have to set the PLLN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	1596	* output frequency is between 192 and 432 MHz.
<>	144:ef7eb2e8f9f7	1597	*
<>	144:ef7eb2e8f9f7	1598	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
<>	144:ef7eb2e8f9f7	1599	* This parameter must be a number in the range {2, 4, 6, or 8}.
<>	144:ef7eb2e8f9f7	1600	*
<>	144:ef7eb2e8f9f7	1601	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
<>	144:ef7eb2e8f9f7	1602	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	1603	* @note If the USB OTG FS is used in your application, you have to set the
<>	144:ef7eb2e8f9f7	1604	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<>	144:ef7eb2e8f9f7	1605	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
<>	144:ef7eb2e8f9f7	1606	* correctly.
<>	144:ef7eb2e8f9f7	1607	*
<>	144:ef7eb2e8f9f7	1608	*/
<>	144:ef7eb2e8f9f7	1609	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
<>	144:ef7eb2e8f9f7	1610	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
<>	144:ef7eb2e8f9f7	1611	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
<>	144:ef7eb2e8f9f7	1612	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
<>	144:ef7eb2e8f9f7	1613	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
<>	144:ef7eb2e8f9f7	1614	/**
<>	144:ef7eb2e8f9f7	1615	* @}
<>	144:ef7eb2e8f9f7	1616	*/
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/** @brief Macro to configure the PLL clock source.
<>	144:ef7eb2e8f9f7	1619	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1620	* @param __PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	1621	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1622	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1623	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1624	*
<>	144:ef7eb2e8f9f7	1625	*/
<>	144:ef7eb2e8f9f7	1626	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/** @brief Macro to configure the PLL multiplication factor.
<>	144:ef7eb2e8f9f7	1629	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1630	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	1631	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	1632	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	1633	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	1634	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	1635	*
<>	144:ef7eb2e8f9f7	1636	*/
<>	144:ef7eb2e8f9f7	1637	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
<>	144:ef7eb2e8f9f7	1640	* @{
<>	144:ef7eb2e8f9f7	1641	*/
<>	144:ef7eb2e8f9f7	1642
<>	144:ef7eb2e8f9f7	1643	/** @brief Macros to enable or disable the PLLI2S.
<>	144:ef7eb2e8f9f7	1644	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1645	*/
<>	144:ef7eb2e8f9f7	1646	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1647	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1648
<>	144:ef7eb2e8f9f7	1649	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
<>	144:ef7eb2e8f9f7	1650	* @note This macro must be used only when the PLLI2S is disabled.
<>	144:ef7eb2e8f9f7	1651	* @note PLLI2S clock source is common with the main PLL (configured in
<>	144:ef7eb2e8f9f7	1652	* HAL_RCC_ClockConfig() API).
<>	144:ef7eb2e8f9f7	1653	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
<>	144:ef7eb2e8f9f7	1654	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	1655	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	1656	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
<>	144:ef7eb2e8f9f7	1657	* @param __PLLI2SR__: specifies the division factor for I2S clock
<>	144:ef7eb2e8f9f7	1658	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	1659	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
<>	144:ef7eb2e8f9f7	1660	* on the I2S clock frequency.
<>	144:ef7eb2e8f9f7	1661	*/
<>	144:ef7eb2e8f9f7	1662	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	/** @brief Macro to configure the I2S clock source (I2SCLK).
<>	144:ef7eb2e8f9f7	1665	* @note This function must be called before enabling the I2S APB clock.
<>	144:ef7eb2e8f9f7	1666	* @param __SOURCE__: specifies the I2S clock source.
<>	144:ef7eb2e8f9f7	1667	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1668	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
<>	144:ef7eb2e8f9f7	1669	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	1670	* used as I2S clock source.
<>	144:ef7eb2e8f9f7	1671	*/
<>	144:ef7eb2e8f9f7	1672	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
<>	144:ef7eb2e8f9f7	1673	/**
<>	144:ef7eb2e8f9f7	1674	* @}
<>	144:ef7eb2e8f9f7	1675	*/
<>	144:ef7eb2e8f9f7	1676
<>	144:ef7eb2e8f9f7	1677	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<>	144:ef7eb2e8f9f7	1678	* @{
<>	144:ef7eb2e8f9f7	1679	*/
<>	144:ef7eb2e8f9f7	1680
<>	144:ef7eb2e8f9f7	1681	/** @brief Macro to configure the MCO1 clock.
<>	144:ef7eb2e8f9f7	1682	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1683	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1684	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1685	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1686	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1687	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1688	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1689	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1690	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	1691	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1692	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1693	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1694	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1695	*/
<>	144:ef7eb2e8f9f7	1696	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1697	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	/** @brief Macro to configure the MCO2 clock.
<>	144:ef7eb2e8f9f7	1700	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1701	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1702	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
<>	144:ef7eb2e8f9f7	1703	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1704	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1705	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1706	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1707	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1708	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	1709	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1710	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1711	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1712	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1713	*/
<>	144:ef7eb2e8f9f7	1714	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1715	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3U)));
<>	144:ef7eb2e8f9f7	1716	/**
<>	144:ef7eb2e8f9f7	1717	* @}
<>	144:ef7eb2e8f9f7	1718	*/
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	/** @defgroup RCC_Get_Clock_source Get Clock source
<>	144:ef7eb2e8f9f7	1721	* @{
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	/**
<>	144:ef7eb2e8f9f7	1724	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	1725	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
<>	144:ef7eb2e8f9f7	1726	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1727	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1728	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1729	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	1730	*/
<>	144:ef7eb2e8f9f7	1731	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	1732
<>	144:ef7eb2e8f9f7	1733	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	1734	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	1735	* of the following:
<>	144:ef7eb2e8f9f7	1736	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
<>	144:ef7eb2e8f9f7	1737	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
<>	144:ef7eb2e8f9f7	1738	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
<>	144:ef7eb2e8f9f7	1739	*/
<>	144:ef7eb2e8f9f7	1740	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
<>	144:ef7eb2e8f9f7	1741
<>	144:ef7eb2e8f9f7	1742	/** @brief Macro to get the oscillator used as PLL clock source.
<>	144:ef7eb2e8f9f7	1743	* @retval The oscillator used as PLL clock source. The returned value can be one
<>	144:ef7eb2e8f9f7	1744	* of the following:
<>	144:ef7eb2e8f9f7	1745	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1746	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1747	*/
<>	144:ef7eb2e8f9f7	1748	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	1749	/**
<>	144:ef7eb2e8f9f7	1750	* @}
<>	144:ef7eb2e8f9f7	1751	*/
<>	144:ef7eb2e8f9f7	1752
<>	144:ef7eb2e8f9f7	1753	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1754	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1755	* @{
<>	144:ef7eb2e8f9f7	1756	*/
<>	144:ef7eb2e8f9f7	1757
<>	144:ef7eb2e8f9f7	1758	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
<>	144:ef7eb2e8f9f7	1759	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1760	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1761	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1762	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1763	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1764	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1765	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1766	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1767	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1768	*/
<>	144:ef7eb2e8f9f7	1769	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
<>	144:ef7eb2e8f9f7	1772	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1773	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1774	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1775	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1776	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1777	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1778	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1779	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1780	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1781	*/
<>	144:ef7eb2e8f9f7	1782	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
<>	144:ef7eb2e8f9f7	1785	* bits to clear the selected interrupt pending bits.
<>	144:ef7eb2e8f9f7	1786	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1787	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1788	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1789	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1790	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1791	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1792	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1793	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1794	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1795	*/
<>	144:ef7eb2e8f9f7	1796	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/** @brief Check the RCC's interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1799	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1800	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1801	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1802	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1803	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1804	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1805	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1806	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1807	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1808	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1809	*/
<>	144:ef7eb2e8f9f7	1810	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
<>	144:ef7eb2e8f9f7	1813	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
<>	144:ef7eb2e8f9f7	1814	*/
<>	144:ef7eb2e8f9f7	1815	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	1816
<>	144:ef7eb2e8f9f7	1817	/** @brief Check RCC flag is set or not.
<>	144:ef7eb2e8f9f7	1818	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	1819	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1820	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1821	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1822	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
<>	144:ef7eb2e8f9f7	1823	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
<>	144:ef7eb2e8f9f7	1824	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1825	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1826	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
<>	144:ef7eb2e8f9f7	1827	* @arg RCC_FLAG_PINRST: Pin reset.
<>	144:ef7eb2e8f9f7	1828	* @arg RCC_FLAG_PORRST: POR/PDR reset.
<>	144:ef7eb2e8f9f7	1829	* @arg RCC_FLAG_SFTRST: Software reset.
<>	144:ef7eb2e8f9f7	1830	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
<>	144:ef7eb2e8f9f7	1831	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
<>	144:ef7eb2e8f9f7	1832	* @arg RCC_FLAG_LPWRRST: Low Power reset.
<>	144:ef7eb2e8f9f7	1833	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1834	*/
<>	144:ef7eb2e8f9f7	1835	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
<>	144:ef7eb2e8f9f7	1836	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
<>	144:ef7eb2e8f9f7	1837
<>	144:ef7eb2e8f9f7	1838	#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	1839	/**
<>	144:ef7eb2e8f9f7	1840	* @}
<>	144:ef7eb2e8f9f7	1841	*/
<>	144:ef7eb2e8f9f7	1842
<>	144:ef7eb2e8f9f7	1843	/**
<>	144:ef7eb2e8f9f7	1844	* @}
<>	144:ef7eb2e8f9f7	1845	*/
<>	144:ef7eb2e8f9f7	1846
<>	144:ef7eb2e8f9f7	1847	/* Include RCC HAL Extended module */
<>	144:ef7eb2e8f9f7	1848	#include "stm32f2xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	1849	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1850	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	1851	* @{
<>	144:ef7eb2e8f9f7	1852	*/
<>	144:ef7eb2e8f9f7	1853
<>	144:ef7eb2e8f9f7	1854	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1855	* @{
<>	144:ef7eb2e8f9f7	1856	*/
<>	144:ef7eb2e8f9f7	1857	/* Initialization and de-initialization functions ******************************/
<>	144:ef7eb2e8f9f7	1858	void HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	1859	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1860	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1861	/**
<>	144:ef7eb2e8f9f7	1862	* @}
<>	144:ef7eb2e8f9f7	1863	*/
<>	144:ef7eb2e8f9f7	1864
<>	144:ef7eb2e8f9f7	1865	/** @addtogroup RCC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1866	* @{
<>	144:ef7eb2e8f9f7	1867	*/
<>	144:ef7eb2e8f9f7	1868	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1869	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1870	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	1871	void HAL_RCC_DisableCSS(void);
<>	144:ef7eb2e8f9f7	1872	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	1873	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	1874	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	1875	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	1876	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1877	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	1878
<>	144:ef7eb2e8f9f7	1879	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	1880	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	1881
<>	144:ef7eb2e8f9f7	1882	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	1883	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	/**
<>	144:ef7eb2e8f9f7	1886	* @}
<>	144:ef7eb2e8f9f7	1887	*/
<>	144:ef7eb2e8f9f7	1888
<>	144:ef7eb2e8f9f7	1889	/**
<>	144:ef7eb2e8f9f7	1890	* @}
<>	144:ef7eb2e8f9f7	1891	*/
<>	144:ef7eb2e8f9f7	1892
<>	144:ef7eb2e8f9f7	1893	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1894	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1895	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1896	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	1897	* @{
<>	144:ef7eb2e8f9f7	1898	*/
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
<>	144:ef7eb2e8f9f7	1901	* @brief RCC registers bit address in the alias region
<>	144:ef7eb2e8f9f7	1902	* @{
<>	144:ef7eb2e8f9f7	1903	*/
<>	144:ef7eb2e8f9f7	1904	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<>	144:ef7eb2e8f9f7	1905	/* --- CR Register ---*/
<>	144:ef7eb2e8f9f7	1906	/* Alias word address of HSION bit */
<>	144:ef7eb2e8f9f7	1907	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
<>	144:ef7eb2e8f9f7	1908	#define RCC_HSION_BIT_NUMBER 0x00U
<>	144:ef7eb2e8f9f7	1909	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1910	/* Alias word address of CSSON bit */
<>	144:ef7eb2e8f9f7	1911	#define RCC_CSSON_BIT_NUMBER 0x13U
<>	144:ef7eb2e8f9f7	1912	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1913	/* Alias word address of PLLON bit */
<>	144:ef7eb2e8f9f7	1914	#define RCC_PLLON_BIT_NUMBER 0x18U
<>	144:ef7eb2e8f9f7	1915	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1916	/* Alias word address of PLLI2SON bit */
<>	144:ef7eb2e8f9f7	1917	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
<>	144:ef7eb2e8f9f7	1918	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* --- CFGR Register ---*/
<>	144:ef7eb2e8f9f7	1921	/* Alias word address of I2SSRC bit */
<>	144:ef7eb2e8f9f7	1922	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
<>	144:ef7eb2e8f9f7	1923	#define RCC_I2SSRC_BIT_NUMBER 0x17U
<>	144:ef7eb2e8f9f7	1924	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1925
<>	144:ef7eb2e8f9f7	1926	/* --- BDCR Register ---*/
<>	144:ef7eb2e8f9f7	1927	/* Alias word address of RTCEN bit */
<>	144:ef7eb2e8f9f7	1928	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
<>	144:ef7eb2e8f9f7	1929	#define RCC_RTCEN_BIT_NUMBER 0x0FU
<>	144:ef7eb2e8f9f7	1930	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1931	/* Alias word address of BDRST bit */
<>	144:ef7eb2e8f9f7	1932	#define RCC_BDRST_BIT_NUMBER 0x10U
<>	144:ef7eb2e8f9f7	1933	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1934
<>	144:ef7eb2e8f9f7	1935	/* --- CSR Register ---*/
<>	144:ef7eb2e8f9f7	1936	/* Alias word address of LSION bit */
<>	144:ef7eb2e8f9f7	1937	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
<>	144:ef7eb2e8f9f7	1938	#define RCC_LSION_BIT_NUMBER 0x00U
<>	144:ef7eb2e8f9f7	1939	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1940
<>	144:ef7eb2e8f9f7	1941	/* CR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	1942	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	/* CIR register byte 2 (Bits[15:8]) base address */
<>	144:ef7eb2e8f9f7	1945	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
<>	144:ef7eb2e8f9f7	1946
<>	144:ef7eb2e8f9f7	1947	/* CIR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	1948	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
<>	144:ef7eb2e8f9f7	1949
<>	144:ef7eb2e8f9f7	1950	/* BDCR register base address */
<>	144:ef7eb2e8f9f7	1951	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
<>	144:ef7eb2e8f9f7	1952
<>	144:ef7eb2e8f9f7	1953	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
<>	144:ef7eb2e8f9f7	1954	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1955
<>	144:ef7eb2e8f9f7	1956	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1957	#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
<>	144:ef7eb2e8f9f7	1958	#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2U) /* Timeout value fixed to 100 ms */
<>	144:ef7eb2e8f9f7	1961	/**
<>	144:ef7eb2e8f9f7	1962	* @}
<>	144:ef7eb2e8f9f7	1963	*/
<>	144:ef7eb2e8f9f7	1964
<>	144:ef7eb2e8f9f7	1965	/**
<>	144:ef7eb2e8f9f7	1966	* @}
<>	144:ef7eb2e8f9f7	1967	*/
<>	144:ef7eb2e8f9f7	1968
<>	144:ef7eb2e8f9f7	1969	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1970	/** @defgroup RCC_Private_Macros RCC Private Macros
<>	144:ef7eb2e8f9f7	1971	* @{
<>	144:ef7eb2e8f9f7	1972	*/
<>	144:ef7eb2e8f9f7	1973
<>	144:ef7eb2e8f9f7	1974	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
<>	144:ef7eb2e8f9f7	1975	* @{
<>	144:ef7eb2e8f9f7	1976	*/
<>	144:ef7eb2e8f9f7	1977	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1980	((HSE) == RCC_HSE_BYPASS))
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1983	((LSE) == RCC_LSE_BYPASS))
<>	144:ef7eb2e8f9f7	1984
<>	144:ef7eb2e8f9f7	1985	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	1986
<>	144:ef7eb2e8f9f7	1987	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
<>	144:ef7eb2e8f9f7	1988
<>	144:ef7eb2e8f9f7	1989	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
<>	144:ef7eb2e8f9f7	1990
<>	144:ef7eb2e8f9f7	1991	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1992	((SOURCE) == RCC_PLLSOURCE_HSE))
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1995	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	1996	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1997
<>	144:ef7eb2e8f9f7	1998	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1999	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	2000	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2001	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
<>	144:ef7eb2e8f9f7	2002	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	2003	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
<>	144:ef7eb2e8f9f7	2004	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| \
<>	144:ef7eb2e8f9f7	2005	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
<>	144:ef7eb2e8f9f7	2006	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	2007	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
<>	144:ef7eb2e8f9f7	2008	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| \
<>	144:ef7eb2e8f9f7	2009	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
<>	144:ef7eb2e8f9f7	2010	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| \
<>	144:ef7eb2e8f9f7	2011	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
<>	144:ef7eb2e8f9f7	2012	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| \
<>	144:ef7eb2e8f9f7	2013	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
<>	144:ef7eb2e8f9f7	2014	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| \
<>	144:ef7eb2e8f9f7	2015	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
<>	144:ef7eb2e8f9f7	2016	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| \
<>	144:ef7eb2e8f9f7	2017	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
<>	144:ef7eb2e8f9f7	2018	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| \
<>	144:ef7eb2e8f9f7	2019	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
<>	144:ef7eb2e8f9f7	2020	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| \
<>	144:ef7eb2e8f9f7	2021	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
<>	144:ef7eb2e8f9f7	2022	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| \
<>	144:ef7eb2e8f9f7	2023	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
<>	144:ef7eb2e8f9f7	2024	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| \
<>	144:ef7eb2e8f9f7	2025	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
<>	144:ef7eb2e8f9f7	2026	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| \
<>	144:ef7eb2e8f9f7	2027	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
<>	144:ef7eb2e8f9f7	2028	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| \
<>	144:ef7eb2e8f9f7	2029	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
<>	144:ef7eb2e8f9f7	2030
<>	144:ef7eb2e8f9f7	2031	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
<>	144:ef7eb2e8f9f7	2032
<>	144:ef7eb2e8f9f7	2033	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) \|\| ((VALUE) == 4U) \|\| ((VALUE) == 6U) \|\| ((VALUE) == 8U))
<>	144:ef7eb2e8f9f7	2036
<>	144:ef7eb2e8f9f7	2037	#define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
<>	144:ef7eb2e8f9f7	2038
<>	144:ef7eb2e8f9f7	2039	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2040	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	2041	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	2042	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	2043	((HCLK) == RCC_SYSCLK_DIV512))
<>	144:ef7eb2e8f9f7	2044
<>	144:ef7eb2e8f9f7	2045	#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
<>	144:ef7eb2e8f9f7	2046
<>	144:ef7eb2e8f9f7	2047	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	2048	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	2049	((PCLK) == RCC_HCLK_DIV16))
<>	144:ef7eb2e8f9f7	2050
<>	144:ef7eb2e8f9f7	2051	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
<>	144:ef7eb2e8f9f7	2052
<>	144:ef7eb2e8f9f7	2053	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	2054	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	2055
<>	144:ef7eb2e8f9f7	2056	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
<>	144:ef7eb2e8f9f7	2057	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	2058
<>	144:ef7eb2e8f9f7	2059	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
<>	144:ef7eb2e8f9f7	2060	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
<>	144:ef7eb2e8f9f7	2061	((DIV) == RCC_MCODIV_5))
<>	144:ef7eb2e8f9f7	2062	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
<>	144:ef7eb2e8f9f7	2063
<>	144:ef7eb2e8f9f7	2064	/**
<>	144:ef7eb2e8f9f7	2065	* @}
<>	144:ef7eb2e8f9f7	2066	*/
<>	144:ef7eb2e8f9f7	2067
<>	144:ef7eb2e8f9f7	2068	/**
<>	144:ef7eb2e8f9f7	2069	* @}
<>	144:ef7eb2e8f9f7	2070	*/
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	/**
<>	144:ef7eb2e8f9f7	2073	* @}
<>	144:ef7eb2e8f9f7	2074	*/
<>	144:ef7eb2e8f9f7	2075
<>	144:ef7eb2e8f9f7	2076	/**
<>	144:ef7eb2e8f9f7	2077	* @}
<>	144:ef7eb2e8f9f7	2078	*/
<>	144:ef7eb2e8f9f7	2079
<>	144:ef7eb2e8f9f7	2080	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	2081	}
<>	144:ef7eb2e8f9f7	2082	#endif
<>	144:ef7eb2e8f9f7	2083
<>	144:ef7eb2e8f9f7	2084	#endif /* __STM32F2xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	2085
<>	144:ef7eb2e8f9f7	2086	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_rcc.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning