Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_iwdg.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_iwdg.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Independent Watchdog (IWDG) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and Start functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### IWDG Generic features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 (+) The IWDG can be started by either software or hardware (configurable
<> 144:ef7eb2e8f9f7 19 through option byte).
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
<> 144:ef7eb2e8f9f7 22 if the main clock fails.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (+) Once the IWDG is started, the LSI is forced ON and both can not be
<> 144:ef7eb2e8f9f7 25 disabled. The counter starts counting down from the reset value (0xFFF).
<> 144:ef7eb2e8f9f7 26 When it reaches the end of count value (0x000) a reset signal is
<> 144:ef7eb2e8f9f7 27 generated (IWDG reset).
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
<> 144:ef7eb2e8f9f7 30 the IWDG_RLR value is reloaded in the counter and the watchdog reset is
<> 144:ef7eb2e8f9f7 31 prevented.
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 (+) The IWDG is implemented in the VDD voltage domain that is still functional
<> 144:ef7eb2e8f9f7 34 in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
<> 144:ef7eb2e8f9f7 35 IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
<> 144:ef7eb2e8f9f7 36 reset occurs.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (+) Debug mode : When the microcontroller enters debug mode (core halted),
<> 144:ef7eb2e8f9f7 39 the IWDG counter either continues to work normally or stops, depending
<> 144:ef7eb2e8f9f7 40 on DBG_IWDG_STOP configuration bit in DBG module, accessible through
<> 144:ef7eb2e8f9f7 41 __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
<> 144:ef7eb2e8f9f7 44 The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx
<> 144:ef7eb2e8f9f7 45 devices provide the capability to measure the LSI frequency (LSI clock
<> 144:ef7eb2e8f9f7 46 connected internally to TIM5 CH4 input capture). The measured value
<> 144:ef7eb2e8f9f7 47 can be used to have an IWDG timeout with an acceptable accuracy.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 50 ==============================================================================
<> 144:ef7eb2e8f9f7 51 [..]
<> 144:ef7eb2e8f9f7 52 (#) Use IWDG using HAL_IWDG_Init() function to :
<> 144:ef7eb2e8f9f7 53 (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
<> 144:ef7eb2e8f9f7 54 clock is forced ON and IWDG counter starts downcounting.
<> 144:ef7eb2e8f9f7 55 (+) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
<> 144:ef7eb2e8f9f7 56 (+) Configure the IWDG prescaler and counter reload value. This reload
<> 144:ef7eb2e8f9f7 57 value will be loaded in the IWDG counter each time the watchdog is
<> 144:ef7eb2e8f9f7 58 reloaded, then the IWDG will start counting down from this value.
<> 144:ef7eb2e8f9f7 59 (+) wait for status flags to be reset"
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Then the application program must refresh the IWDG counter at regular
<> 144:ef7eb2e8f9f7 62 intervals during normal operation to prevent an MCU reset, using
<> 144:ef7eb2e8f9f7 63 HAL_IWDG_Refresh() function.
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 *** IWDG HAL driver macros list ***
<> 144:ef7eb2e8f9f7 66 ====================================
<> 144:ef7eb2e8f9f7 67 [..]
<> 144:ef7eb2e8f9f7 68 Below the list of most used macros in IWDG HAL driver:
<> 144:ef7eb2e8f9f7 69 (+) __HAL_IWDG_START: Enable the IWDG peripheral
<> 144:ef7eb2e8f9f7 70 (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
<> 144:ef7eb2e8f9f7 71 the reload register
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 @endverbatim
<> 144:ef7eb2e8f9f7 74 ******************************************************************************
<> 144:ef7eb2e8f9f7 75 * @attention
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 78 *
<> 144:ef7eb2e8f9f7 79 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 80 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 81 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 84 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 85 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 87 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 88 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 89 *
<> 144:ef7eb2e8f9f7 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 ******************************************************************************
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 105 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_IWDG_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112 /** @addtogroup IWDG
<> 144:ef7eb2e8f9f7 113 * @brief IWDG HAL module driver.
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup IWDG_Private_Defines IWDG Private Defines
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
<> 144:ef7eb2e8f9f7 123 higher prescaler (256), and according to HSI variation, we need to wait at
<> 144:ef7eb2e8f9f7 124 least 6 cycles so 48 ms. */
<> 144:ef7eb2e8f9f7 125 #define HAL_IWDG_DEFAULT_TIMEOUT 48U
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 133 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @addtogroup IWDG_Exported_Functions
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @addtogroup IWDG_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 140 * @brief Initialization and Start functions.
<> 144:ef7eb2e8f9f7 141 *
<> 144:ef7eb2e8f9f7 142 @verbatim
<> 144:ef7eb2e8f9f7 143 ===============================================================================
<> 144:ef7eb2e8f9f7 144 ##### Initialization and Start functions #####
<> 144:ef7eb2e8f9f7 145 ===============================================================================
<> 144:ef7eb2e8f9f7 146 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 147 (+) Initialize the IWDG according to the specified parameters in the
<> 144:ef7eb2e8f9f7 148 IWDG_InitTypeDef of associated handle.
<> 144:ef7eb2e8f9f7 149 (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
<> 144:ef7eb2e8f9f7 150 is reloaded in order to exit function with correct time base.
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 @endverbatim
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @brief Initialize the IWDG according to the specified parameters in the
<> 144:ef7eb2e8f9f7 158 * IWDG_InitTypeDef and start watchdog. Before exiting function,
<> 144:ef7eb2e8f9f7 159 * watchdog is refreshed in order to have correct time base.
<> 144:ef7eb2e8f9f7 160 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 161 * the configuration information for the specified IWDG module.
<> 144:ef7eb2e8f9f7 162 * @retval HAL status
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Check the IWDG handle allocation */
<> 144:ef7eb2e8f9f7 169 if(hiwdg == NULL)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Check the parameters */
<> 144:ef7eb2e8f9f7 175 assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Enable IWDG. LSI is turned on automaticaly */
<> 144:ef7eb2e8f9f7 180 __HAL_IWDG_START(hiwdg);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
<> 144:ef7eb2e8f9f7 183 IWDG_ENABLE_WRITE_ACCESS(hiwdg);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Write to IWDG registers the Prescaler & Reload values to work with */
<> 144:ef7eb2e8f9f7 186 hiwdg->Instance->PR = hiwdg->Init.Prescaler;
<> 144:ef7eb2e8f9f7 187 hiwdg->Instance->RLR = hiwdg->Init.Reload;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Check pending flag, if previous update not done, return timeout */
<> 144:ef7eb2e8f9f7 190 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Wait for register to be updated */
<> 144:ef7eb2e8f9f7 193 while(hiwdg->Instance->SR != RESET)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Reload IWDG counter with value defined in the reload register */
<> 144:ef7eb2e8f9f7 202 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Return function status */
<> 144:ef7eb2e8f9f7 205 return HAL_OK;
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @}
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @addtogroup IWDG_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 213 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 214 *
<> 144:ef7eb2e8f9f7 215 @verbatim
<> 144:ef7eb2e8f9f7 216 ===============================================================================
<> 144:ef7eb2e8f9f7 217 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 218 ===============================================================================
<> 144:ef7eb2e8f9f7 219 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 220 (+) Refresh the IWDG.
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 @endverbatim
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief Refresh the IWDG.
<> 144:ef7eb2e8f9f7 228 * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 229 * the configuration information for the specified IWDG module.
<> 144:ef7eb2e8f9f7 230 * @retval HAL status
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* Reload IWDG counter with value defined in the reload register */
<> 144:ef7eb2e8f9f7 235 __HAL_IWDG_RELOAD_COUNTER(hiwdg);
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* Return function status */
<> 144:ef7eb2e8f9f7 238 return HAL_OK;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 #endif /* HAL_IWDG_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 250 /**
<> 144:ef7eb2e8f9f7 251 * @}
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/