Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_i2s.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The I2S HAL driver can be used as follow:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 23 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these I2S pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 28 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 31 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA handle structure for the Tx/Rx stream.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 38 DMA Tx/Rx Stream.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 41 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 44 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 45 __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 46 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 47 (+@) I2S PLL is configured or
<> 144:ef7eb2e8f9f7 48 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f2xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 54 =================================
<> 144:ef7eb2e8f9f7 55 [..]
<> 144:ef7eb2e8f9f7 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 60 ===================================
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ==============================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 =============================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in USART HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 [..]
<> 144:ef7eb2e8f9f7 106 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 @endverbatim
<> 144:ef7eb2e8f9f7 109 ******************************************************************************
<> 144:ef7eb2e8f9f7 110 * @attention
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 115 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 116 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 117 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 119 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 120 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 122 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 123 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 ******************************************************************************
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 147 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /** @addtogroup I2S_Private_Functions
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 166 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 167 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 168 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 179 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 180 *
<> 144:ef7eb2e8f9f7 181 @verbatim
<> 144:ef7eb2e8f9f7 182 ===============================================================================
<> 144:ef7eb2e8f9f7 183 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 184 ===============================================================================
<> 144:ef7eb2e8f9f7 185 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 186 de-initialize the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 189 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 192 the selected configuration:
<> 144:ef7eb2e8f9f7 193 (++) Mode
<> 144:ef7eb2e8f9f7 194 (++) Standard
<> 144:ef7eb2e8f9f7 195 (++) Data Format
<> 144:ef7eb2e8f9f7 196 (++) MCLK Output
<> 144:ef7eb2e8f9f7 197 (++) Audio frequency
<> 144:ef7eb2e8f9f7 198 (++) Polarity
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 201 of the selected I2Sx peripheral.
<> 144:ef7eb2e8f9f7 202 @endverbatim
<> 144:ef7eb2e8f9f7 203 * @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 208 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 209 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 210 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 211 * @retval HAL status
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
<> 144:ef7eb2e8f9f7 216 uint32_t tmp = 0U, i2sclk = 0U;
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 219 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Check the I2S parameters */
<> 144:ef7eb2e8f9f7 225 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 226 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 227 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 228 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 229 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 230 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 if(hi2s->State == HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 237 hi2s->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 238 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 239 HAL_I2S_MspInit(hi2s);
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
<> 144:ef7eb2e8f9f7 245 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
<> 144:ef7eb2e8f9f7 246 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
<> 144:ef7eb2e8f9f7 247 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
<> 144:ef7eb2e8f9f7 248 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 249 hi2s->Instance->I2SPR = 0x0002U;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Get the I2SCFGR register value */
<> 144:ef7eb2e8f9f7 252 tmpreg = hi2s->Instance->I2SCFGR;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
<> 144:ef7eb2e8f9f7 255 /* If the requested audio frequency is not the default, compute the prescaler */
<> 144:ef7eb2e8f9f7 256 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 /* Check the frame length (For the Prescaler computing) *******************/
<> 144:ef7eb2e8f9f7 259 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 260 {
<> 144:ef7eb2e8f9f7 261 /* Packet length is 32 bits */
<> 144:ef7eb2e8f9f7 262 packetlength = 2U;
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Get I2S source Clock frequency ****************************************/
<> 144:ef7eb2e8f9f7 266 /* If an external I2S clock has to be used, the specific define should be set
<> 144:ef7eb2e8f9f7 267 in the project configuration or in the stm32f2xx_conf.h file */
<> 144:ef7eb2e8f9f7 268 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Set external clock as I2S clock source */
<> 144:ef7eb2e8f9f7 271 if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0U)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Set the I2S clock to the external clock value */
<> 144:ef7eb2e8f9f7 277 i2sclk = EXTERNAL_CLOCK_VALUE;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 else
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 /* Check if PLLI2S is enabled or Not */
<> 144:ef7eb2e8f9f7 282 if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Set PLLI2S as I2S clock source */
<> 144:ef7eb2e8f9f7 290 if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0U)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Get the PLLM value */
<> 144:ef7eb2e8f9f7 296 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Get the I2S source clock value */
<> 144:ef7eb2e8f9f7 299 i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 else
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Get the I2S source clock value */
<> 144:ef7eb2e8f9f7 304 i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U));
<> 144:ef7eb2e8f9f7 307 i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U));
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 311 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 /* MCLK output is enabled */
<> 144:ef7eb2e8f9f7 314 tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 else
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* MCLK output is disabled */
<> 144:ef7eb2e8f9f7 319 tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Remove the flatting point */
<> 144:ef7eb2e8f9f7 323 tmp = tmp / 10U;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* Check the parity of the divider */
<> 144:ef7eb2e8f9f7 326 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* Compute the i2sdiv prescaler */
<> 144:ef7eb2e8f9f7 329 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 144:ef7eb2e8f9f7 332 i2sodd = (uint32_t) (i2sodd << 8U);
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 144:ef7eb2e8f9f7 336 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Set the default values */
<> 144:ef7eb2e8f9f7 339 i2sdiv = 2U;
<> 144:ef7eb2e8f9f7 340 i2sodd = 0U;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 344 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Configure the I2S with the I2S_InitStruct values */
<> 144:ef7eb2e8f9f7 347 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 350 hi2s->Instance->I2SCFGR = tmpreg;
<> 144:ef7eb2e8f9f7 351 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 352 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 return HAL_OK;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 359 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 360 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 361 * @retval HAL status
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 364 {
<> 144:ef7eb2e8f9f7 365 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 366 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 369 }
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 374 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 377 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Release Lock */
<> 144:ef7eb2e8f9f7 380 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 return HAL_OK;
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 387 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 388 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 389 * @retval None
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 394 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 395 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 396 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 402 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 403 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 404 * @retval None
<> 144:ef7eb2e8f9f7 405 */
<> 144:ef7eb2e8f9f7 406 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 409 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 410 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 411 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 419 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 420 *
<> 144:ef7eb2e8f9f7 421 @verbatim
<> 144:ef7eb2e8f9f7 422 ===============================================================================
<> 144:ef7eb2e8f9f7 423 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 424 ===============================================================================
<> 144:ef7eb2e8f9f7 425 [..]
<> 144:ef7eb2e8f9f7 426 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 427 transfers.
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 430 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 431 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 432 after finishing transfer.
<> 144:ef7eb2e8f9f7 433 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 434 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 435 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 436 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 437 using DMA mode.
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 440 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 441 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 444 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 445 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 448 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 449 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 452 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 453 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 454 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 @endverbatim
<> 144:ef7eb2e8f9f7 457 * @{
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 462 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 463 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 464 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 465 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 466 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 467 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 468 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 469 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 470 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 471 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 472 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 473 * @retval HAL status
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 478 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 hi2s->TxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 490 hi2s->TxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else
<> 144:ef7eb2e8f9f7 493 {
<> 144:ef7eb2e8f9f7 494 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 495 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Process Locked */
<> 144:ef7eb2e8f9f7 499 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 504 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 507 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 while(hi2s->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 hi2s->Instance->DR = (*pData++);
<> 144:ef7eb2e8f9f7 513 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 514 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 515 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Check if Slave mode is selected */
<> 144:ef7eb2e8f9f7 522 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* Wait until Busy flag is reset */
<> 144:ef7eb2e8f9f7 525 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 526 {
<> 144:ef7eb2e8f9f7 527 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 534 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 return HAL_OK;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538 else
<> 144:ef7eb2e8f9f7 539 {
<> 144:ef7eb2e8f9f7 540 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 546 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 547 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 548 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 549 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 550 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 551 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 552 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 553 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 554 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 555 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 556 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 557 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 558 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 559 * @retval HAL status
<> 144:ef7eb2e8f9f7 560 */
<> 144:ef7eb2e8f9f7 561 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 564 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 hi2s->RxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 576 hi2s->RxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 else
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 581 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 /* Process Locked */
<> 144:ef7eb2e8f9f7 584 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 589 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 592 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 596 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 599 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 600 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Receive data */
<> 144:ef7eb2e8f9f7 604 while(hi2s->RxXferCount > 0U)
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 607 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 610 }
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 (*pData++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 613 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 614 }
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 619 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 return HAL_OK;
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623 else
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 631 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 632 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 633 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 634 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 635 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 636 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 637 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 638 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 639 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 640 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 641 * @retval HAL status
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 646 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 654 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 hi2s->TxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 659 hi2s->TxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 else
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 664 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Process Locked */
<> 144:ef7eb2e8f9f7 668 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 671 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 674 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 677 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 680 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 684 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 return HAL_OK;
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 else
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 696 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 697 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 698 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 699 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 700 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 701 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 702 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 703 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 704 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 705 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 706 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 707 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 708 * @retval HAL status
<> 144:ef7eb2e8f9f7 709 */
<> 144:ef7eb2e8f9f7 710 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 713 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 721 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 hi2s->RxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 726 hi2s->RxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 else
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 731 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 /* Process Locked */
<> 144:ef7eb2e8f9f7 734 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 737 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 740 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 743 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 746 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 750 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 return HAL_OK;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 else
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /**
<> 144:ef7eb2e8f9f7 762 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 763 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 764 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 765 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 766 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 767 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 768 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 769 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 770 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 771 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 772 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 773 * @retval HAL status
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 778 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 788 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 hi2s->TxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 793 hi2s->TxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795 else
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 798 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Process Locked */
<> 144:ef7eb2e8f9f7 802 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 805 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Set the I2S Tx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 808 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /* Set the I2S Tx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 811 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 814 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Enable the Tx DMA Stream */
<> 144:ef7eb2e8f9f7 817 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 818 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 821 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 824 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Check if the I2S Tx request is already enabled */
<> 144:ef7eb2e8f9f7 828 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 831 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 832 }
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 835 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 return HAL_OK;
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 else
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 }
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief Receive an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 847 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 848 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 849 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 850 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 851 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 852 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 853 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 854 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 855 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 856 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 857 * @retval HAL status
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 862 uint32_t tmp1 = 0U;
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 870 {
<> 144:ef7eb2e8f9f7 871 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 872 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
<> 144:ef7eb2e8f9f7 873 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 hi2s->RxXferSize = Size*2U;
<> 144:ef7eb2e8f9f7 876 hi2s->RxXferCount = Size*2U;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878 else
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 881 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 /* Process Locked */
<> 144:ef7eb2e8f9f7 884 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 887 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /* Set the I2S Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 890 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Set the I2S Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 893 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 896 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 899 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 900 {
<> 144:ef7eb2e8f9f7 901 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 902 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 903 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Enable the Rx DMA Stream */
<> 144:ef7eb2e8f9f7 907 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 908 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 911 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 914 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 915 }
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Check if the I2S Rx request is already enabled */
<> 144:ef7eb2e8f9f7 918 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 921 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 925 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 return HAL_OK;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 else
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /**
<> 144:ef7eb2e8f9f7 936 * @brief Pauses the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 937 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 938 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 939 * @retval HAL status
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 942 {
<> 144:ef7eb2e8f9f7 943 /* Process Locked */
<> 144:ef7eb2e8f9f7 944 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 949 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 950 }
<> 144:ef7eb2e8f9f7 951 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 954 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 961 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963 else
<> 144:ef7eb2e8f9f7 964 {
<> 144:ef7eb2e8f9f7 965 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 966 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968 }
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 971 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 return HAL_OK;
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 978 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 979 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 980 * @retval HAL status
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 /* Process Locked */
<> 144:ef7eb2e8f9f7 985 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 990 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 995 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 1002 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004 else
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 1007 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 }
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* If the I2S peripheral is still not enabled, enable it */
<> 144:ef7eb2e8f9f7 1012 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 1015 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1019 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 return HAL_OK;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /**
<> 144:ef7eb2e8f9f7 1025 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 1026 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1027 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1028 * @retval HAL status
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 /* Process Locked */
<> 144:ef7eb2e8f9f7 1033 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 1036 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 1037 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 /* Abort the I2S DMA Stream tx */
<> 144:ef7eb2e8f9f7 1040 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044 /* Abort the I2S DMA Stream rx */
<> 144:ef7eb2e8f9f7 1045 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1048 }
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1051 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1056 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 return HAL_OK;
<> 144:ef7eb2e8f9f7 1059 }
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /**
<> 144:ef7eb2e8f9f7 1062 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 1063 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1064 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1065 * @retval None
<> 144:ef7eb2e8f9f7 1066 */
<> 144:ef7eb2e8f9f7 1067 __weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 uint32_t tmp1 = 0U, tmp2 = 0U;
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1072 {
<> 144:ef7eb2e8f9f7 1073 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
<> 144:ef7eb2e8f9f7 1074 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
<> 144:ef7eb2e8f9f7 1075 /* I2S in mode Receiver ------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1076 if((tmp1 != RESET) && (tmp2 != RESET))
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
<> 144:ef7eb2e8f9f7 1082 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
<> 144:ef7eb2e8f9f7 1083 /* I2S Overrun error interrupt occurred ---------------------------------*/
<> 144:ef7eb2e8f9f7 1084 if((tmp1 != RESET) && (tmp2 != RESET))
<> 144:ef7eb2e8f9f7 1085 {
<> 144:ef7eb2e8f9f7 1086 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 1087 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 1088 }
<> 144:ef7eb2e8f9f7 1089 }
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
<> 144:ef7eb2e8f9f7 1094 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
<> 144:ef7eb2e8f9f7 1095 /* I2S in mode Transmitter -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1096 if((tmp1 != RESET) && (tmp2 != RESET))
<> 144:ef7eb2e8f9f7 1097 {
<> 144:ef7eb2e8f9f7 1098 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
<> 144:ef7eb2e8f9f7 1102 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
<> 144:ef7eb2e8f9f7 1103 /* I2S Underrun error interrupt occurred --------------------------------*/
<> 144:ef7eb2e8f9f7 1104 if((tmp1 != RESET) && (tmp2 != RESET))
<> 144:ef7eb2e8f9f7 1105 {
<> 144:ef7eb2e8f9f7 1106 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 1107 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 1108 }
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Call the Error call Back in case of Errors */
<> 144:ef7eb2e8f9f7 1112 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 /* Set the I2S state ready to be able to start again the process */
<> 144:ef7eb2e8f9f7 1115 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1116 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1122 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1123 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1124 * @retval None
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1129 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1130 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1131 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1132 */
<> 144:ef7eb2e8f9f7 1133 }
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /**
<> 144:ef7eb2e8f9f7 1136 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1137 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1138 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1139 * @retval None
<> 144:ef7eb2e8f9f7 1140 */
<> 144:ef7eb2e8f9f7 1141 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1144 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1145 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1146 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1147 */
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 /**
<> 144:ef7eb2e8f9f7 1151 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1152 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1153 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1154 * @retval None
<> 144:ef7eb2e8f9f7 1155 */
<> 144:ef7eb2e8f9f7 1156 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1159 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1160 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1161 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1162 */
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /**
<> 144:ef7eb2e8f9f7 1166 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1167 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1168 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1169 * @retval None
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1174 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1175 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1176 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1177 */
<> 144:ef7eb2e8f9f7 1178 }
<> 144:ef7eb2e8f9f7 1179
<> 144:ef7eb2e8f9f7 1180 /**
<> 144:ef7eb2e8f9f7 1181 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1182 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1183 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1184 * @retval None
<> 144:ef7eb2e8f9f7 1185 */
<> 144:ef7eb2e8f9f7 1186 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1187 {
<> 144:ef7eb2e8f9f7 1188 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1189 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1190 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1191 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1192 */
<> 144:ef7eb2e8f9f7 1193 }
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 /**
<> 144:ef7eb2e8f9f7 1196 * @}
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1200 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1201 @verbatim
<> 144:ef7eb2e8f9f7 1202 ===============================================================================
<> 144:ef7eb2e8f9f7 1203 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1204 ===============================================================================
<> 144:ef7eb2e8f9f7 1205 [..]
<> 144:ef7eb2e8f9f7 1206 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1207 and the data flow.
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 @endverbatim
<> 144:ef7eb2e8f9f7 1210 * @{
<> 144:ef7eb2e8f9f7 1211 */
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /**
<> 144:ef7eb2e8f9f7 1214 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1215 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1216 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1217 * @retval HAL state
<> 144:ef7eb2e8f9f7 1218 */
<> 144:ef7eb2e8f9f7 1219 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1220 {
<> 144:ef7eb2e8f9f7 1221 return hi2s->State;
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /**
<> 144:ef7eb2e8f9f7 1225 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1226 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1227 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1228 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1229 */
<> 144:ef7eb2e8f9f7 1230 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234 /**
<> 144:ef7eb2e8f9f7 1235 * @}
<> 144:ef7eb2e8f9f7 1236 */
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 /**
<> 144:ef7eb2e8f9f7 1239 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1240 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1241 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1242 * @retval None
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 hi2s->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1253 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 if(hi2s->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1258 {
<> 144:ef7eb2e8f9f7 1259 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1260 }
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262 else
<> 144:ef7eb2e8f9f7 1263 {
<> 144:ef7eb2e8f9f7 1264 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /**
<> 144:ef7eb2e8f9f7 1271 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1272 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1273 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1274 * @retval None
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1277 {
<> 144:ef7eb2e8f9f7 1278 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /**
<> 144:ef7eb2e8f9f7 1284 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1285 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1286 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1287 * @retval None
<> 144:ef7eb2e8f9f7 1288 */
<> 144:ef7eb2e8f9f7 1289 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1290 {
<> 144:ef7eb2e8f9f7 1291 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1296 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1297 hi2s->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1298 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1299 {
<> 144:ef7eb2e8f9f7 1300 if(hi2s->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1301 {
<> 144:ef7eb2e8f9f7 1302 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304 }
<> 144:ef7eb2e8f9f7 1305 else
<> 144:ef7eb2e8f9f7 1306 {
<> 144:ef7eb2e8f9f7 1307 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1308 }
<> 144:ef7eb2e8f9f7 1309 }
<> 144:ef7eb2e8f9f7 1310 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1315 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1316 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1317 * @retval None
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1324 }
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1328 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1329 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1330 * @retval None
<> 144:ef7eb2e8f9f7 1331 */
<> 144:ef7eb2e8f9f7 1332 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1333 {
<> 144:ef7eb2e8f9f7 1334 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 hi2s->TxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1337 hi2s->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1342 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /**
<> 144:ef7eb2e8f9f7 1346 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1347 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1348 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1349 * @retval HAL status
<> 144:ef7eb2e8f9f7 1350 */
<> 144:ef7eb2e8f9f7 1351 static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1352 {
<> 144:ef7eb2e8f9f7 1353 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1354 {
<> 144:ef7eb2e8f9f7 1355 /* Process Locked */
<> 144:ef7eb2e8f9f7 1356 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 /* Transmit data */
<> 144:ef7eb2e8f9f7 1359 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 if(hi2s->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1366 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1371 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1372 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1373 }
<> 144:ef7eb2e8f9f7 1374 else
<> 144:ef7eb2e8f9f7 1375 {
<> 144:ef7eb2e8f9f7 1376 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1377 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 return HAL_OK;
<> 144:ef7eb2e8f9f7 1381 }
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 else
<> 144:ef7eb2e8f9f7 1384 {
<> 144:ef7eb2e8f9f7 1385 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1386 }
<> 144:ef7eb2e8f9f7 1387 }
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /**
<> 144:ef7eb2e8f9f7 1390 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1391 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1392 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1393 * @retval HAL status
<> 144:ef7eb2e8f9f7 1394 */
<> 144:ef7eb2e8f9f7 1395 static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1398 {
<> 144:ef7eb2e8f9f7 1399 /* Process Locked */
<> 144:ef7eb2e8f9f7 1400 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 /* Receive data */
<> 144:ef7eb2e8f9f7 1403 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 1408 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 1409 {
<> 144:ef7eb2e8f9f7 1410 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 1411 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 1412 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 if(hi2s->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1416 {
<> 144:ef7eb2e8f9f7 1417 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1418 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1423 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1424
<> 144:ef7eb2e8f9f7 1425 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1426 }
<> 144:ef7eb2e8f9f7 1427 else
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1430 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1431 }
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 return HAL_OK;
<> 144:ef7eb2e8f9f7 1434 }
<> 144:ef7eb2e8f9f7 1435 else
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /**
<> 144:ef7eb2e8f9f7 1442 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1443 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1444 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1445 * @param Flag: Flag checked
<> 144:ef7eb2e8f9f7 1446 * @param Status: Value of the flag expected
<> 144:ef7eb2e8f9f7 1447 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1448 * @retval HAL status
<> 144:ef7eb2e8f9f7 1449 */
<> 144:ef7eb2e8f9f7 1450 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1453
<> 144:ef7eb2e8f9f7 1454 /* Get tick */
<> 144:ef7eb2e8f9f7 1455 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1458 if(Status == RESET)
<> 144:ef7eb2e8f9f7 1459 {
<> 144:ef7eb2e8f9f7 1460 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1461 {
<> 144:ef7eb2e8f9f7 1462 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1463 {
<> 144:ef7eb2e8f9f7 1464 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1465 {
<> 144:ef7eb2e8f9f7 1466 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1467 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1470 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1473 }
<> 144:ef7eb2e8f9f7 1474 }
<> 144:ef7eb2e8f9f7 1475 }
<> 144:ef7eb2e8f9f7 1476 }
<> 144:ef7eb2e8f9f7 1477 else
<> 144:ef7eb2e8f9f7 1478 {
<> 144:ef7eb2e8f9f7 1479 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1480 {
<> 144:ef7eb2e8f9f7 1481 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1482 {
<> 144:ef7eb2e8f9f7 1483 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1484 {
<> 144:ef7eb2e8f9f7 1485 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1486 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1489 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1492 }
<> 144:ef7eb2e8f9f7 1493 }
<> 144:ef7eb2e8f9f7 1494 }
<> 144:ef7eb2e8f9f7 1495 }
<> 144:ef7eb2e8f9f7 1496 return HAL_OK;
<> 144:ef7eb2e8f9f7 1497 }
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /**
<> 144:ef7eb2e8f9f7 1500 * @}
<> 144:ef7eb2e8f9f7 1501 */
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1504 /**
<> 144:ef7eb2e8f9f7 1505 * @}
<> 144:ef7eb2e8f9f7 1506 */
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /**
<> 144:ef7eb2e8f9f7 1509 * @}
<> 144:ef7eb2e8f9f7 1510 */
<> 144:ef7eb2e8f9f7 1511
<> 144:ef7eb2e8f9f7 1512 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/