Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_i2c.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_i2c.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of I2C HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup I2C
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
<> 144:ef7eb2e8f9f7 68 This parameter must be set to a value lower than 400kHz */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 74 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref I2C_addressing_mode */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref I2C_dual_addressing_mode */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 83 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref I2C_general_call_addressing_mode */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref I2C_nostretch_mode */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 }I2C_InitTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief HAL State structure definition
<> 144:ef7eb2e8f9f7 95 * @note HAL I2C State value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 96 * b7-b6 Error information
<> 144:ef7eb2e8f9f7 97 * 00 : No Error
<> 144:ef7eb2e8f9f7 98 * 01 : Abort (Abort user request on going)
<> 144:ef7eb2e8f9f7 99 * 10 : Timeout
<> 144:ef7eb2e8f9f7 100 * 11 : Error
<> 144:ef7eb2e8f9f7 101 * b5 IP initilisation status
<> 144:ef7eb2e8f9f7 102 * 0 : Reset (IP not initialized)
<> 144:ef7eb2e8f9f7 103 * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
<> 144:ef7eb2e8f9f7 104 * b4 (not used)
<> 144:ef7eb2e8f9f7 105 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 106 * b3
<> 144:ef7eb2e8f9f7 107 * 0 : Ready or Busy (No Listen mode ongoing)
<> 144:ef7eb2e8f9f7 108 * 1 : Listen (IP in Address Listen Mode)
<> 144:ef7eb2e8f9f7 109 * b2 Intrinsic process state
<> 144:ef7eb2e8f9f7 110 * 0 : Ready
<> 144:ef7eb2e8f9f7 111 * 1 : Busy (IP busy with some configuration or internal operations)
<> 144:ef7eb2e8f9f7 112 * b1 Rx state
<> 144:ef7eb2e8f9f7 113 * 0 : Ready (no Rx operation ongoing)
<> 144:ef7eb2e8f9f7 114 * 1 : Busy (Rx operation ongoing)
<> 144:ef7eb2e8f9f7 115 * b0 Tx state
<> 144:ef7eb2e8f9f7 116 * 0 : Ready (no Tx operation ongoing)
<> 144:ef7eb2e8f9f7 117 * 1 : Busy (Tx operation ongoing)
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef enum
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
<> 144:ef7eb2e8f9f7 122 HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 123 HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
<> 144:ef7eb2e8f9f7 124 HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 125 HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 126 HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
<> 144:ef7eb2e8f9f7 127 HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
<> 144:ef7eb2e8f9f7 128 process is ongoing */
<> 144:ef7eb2e8f9f7 129 HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
<> 144:ef7eb2e8f9f7 130 process is ongoing */
<> 144:ef7eb2e8f9f7 131 HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
<> 144:ef7eb2e8f9f7 132 HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 133 HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 }HAL_I2C_StateTypeDef;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief HAL Mode structure definition
<> 144:ef7eb2e8f9f7 139 * @note HAL I2C Mode value coding follow below described bitmap :
<> 144:ef7eb2e8f9f7 140 * b7 (not used)
<> 144:ef7eb2e8f9f7 141 * x : Should be set to 0
<> 144:ef7eb2e8f9f7 142 * b6
<> 144:ef7eb2e8f9f7 143 * 0 : None
<> 144:ef7eb2e8f9f7 144 * 1 : Memory (HAL I2C communication is in Memory Mode)
<> 144:ef7eb2e8f9f7 145 * b5
<> 144:ef7eb2e8f9f7 146 * 0 : None
<> 144:ef7eb2e8f9f7 147 * 1 : Slave (HAL I2C communication is in Slave Mode)
<> 144:ef7eb2e8f9f7 148 * b4
<> 144:ef7eb2e8f9f7 149 * 0 : None
<> 144:ef7eb2e8f9f7 150 * 1 : Master (HAL I2C communication is in Master Mode)
<> 144:ef7eb2e8f9f7 151 * b3-b2-b1-b0 (not used)
<> 144:ef7eb2e8f9f7 152 * xxxx : Should be set to 0000
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 typedef enum
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
<> 144:ef7eb2e8f9f7 157 HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
<> 144:ef7eb2e8f9f7 158 HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
<> 144:ef7eb2e8f9f7 159 HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 }HAL_I2C_ModeTypeDef;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief I2C handle Structure definition
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 typedef struct
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 uint16_t XferSize; /*!< I2C transfer size */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 __IO uint32_t XferOptions; /*!< I2C transfer options */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
<> 144:ef7eb2e8f9f7 181 context for internal usage */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 __IO uint32_t ErrorCode; /*!< I2C Error code */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 __IO uint32_t Devaddress; /*!< I2C Target device address */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 __IO uint32_t Memaddress; /*!< I2C Target memory address */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 __IO uint32_t EventCount; /*!< I2C Event counter */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 }I2C_HandleTypeDef;
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 209 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup I2C_Error_Code I2C Error Code
<> 144:ef7eb2e8f9f7 214 * @brief I2C Error Code
<> 144:ef7eb2e8f9f7 215 * @{
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217 #define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 144:ef7eb2e8f9f7 218 #define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
<> 144:ef7eb2e8f9f7 219 #define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
<> 144:ef7eb2e8f9f7 220 #define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
<> 144:ef7eb2e8f9f7 221 #define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
<> 144:ef7eb2e8f9f7 222 #define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 223 #define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
<> 144:ef7eb2e8f9f7 224 /**
<> 144:ef7eb2e8f9f7 225 * @}
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
<> 144:ef7eb2e8f9f7 229 * @{
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 #define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 232 #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @}
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /** @defgroup I2C_addressing_mode I2C addressing mode
<> 144:ef7eb2e8f9f7 238 * @{
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 241 #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 #define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 250 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 259 #define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @}
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /** @defgroup I2C_nostretch_mode I2C nostretch mode
<> 144:ef7eb2e8f9f7 265 * @{
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 #define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 268 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 277 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 #define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 286 #define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 295 #define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 296 #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 297 #define I2C_LAST_FRAME ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @}
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306 #define I2C_IT_BUF I2C_CR2_ITBUFEN
<> 144:ef7eb2e8f9f7 307 #define I2C_IT_EVT I2C_CR2_ITEVTEN
<> 144:ef7eb2e8f9f7 308 #define I2C_IT_ERR I2C_CR2_ITERREN
<> 144:ef7eb2e8f9f7 309 /**
<> 144:ef7eb2e8f9f7 310 * @}
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 144:ef7eb2e8f9f7 314 * @{
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
<> 144:ef7eb2e8f9f7 317 #define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
<> 144:ef7eb2e8f9f7 318 #define I2C_FLAG_PECERR ((uint32_t)0x00011000U)
<> 144:ef7eb2e8f9f7 319 #define I2C_FLAG_OVR ((uint32_t)0x00010800U)
<> 144:ef7eb2e8f9f7 320 #define I2C_FLAG_AF ((uint32_t)0x00010400U)
<> 144:ef7eb2e8f9f7 321 #define I2C_FLAG_ARLO ((uint32_t)0x00010200U)
<> 144:ef7eb2e8f9f7 322 #define I2C_FLAG_BERR ((uint32_t)0x00010100U)
<> 144:ef7eb2e8f9f7 323 #define I2C_FLAG_TXE ((uint32_t)0x00010080U)
<> 144:ef7eb2e8f9f7 324 #define I2C_FLAG_RXNE ((uint32_t)0x00010040U)
<> 144:ef7eb2e8f9f7 325 #define I2C_FLAG_STOPF ((uint32_t)0x00010010U)
<> 144:ef7eb2e8f9f7 326 #define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
<> 144:ef7eb2e8f9f7 327 #define I2C_FLAG_BTF ((uint32_t)0x00010004U)
<> 144:ef7eb2e8f9f7 328 #define I2C_FLAG_ADDR ((uint32_t)0x00010002U)
<> 144:ef7eb2e8f9f7 329 #define I2C_FLAG_SB ((uint32_t)0x00010001U)
<> 144:ef7eb2e8f9f7 330 #define I2C_FLAG_DUALF ((uint32_t)0x00100080U)
<> 144:ef7eb2e8f9f7 331 #define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
<> 144:ef7eb2e8f9f7 332 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
<> 144:ef7eb2e8f9f7 333 #define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
<> 144:ef7eb2e8f9f7 334 #define I2C_FLAG_TRA ((uint32_t)0x00100004U)
<> 144:ef7eb2e8f9f7 335 #define I2C_FLAG_BUSY ((uint32_t)0x00100002U)
<> 144:ef7eb2e8f9f7 336 #define I2C_FLAG_MSL ((uint32_t)0x00100001U)
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @}
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 346 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 144:ef7eb2e8f9f7 347 * @{
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /** @brief Reset I2C handle state
<> 144:ef7eb2e8f9f7 351 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 352 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 353 * @retval None
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @brief Enable or disable the specified I2C interrupts.
<> 144:ef7eb2e8f9f7 358 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 359 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 360 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 361 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 362 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 144:ef7eb2e8f9f7 363 * @arg I2C_IT_EVT: Event interrupt enable
<> 144:ef7eb2e8f9f7 364 * @arg I2C_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 365 * @retval None
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 368 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /** @brief Checks if the specified I2C interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 371 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 372 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 373 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
<> 144:ef7eb2e8f9f7 374 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 375 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 144:ef7eb2e8f9f7 376 * @arg I2C_IT_EVT: Event interrupt enable
<> 144:ef7eb2e8f9f7 377 * @arg I2C_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 378 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /** @brief Checks whether the specified I2C flag is set or not.
<> 144:ef7eb2e8f9f7 383 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 384 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 385 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 386 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 387 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
<> 144:ef7eb2e8f9f7 388 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
<> 144:ef7eb2e8f9f7 389 * @arg I2C_FLAG_PECERR: PEC error in reception flag
<> 144:ef7eb2e8f9f7 390 * @arg I2C_FLAG_OVR: Overrun/Underrun flag
<> 144:ef7eb2e8f9f7 391 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 144:ef7eb2e8f9f7 392 * @arg I2C_FLAG_ARLO: Arbitration lost flag
<> 144:ef7eb2e8f9f7 393 * @arg I2C_FLAG_BERR: Bus error flag
<> 144:ef7eb2e8f9f7 394 * @arg I2C_FLAG_TXE: Data register empty flag
<> 144:ef7eb2e8f9f7 395 * @arg I2C_FLAG_RXNE: Data register not empty flag
<> 144:ef7eb2e8f9f7 396 * @arg I2C_FLAG_STOPF: Stop detection flag
<> 144:ef7eb2e8f9f7 397 * @arg I2C_FLAG_ADD10: 10-bit header sent flag
<> 144:ef7eb2e8f9f7 398 * @arg I2C_FLAG_BTF: Byte transfer finished flag
<> 144:ef7eb2e8f9f7 399 * @arg I2C_FLAG_ADDR: Address sent flag
<> 144:ef7eb2e8f9f7 400 * Address matched flag
<> 144:ef7eb2e8f9f7 401 * @arg I2C_FLAG_SB: Start bit flag
<> 144:ef7eb2e8f9f7 402 * @arg I2C_FLAG_DUALF: Dual flag
<> 144:ef7eb2e8f9f7 403 * @arg I2C_FLAG_SMBHOST: SMBus host header
<> 144:ef7eb2e8f9f7 404 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
<> 144:ef7eb2e8f9f7 405 * @arg I2C_FLAG_GENCALL: General call header flag
<> 144:ef7eb2e8f9f7 406 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
<> 144:ef7eb2e8f9f7 407 * @arg I2C_FLAG_BUSY: Bus busy flag
<> 144:ef7eb2e8f9f7 408 * @arg I2C_FLAG_MSL: Master/Slave flag
<> 144:ef7eb2e8f9f7 409 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
<> 144:ef7eb2e8f9f7 412 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
<> 144:ef7eb2e8f9f7 415 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 416 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 417 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 418 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 419 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
<> 144:ef7eb2e8f9f7 420 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
<> 144:ef7eb2e8f9f7 421 * @arg I2C_FLAG_PECERR: PEC error in reception flag
<> 144:ef7eb2e8f9f7 422 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
<> 144:ef7eb2e8f9f7 423 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 144:ef7eb2e8f9f7 424 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
<> 144:ef7eb2e8f9f7 425 * @arg I2C_FLAG_BERR: Bus error flag
<> 144:ef7eb2e8f9f7 426 * @retval None
<> 144:ef7eb2e8f9f7 427 */
<> 144:ef7eb2e8f9f7 428 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /** @brief Clears the I2C ADDR pending flag.
<> 144:ef7eb2e8f9f7 431 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 432 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 436 do{ \
<> 144:ef7eb2e8f9f7 437 __IO uint32_t tmpreg_addr = 0x00U; \
<> 144:ef7eb2e8f9f7 438 tmpreg_addr = (__HANDLE__)->Instance->SR1; \
<> 144:ef7eb2e8f9f7 439 tmpreg_addr = (__HANDLE__)->Instance->SR2; \
<> 144:ef7eb2e8f9f7 440 UNUSED(tmpreg_addr); \
<> 144:ef7eb2e8f9f7 441 } while(0)
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /** @brief Clears the I2C STOPF pending flag.
<> 144:ef7eb2e8f9f7 444 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 445 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 446 * @retval None
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
<> 144:ef7eb2e8f9f7 449 do{ \
<> 144:ef7eb2e8f9f7 450 __IO uint32_t tmpreg_stop = 0x00U; \
<> 144:ef7eb2e8f9f7 451 tmpreg_stop = (__HANDLE__)->Instance->SR1; \
<> 144:ef7eb2e8f9f7 452 (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
<> 144:ef7eb2e8f9f7 453 UNUSED(tmpreg_stop); \
<> 144:ef7eb2e8f9f7 454 } while(0)
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @brief Enable the I2C peripheral.
<> 144:ef7eb2e8f9f7 457 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 458 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 459 * @retval None
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461 #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /** @brief Disable the I2C peripheral.
<> 144:ef7eb2e8f9f7 464 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 465 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 144:ef7eb2e8f9f7 466 * @retval None
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468 #define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @}
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 475 /** @addtogroup I2C_Exported_Functions
<> 144:ef7eb2e8f9f7 476 * @{
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /** @addtogroup I2C_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 480 * @{
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 483 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 485 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 486 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @}
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /** @addtogroup I2C_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 492 * @{
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 495 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 497 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 498 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 499 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 500 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 501 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 502 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 505 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 506 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 507 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 508 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 509 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 510 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 513 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 514 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 515 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 144:ef7eb2e8f9f7 516 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
<> 144:ef7eb2e8f9f7 517 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 518 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /******* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 522 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 523 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 524 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 525 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 526 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 144:ef7eb2e8f9f7 529 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 530 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 531 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 532 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 533 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 534 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 535 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 144:ef7eb2e8f9f7 536 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 537 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 538 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 539 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 540 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @}
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /** @addtogroup I2C_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 546 * @{
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548 /* Peripheral State, Mode and Errors functions *********************************/
<> 144:ef7eb2e8f9f7 549 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 550 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 551 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @}
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @}
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 561 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 562 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 563 /** @defgroup I2C_Private_Constants I2C Private Constants
<> 144:ef7eb2e8f9f7 564 * @{
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @}
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 572 /** @defgroup I2C_Private_Macros I2C Private Macros
<> 144:ef7eb2e8f9f7 573 * @{
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
<> 144:ef7eb2e8f9f7 577 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
<> 144:ef7eb2e8f9f7 578 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
<> 144:ef7eb2e8f9f7 579 #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
<> 144:ef7eb2e8f9f7 580 #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
<> 144:ef7eb2e8f9f7 581 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
<> 144:ef7eb2e8f9f7 582 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
<> 144:ef7eb2e8f9f7 585 #define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 #define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 144:ef7eb2e8f9f7 588 #define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF0U))))
<> 144:ef7eb2e8f9f7 589 #define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0xF1U))))
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
<> 144:ef7eb2e8f9f7 592 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
<> 144:ef7eb2e8f9f7 595 * @{
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
<> 144:ef7eb2e8f9f7 598 ((CYCLE) == I2C_DUTYCYCLE_16_9))
<> 144:ef7eb2e8f9f7 599 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
<> 144:ef7eb2e8f9f7 600 ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
<> 144:ef7eb2e8f9f7 601 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 144:ef7eb2e8f9f7 602 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 144:ef7eb2e8f9f7 603 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 144:ef7eb2e8f9f7 604 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 144:ef7eb2e8f9f7 605 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 606 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 144:ef7eb2e8f9f7 607 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 144:ef7eb2e8f9f7 608 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 144:ef7eb2e8f9f7 609 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))
<> 144:ef7eb2e8f9f7 610 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
<> 144:ef7eb2e8f9f7 611 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
<> 144:ef7eb2e8f9f7 612 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
<> 144:ef7eb2e8f9f7 613 ((REQUEST) == I2C_NEXT_FRAME) || \
<> 144:ef7eb2e8f9f7 614 ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
<> 144:ef7eb2e8f9f7 615 ((REQUEST) == I2C_LAST_FRAME))
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @}
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /**
<> 144:ef7eb2e8f9f7 621 * @}
<> 144:ef7eb2e8f9f7 622 */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 625 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 144:ef7eb2e8f9f7 626 * @{
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /**
<> 144:ef7eb2e8f9f7 630 * @}
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /**
<> 144:ef7eb2e8f9f7 634 * @}
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /**
<> 144:ef7eb2e8f9f7 638 * @}
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643 #endif
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #endif /* __STM32F2xx_HAL_I2C_H */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/