Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_dma_ex.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_dma_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA Extension HAL module driver
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the DMA Extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended features functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 The DMA Extension HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 18 (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
<> 144:ef7eb2e8f9f7 19 for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
<> 144:ef7eb2e8f9f7 22 -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
<> 144:ef7eb2e8f9f7 23 -@- In Multi (Double) buffer mode, it is possible to update the base address for
<> 144:ef7eb2e8f9f7 24 the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 @endverbatim
<> 144:ef7eb2e8f9f7 27 ******************************************************************************
<> 144:ef7eb2e8f9f7 28 * @attention
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 33 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 34 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 35 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 36 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 37 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 38 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 39 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 40 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 41 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 44 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 46 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 50 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 53 *
<> 144:ef7eb2e8f9f7 54 ******************************************************************************
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** @defgroup DMAEx DMAEx
<> 144:ef7eb2e8f9f7 65 * @brief DMA Extended HAL module driver
<> 144:ef7eb2e8f9f7 66 * @{
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 /* Private Constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 74 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /** @addtogroup DMAEx_Private_Functions
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 80 /**
<> 144:ef7eb2e8f9f7 81 * @}
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup DMAEx_Exported_Functions
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @addtogroup DMAEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 92 *
<> 144:ef7eb2e8f9f7 93 @verbatim
<> 144:ef7eb2e8f9f7 94 ===============================================================================
<> 144:ef7eb2e8f9f7 95 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 96 ===============================================================================
<> 144:ef7eb2e8f9f7 97 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 98 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 99 Start MultiBuffer DMA transfer
<> 144:ef7eb2e8f9f7 100 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 101 Start MultiBuffer DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 102 (+) Change on the fly the memory0 or memory1 address.
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 @endverbatim
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /**
<> 144:ef7eb2e8f9f7 110 * @brief Starts the multi_buffer DMA Transfer.
<> 144:ef7eb2e8f9f7 111 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 112 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 113 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 114 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 115 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
<> 144:ef7eb2e8f9f7 116 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 117 * @retval HAL status
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Check the parameters */
<> 144:ef7eb2e8f9f7 124 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Memory-to-memory transfer not supported in double buffering mode */
<> 144:ef7eb2e8f9f7 127 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 130 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132 else
<> 144:ef7eb2e8f9f7 133 {
<> 144:ef7eb2e8f9f7 134 /* Process Locked */
<> 144:ef7eb2e8f9f7 135 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 138 {
<> 144:ef7eb2e8f9f7 139 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 140 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Enable the double buffer mode */
<> 144:ef7eb2e8f9f7 143 hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 146 hdma->Instance->M1AR = SecondMemAddress;
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 149 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Enable the peripheral */
<> 144:ef7eb2e8f9f7 152 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 153 }
<> 144:ef7eb2e8f9f7 154 else
<> 144:ef7eb2e8f9f7 155 {
<> 144:ef7eb2e8f9f7 156 /* Return error status */
<> 144:ef7eb2e8f9f7 157 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 158 }
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 return status;
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 165 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 166 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 167 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 168 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 169 * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
<> 144:ef7eb2e8f9f7 170 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 171 * @retval HAL status
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Check the parameters */
<> 144:ef7eb2e8f9f7 178 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Memory-to-memory transfer not supported in double buffering mode */
<> 144:ef7eb2e8f9f7 181 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
<> 144:ef7eb2e8f9f7 182 {
<> 144:ef7eb2e8f9f7 183 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 144:ef7eb2e8f9f7 184 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Check callback functions */
<> 144:ef7eb2e8f9f7 188 if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
<> 144:ef7eb2e8f9f7 191 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Process locked */
<> 144:ef7eb2e8f9f7 195 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 200 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 203 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Enable the Double buffer mode */
<> 144:ef7eb2e8f9f7 206 hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 209 hdma->Instance->M1AR = SecondMemAddress;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Configure the source, destination address and the data length */
<> 144:ef7eb2e8f9f7 212 DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Clear all flags */
<> 144:ef7eb2e8f9f7 215 __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 216 __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 217 __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 218 __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 219 __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Enable Common interrupts*/
<> 144:ef7eb2e8f9f7 222 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
<> 144:ef7eb2e8f9f7 223 hdma->Instance->FCR |= DMA_IT_FE;
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 hdma->Instance->CR |= DMA_IT_HT;
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /* Enable the peripheral */
<> 144:ef7eb2e8f9f7 231 __HAL_DMA_ENABLE(hdma);
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 else
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 /* Process unlocked */
<> 144:ef7eb2e8f9f7 236 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Return error status */
<> 144:ef7eb2e8f9f7 239 status = HAL_BUSY;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241 return status;
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Change the memory0 or memory1 address on the fly.
<> 144:ef7eb2e8f9f7 246 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 247 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 248 * @param Address: The new address
<> 144:ef7eb2e8f9f7 249 * @param memory: the memory to be changed, This parameter can be one of
<> 144:ef7eb2e8f9f7 250 * the following values:
<> 144:ef7eb2e8f9f7 251 * MEMORY0 /
<> 144:ef7eb2e8f9f7 252 * MEMORY1
<> 144:ef7eb2e8f9f7 253 * @note The MEMORY0 address can be changed only when the current transfer use
<> 144:ef7eb2e8f9f7 254 * MEMORY1 and the MEMORY1 address can be changed only when the current
<> 144:ef7eb2e8f9f7 255 * transfer use MEMORY0.
<> 144:ef7eb2e8f9f7 256 * @retval HAL status
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 if(memory == MEMORY0)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /* change the memory0 address */
<> 144:ef7eb2e8f9f7 263 hdma->Instance->M0AR = Address;
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265 else
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 /* change the memory1 address */
<> 144:ef7eb2e8f9f7 268 hdma->Instance->M1AR = Address;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 return HAL_OK;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /** @addtogroup DMAEx_Private_Functions
<> 144:ef7eb2e8f9f7 283 * @{
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @brief Set the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 288 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 289 * the configuration information for the specified DMA Stream.
<> 144:ef7eb2e8f9f7 290 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 291 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 292 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 293 * @retval HAL status
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Configure DMA Stream data length */
<> 144:ef7eb2e8f9f7 298 hdma->Instance->NDTR = DataLength;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 301 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 304 hdma->Instance->PAR = DstAddress;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 307 hdma->Instance->M0AR = SrcAddress;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 310 else
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Configure DMA Stream source address */
<> 144:ef7eb2e8f9f7 313 hdma->Instance->PAR = SrcAddress;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 /* Configure DMA Stream destination address */
<> 144:ef7eb2e8f9f7 316 hdma->Instance->M0AR = DstAddress;
<> 144:ef7eb2e8f9f7 317 }
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @}
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/