Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_dac.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_dac.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DAC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_DAC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DAC
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup DAC_Exported_Types DAC Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef enum
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 68 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
<> 144:ef7eb2e8f9f7 69 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
<> 144:ef7eb2e8f9f7 70 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
<> 144:ef7eb2e8f9f7 71 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
<> 144:ef7eb2e8f9f7 72 }HAL_DAC_StateTypeDef;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @brief DAC handle Structure definition
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 typedef struct
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 DAC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 HAL_LockTypeDef Lock; /*!< DAC locking object */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 __IO uint32_t ErrorCode; /*!< DAC Error code */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 }DAC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief DAC Configuration regular Channel structure definition
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96 typedef struct
<> 144:ef7eb2e8f9f7 97 {
<> 144:ef7eb2e8f9f7 98 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref DAC_trigger_selection */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
<> 144:ef7eb2e8f9f7 102 This parameter can be a value of @ref DAC_output_buffer */
<> 144:ef7eb2e8f9f7 103 }DAC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @}
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 109 /** @defgroup DAC_Exported_Constants DAC Exported Constants
<> 144:ef7eb2e8f9f7 110 * @{
<> 144:ef7eb2e8f9f7 111 */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /** @defgroup DAC_Error_Code DAC Error Code
<> 144:ef7eb2e8f9f7 114 * @{
<> 144:ef7eb2e8f9f7 115 */
<> 144:ef7eb2e8f9f7 116 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
<> 144:ef7eb2e8f9f7 117 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
<> 144:ef7eb2e8f9f7 118 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
<> 144:ef7eb2e8f9f7 119 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @defgroup DAC_trigger_selection DAC Trigger Selection
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
<> 144:ef7eb2e8f9f7 129 has been loaded, and not by external trigger */
<> 144:ef7eb2e8f9f7 130 #define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 131 #define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 132 #define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 133 #define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 134 #define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 135 #define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
<> 144:ef7eb2e8f9f7 138 #define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup DAC_output_buffer DAC Output Buffer
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 147 #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
<> 144:ef7eb2e8f9f7 148 /**
<> 144:ef7eb2e8f9f7 149 * @}
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup DAC_Channel_selection DAC Channel Selection
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155 #define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 156 #define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup DAC_data_alignment DAC Data Alignment
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 165 #define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 166 #define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @defgroup DAC_flags_definition DAC Flags Definition
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 175 #define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup DAC_IT_definition DAC IT Definition
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 #define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
<> 144:ef7eb2e8f9f7 184 #define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
<> 144:ef7eb2e8f9f7 185 /**
<> 144:ef7eb2e8f9f7 186 * @}
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 194 /** @defgroup DAC_Exported_Macros DAC Exported Macros
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @brief Reset DAC handle state
<> 144:ef7eb2e8f9f7 199 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 200 * @retval None
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /** @brief Enable the DAC channel
<> 144:ef7eb2e8f9f7 205 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 206 * @param __DAC_Channel__: specifies the DAC channel
<> 144:ef7eb2e8f9f7 207 * @retval None
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @brief Disable the DAC channel
<> 144:ef7eb2e8f9f7 212 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 213 * @param __DAC_Channel__: specifies the DAC channel.
<> 144:ef7eb2e8f9f7 214 * @retval None
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /** @brief Enable the DAC interrupt
<> 144:ef7eb2e8f9f7 219 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 220 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 221 * @retval None
<> 144:ef7eb2e8f9f7 222 */
<> 144:ef7eb2e8f9f7 223 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @brief Disable the DAC interrupt
<> 144:ef7eb2e8f9f7 226 * @param __HANDLE__: specifies the DAC handle
<> 144:ef7eb2e8f9f7 227 * @param __INTERRUPT__: specifies the DAC interrupt.
<> 144:ef7eb2e8f9f7 228 * @retval None
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /** @brief Checks if the specified DAC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 233 * @param __HANDLE__: DAC handle
<> 144:ef7eb2e8f9f7 234 * @param __INTERRUPT__: DAC interrupt source to check
<> 144:ef7eb2e8f9f7 235 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 236 * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 237 * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
<> 144:ef7eb2e8f9f7 238 * @retval State of interruption (SET or RESET)
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @brief Get the selected DAC's flag status.
<> 144:ef7eb2e8f9f7 243 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 244 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 245 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 246 * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
<> 144:ef7eb2e8f9f7 247 * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
<> 144:ef7eb2e8f9f7 248 * @retval None
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /** @brief Clear the DAC's flag.
<> 144:ef7eb2e8f9f7 253 * @param __HANDLE__: specifies the DAC handle.
<> 144:ef7eb2e8f9f7 254 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 255 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 256 * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
<> 144:ef7eb2e8f9f7 257 * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
<> 144:ef7eb2e8f9f7 258 * @retval None
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Include DAC HAL Extension module */
<> 144:ef7eb2e8f9f7 266 #include "stm32f2xx_hal_dac_ex.h"
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 269 /** @addtogroup DAC_Exported_Functions
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @addtogroup DAC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 /* Initialization/de-initialization functions *********************************/
<> 144:ef7eb2e8f9f7 277 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 278 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 279 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 280 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @addtogroup DAC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 /* I/O operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 289 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 290 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 291 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
<> 144:ef7eb2e8f9f7 292 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 293 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @}
<> 144:ef7eb2e8f9f7 296 */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** @addtogroup DAC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 302 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @addtogroup DAC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 309 * @{
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 312 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 313 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 314 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 317 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
<> 144:ef7eb2e8f9f7 318 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 319 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @}
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 328 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 329 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 330 /** @defgroup DAC_Private_Constants DAC Private Constants
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /**
<> 144:ef7eb2e8f9f7 335 * @}
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 339 /** @defgroup DAC_Private_Macros DAC Private Macros
<> 144:ef7eb2e8f9f7 340 * @{
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
<> 144:ef7eb2e8f9f7 343 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
<> 144:ef7eb2e8f9f7 344 ((ALIGN) == DAC_ALIGN_12B_L) || \
<> 144:ef7eb2e8f9f7 345 ((ALIGN) == DAC_ALIGN_8B_R))
<> 144:ef7eb2e8f9f7 346 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 347 ((CHANNEL) == DAC_CHANNEL_2))
<> 144:ef7eb2e8f9f7 348 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
<> 144:ef7eb2e8f9f7 349 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
<> 144:ef7eb2e8f9f7 352 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
<> 144:ef7eb2e8f9f7 353 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
<> 144:ef7eb2e8f9f7 354 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
<> 144:ef7eb2e8f9f7 355 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
<> 144:ef7eb2e8f9f7 356 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
<> 144:ef7eb2e8f9f7 357 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
<> 144:ef7eb2e8f9f7 358 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
<> 144:ef7eb2e8f9f7 359 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /** @brief Set DHR12R1 alignment
<> 144:ef7eb2e8f9f7 362 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 363 * @retval None
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @brief Set DHR12R2 alignment
<> 144:ef7eb2e8f9f7 368 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /** @brief Set DHR12RD alignment
<> 144:ef7eb2e8f9f7 374 * @param __ALIGNMENT__: specifies the DAC alignment
<> 144:ef7eb2e8f9f7 375 * @retval None
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @}
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 384 /** @defgroup DAC_Private_Functions DAC Private Functions
<> 144:ef7eb2e8f9f7 385 * @{
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @}
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 #endif
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #endif /*__STM32F2xx_HAL_DAC_H */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/