Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_cortex.c@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 20 ===========================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 23 The Cortex-M3 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
<> 144:ef7eb2e8f9f7 26 function according to the following table.
<> 144:ef7eb2e8f9f7 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
<> 144:ef7eb2e8f9f7 28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 29 (#) please refer to programing manual for details in how to configure priority.
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
<> 144:ef7eb2e8f9f7 32 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 -@- IRQ priority order (sorted by highest to lowest priority):
<> 144:ef7eb2e8f9f7 35 (+@) Lowest preemption priority
<> 144:ef7eb2e8f9f7 36 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 37 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 *** How to configure Systick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 41 ========================================================
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 46 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 47 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 144:ef7eb2e8f9f7 49 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 51 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 52 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
<> 144:ef7eb2e8f9f7 57 inside the stm32f2xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 67 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
<> 144:ef7eb2e8f9f7 70 ******************************************************************************
<> 144:ef7eb2e8f9f7 71 * @attention
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 76 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 77 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 81 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 83 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 84 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 85 *
<> 144:ef7eb2e8f9f7 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 108 * @brief CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 122 * @{
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 135 Systick functionalities
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 @endverbatim
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @brief Sets the priority grouping field (preemption priority and subpriority)
<> 144:ef7eb2e8f9f7 144 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 145 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 146 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
<> 144:ef7eb2e8f9f7 148 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
<> 144:ef7eb2e8f9f7 150 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
<> 144:ef7eb2e8f9f7 152 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
<> 144:ef7eb2e8f9f7 154 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
<> 144:ef7eb2e8f9f7 156 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
<> 144:ef7eb2e8f9f7 158 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 159 * @retval None
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 162 {
<> 144:ef7eb2e8f9f7 163 /* Check the parameters */
<> 144:ef7eb2e8f9f7 164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 167 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @brief Sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 172 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 173 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 174 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 175 * @param PreemptPriority: The preemption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 176 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 177 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 178 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 179 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 180 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 181 * @retval None
<> 144:ef7eb2e8f9f7 182 */
<> 144:ef7eb2e8f9f7 183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 uint32_t prioritygroup = 0x00U;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Check the parameters */
<> 144:ef7eb2e8f9f7 188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 199 * function should be called before.
<> 144:ef7eb2e8f9f7 200 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 201 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 202 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 203 * @retval None
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 206 {
<> 144:ef7eb2e8f9f7 207 /* Check the parameters */
<> 144:ef7eb2e8f9f7 208 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 211 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 216 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 217 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 218 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 219 * @retval None
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 /* Check the parameters */
<> 144:ef7eb2e8f9f7 224 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 227 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 228 }
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 232 * @retval None
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* System Reset */
<> 144:ef7eb2e8f9f7 237 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 242 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 243 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 244 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 245 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 256 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 @verbatim
<> 144:ef7eb2e8f9f7 259 ==============================================================================
<> 144:ef7eb2e8f9f7 260 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 261 ==============================================================================
<> 144:ef7eb2e8f9f7 262 [..]
<> 144:ef7eb2e8f9f7 263 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 264 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 @endverbatim
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if (__MPU_PRESENT == 1U)
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Initializes and configures the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 274 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 275 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 276 * @retval None
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* Check the parameters */
<> 144:ef7eb2e8f9f7 281 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 282 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Set the Region number */
<> 144:ef7eb2e8f9f7 285 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Check the parameters */
<> 144:ef7eb2e8f9f7 290 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 291 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 292 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 293 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 294 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 295 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 296 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 297 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 300 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 301 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 302 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 303 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 304 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 305 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 306 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 307 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 308 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310 else
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 MPU->RBAR = 0x00U;
<> 144:ef7eb2e8f9f7 313 MPU->RASR = 0x00U;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 320 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 325 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @brief Gets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 330 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 331 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 332 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 333 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 334 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 335 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
<> 144:ef7eb2e8f9f7 336 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 337 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
<> 144:ef7eb2e8f9f7 338 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 339 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
<> 144:ef7eb2e8f9f7 340 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 341 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
<> 144:ef7eb2e8f9f7 342 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 343 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
<> 144:ef7eb2e8f9f7 344 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 345 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 346 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 347 * @retval None
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Check the parameters */
<> 144:ef7eb2e8f9f7 352 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 353 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 354 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 359 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 360 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 361 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 362 * @retval None
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 365 {
<> 144:ef7eb2e8f9f7 366 /* Check the parameters */
<> 144:ef7eb2e8f9f7 367 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 370 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 375 * and returns the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 376 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 377 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 378 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 379 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 380 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 /* Check the parameters */
<> 144:ef7eb2e8f9f7 385 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 388 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @brief Clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 393 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 394 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 395 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 396 * @retval None
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 /* Check the parameters */
<> 144:ef7eb2e8f9f7 401 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 404 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
<> 144:ef7eb2e8f9f7 409 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 410 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 411 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
<> 144:ef7eb2e8f9f7 412 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 413 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /* Check the parameters */
<> 144:ef7eb2e8f9f7 418 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 421 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @brief Configures the SysTick clock source.
<> 144:ef7eb2e8f9f7 426 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 427 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 428 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 429 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 430 * @retval None
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 /* Check the parameters */
<> 144:ef7eb2e8f9f7 435 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 436 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 437 {
<> 144:ef7eb2e8f9f7 438 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 else
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444 }
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /**
<> 144:ef7eb2e8f9f7 447 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 448 * @retval None
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 457 * @retval None
<> 144:ef7eb2e8f9f7 458 */
<> 144:ef7eb2e8f9f7 459 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 462 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /**
<> 144:ef7eb2e8f9f7 471 * @}
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @}
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @}
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/