Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/TOOLCHAIN_ARM/startup_NCS36510.s@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/* File: startup_ncs36510.s
<> 144:ef7eb2e8f9f7 2 ; * Purpose: startup file for Cortex-M3 devices. Should use with
<> 144:ef7eb2e8f9f7 3 ; * ARMGCC for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 ; * Version: V2.00
<> 144:ef7eb2e8f9f7 5 ; * Date: 25 Feb 2016
<> 144:ef7eb2e8f9f7 6 ; *
<> 144:ef7eb2e8f9f7 7 ; */
<> 144:ef7eb2e8f9f7 8 ;/* Copyright (c) 2011 - 2014 ARM LIMITED
<> 144:ef7eb2e8f9f7 9 ;
<> 144:ef7eb2e8f9f7 10 ; All rights reserved.
<> 144:ef7eb2e8f9f7 11 ; Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 12 ; modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 ; - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 14 ; notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 ; - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 16 ; notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 17 ; documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 ; - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 19 ; to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 20 ; specific prior written permission.
<> 144:ef7eb2e8f9f7 21 ; *
<> 144:ef7eb2e8f9f7 22 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 25 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 26 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 27 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 28 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 29 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 30 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 31 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 32 ; POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 ; ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 PRESERVE8
<> 144:ef7eb2e8f9f7 37 THUMB
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 ; Vector Table Mapped to Address 0x3000 at Reset
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 43 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 44 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 45 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 46 IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
<> 144:ef7eb2e8f9f7 49 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 50 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 51 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 52 DCD MemManage_Handler ; MPU Fault Handler
<> 144:ef7eb2e8f9f7 53 DCD BusFault_Handler ; Bus Fault Handler
<> 144:ef7eb2e8f9f7 54 DCD UsageFault_Handler ; Usage Fault Handler
<> 144:ef7eb2e8f9f7 55 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 56 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 57 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 60 DCD DebugMon_Handler ; Debug Monitor Handler
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 63 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 ; External Interrupts
<> 144:ef7eb2e8f9f7 66 DCD fIrqTim0Handler
<> 144:ef7eb2e8f9f7 67 DCD fIrqTim1Handler
<> 144:ef7eb2e8f9f7 68 DCD fIrqTim2Handler
<> 144:ef7eb2e8f9f7 69 DCD fIrqUart1Handler
<> 144:ef7eb2e8f9f7 70 DCD fIrqSpiHandler
<> 144:ef7eb2e8f9f7 71 DCD fIrqI2CHandler
<> 144:ef7eb2e8f9f7 72 DCD fIrqGpioHandler
<> 144:ef7eb2e8f9f7 73 DCD fIrqRtcHandler
<> 144:ef7eb2e8f9f7 74 DCD fIrqFlashHandler
<> 144:ef7eb2e8f9f7 75 DCD fIrqMacHwHandler
<> 144:ef7eb2e8f9f7 76 DCD fIrqAesHandler
<> 144:ef7eb2e8f9f7 77 DCD fIrqAdcHandler
<> 144:ef7eb2e8f9f7 78 DCD fIrqClockCalHandler
<> 144:ef7eb2e8f9f7 79 DCD fIrqUart2Handler
<> 144:ef7eb2e8f9f7 80 DCD fIrqUviHandler
<> 144:ef7eb2e8f9f7 81 DCD fIrqDmaHandler
<> 144:ef7eb2e8f9f7 82 DCD fIrqDbgPwrUpHandler
<> 144:ef7eb2e8f9f7 83 DCD fIrqSpi2Handler
<> 144:ef7eb2e8f9f7 84 DCD fIrqI2C2Handler
<> 144:ef7eb2e8f9f7 85 DCD fIrqFVDDHCompHandler
<> 144:ef7eb2e8f9f7 86 __Vectors_End
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 ; Reset Handler
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 95 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 96 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 97 IMPORT __main
<> 144:ef7eb2e8f9f7 98 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 99 BLX R0
<> 144:ef7eb2e8f9f7 100 LDR R0, =__main
<> 144:ef7eb2e8f9f7 101 BX R0
<> 144:ef7eb2e8f9f7 102 ENDP
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 108 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 109 B .
<> 144:ef7eb2e8f9f7 110 ENDP
<> 144:ef7eb2e8f9f7 111 HardFault_Handler\
<> 144:ef7eb2e8f9f7 112 PROC
<> 144:ef7eb2e8f9f7 113 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 114 B .
<> 144:ef7eb2e8f9f7 115 ENDP
<> 144:ef7eb2e8f9f7 116 MemManage_Handler\
<> 144:ef7eb2e8f9f7 117 PROC
<> 144:ef7eb2e8f9f7 118 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 119 B .
<> 144:ef7eb2e8f9f7 120 ENDP
<> 144:ef7eb2e8f9f7 121 BusFault_Handler\
<> 144:ef7eb2e8f9f7 122 PROC
<> 144:ef7eb2e8f9f7 123 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 124 B .
<> 144:ef7eb2e8f9f7 125 ENDP
<> 144:ef7eb2e8f9f7 126 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 127 PROC
<> 144:ef7eb2e8f9f7 128 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 129 B .
<> 144:ef7eb2e8f9f7 130 ENDP
<> 144:ef7eb2e8f9f7 131 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 132 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 133 B .
<> 144:ef7eb2e8f9f7 134 ENDP
<> 144:ef7eb2e8f9f7 135 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 136 PROC
<> 144:ef7eb2e8f9f7 137 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 138 B .
<> 144:ef7eb2e8f9f7 139 ENDP
<> 144:ef7eb2e8f9f7 140 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 141 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 142 B .
<> 144:ef7eb2e8f9f7 143 ENDP
<> 144:ef7eb2e8f9f7 144 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 145 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 146 B .
<> 144:ef7eb2e8f9f7 147 ENDP
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 Default_Handler PROC
<> 144:ef7eb2e8f9f7 150 EXPORT fIrqTim0Handler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT fIrqTim1Handler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT fIrqTim2Handler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT fIrqUart1Handler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT fIrqSpiHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT fIrqI2CHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT fIrqGpioHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT fIrqRtcHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT fIrqFlashHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT fIrqMacHwHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT fIrqAesHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT fIrqAdcHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT fIrqClockCalHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT fIrqUart2Handler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT fIrqUviHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT fIrqDmaHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT fIrqDbgPwrUpHandler [WEAK]
<> 144:ef7eb2e8f9f7 167 EXPORT fIrqSpi2Handler [WEAK]
<> 144:ef7eb2e8f9f7 168 EXPORT fIrqI2C2Handler [WEAK]
<> 144:ef7eb2e8f9f7 169 EXPORT fIrqFVDDHCompHandler [WEAK]
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 fIrqTim0Handler
<> 144:ef7eb2e8f9f7 172 fIrqTim1Handler
<> 144:ef7eb2e8f9f7 173 fIrqTim2Handler
<> 144:ef7eb2e8f9f7 174 fIrqUart1Handler
<> 144:ef7eb2e8f9f7 175 fIrqSpiHandler
<> 144:ef7eb2e8f9f7 176 fIrqI2CHandler
<> 144:ef7eb2e8f9f7 177 fIrqGpioHandler
<> 144:ef7eb2e8f9f7 178 fIrqRtcHandler
<> 144:ef7eb2e8f9f7 179 fIrqFlashHandler
<> 144:ef7eb2e8f9f7 180 fIrqMacHwHandler
<> 144:ef7eb2e8f9f7 181 fIrqAesHandler
<> 144:ef7eb2e8f9f7 182 fIrqAdcHandler
<> 144:ef7eb2e8f9f7 183 fIrqClockCalHandler
<> 144:ef7eb2e8f9f7 184 fIrqUart2Handler
<> 144:ef7eb2e8f9f7 185 fIrqUviHandler
<> 144:ef7eb2e8f9f7 186 fIrqDmaHandler
<> 144:ef7eb2e8f9f7 187 fIrqDbgPwrUpHandler
<> 144:ef7eb2e8f9f7 188 fIrqSpi2Handler
<> 144:ef7eb2e8f9f7 189 fIrqI2C2Handler
<> 144:ef7eb2e8f9f7 190 fIrqFVDDHCompHandler
<> 144:ef7eb2e8f9f7 191 DefaultISR
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 B .
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 ENDP
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 EXPORT __user_initial_stackheap
<> 144:ef7eb2e8f9f7 198 IMPORT |Image$$ARM_LIB_HEAP$$Base|
<> 144:ef7eb2e8f9f7 199 IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit|
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 __user_initial_stackheap PROC
<> 144:ef7eb2e8f9f7 202 LDR R0, = |Image$$ARM_LIB_HEAP$$Base|
<> 144:ef7eb2e8f9f7 203 LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit|
<> 144:ef7eb2e8f9f7 204 BX LR
<> 144:ef7eb2e8f9f7 205 ENDP
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 ALIGN
<> 144:ef7eb2e8f9f7 208 END