Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_WDT_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_WDT_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file wdt_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup wdt WDT
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines watchdog timer periods
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** 2^31 cycle period */
<> 144:ef7eb2e8f9f7 54 MXC_E_WDT_PERIOD_2_31_CLKS = 0,
<> 144:ef7eb2e8f9f7 55 /** 2^30 cycle period */
<> 144:ef7eb2e8f9f7 56 MXC_E_WDT_PERIOD_2_30_CLKS,
<> 144:ef7eb2e8f9f7 57 /** 2^29 cycle period */
<> 144:ef7eb2e8f9f7 58 MXC_E_WDT_PERIOD_2_29_CLKS,
<> 144:ef7eb2e8f9f7 59 /** 2^28 cycle period */
<> 144:ef7eb2e8f9f7 60 MXC_E_WDT_PERIOD_2_28_CLKS,
<> 144:ef7eb2e8f9f7 61 /** 2^27 cycle period */
<> 144:ef7eb2e8f9f7 62 MXC_E_WDT_PERIOD_2_27_CLKS,
<> 144:ef7eb2e8f9f7 63 /** 2^26 cycle period */
<> 144:ef7eb2e8f9f7 64 MXC_E_WDT_PERIOD_2_26_CLKS,
<> 144:ef7eb2e8f9f7 65 /** 2^25 cycle period */
<> 144:ef7eb2e8f9f7 66 MXC_E_WDT_PERIOD_2_25_CLKS,
<> 144:ef7eb2e8f9f7 67 /** 2^24 cycle period */
<> 144:ef7eb2e8f9f7 68 MXC_E_WDT_PERIOD_2_24_CLKS,
<> 144:ef7eb2e8f9f7 69 /** 2^23 cycle period */
<> 144:ef7eb2e8f9f7 70 MXC_E_WDT_PERIOD_2_23_CLKS,
<> 144:ef7eb2e8f9f7 71 /** 2^22 cycle period */
<> 144:ef7eb2e8f9f7 72 MXC_E_WDT_PERIOD_2_22_CLKS,
<> 144:ef7eb2e8f9f7 73 /** 2^21 cycle period */
<> 144:ef7eb2e8f9f7 74 MXC_E_WDT_PERIOD_2_21_CLKS,
<> 144:ef7eb2e8f9f7 75 /** 2^20 cycle period */
<> 144:ef7eb2e8f9f7 76 MXC_E_WDT_PERIOD_2_20_CLKS,
<> 144:ef7eb2e8f9f7 77 /** 2^19 cycle period */
<> 144:ef7eb2e8f9f7 78 MXC_E_WDT_PERIOD_2_19_CLKS,
<> 144:ef7eb2e8f9f7 79 /** 2^18 cycle period */
<> 144:ef7eb2e8f9f7 80 MXC_E_WDT_PERIOD_2_18_CLKS,
<> 144:ef7eb2e8f9f7 81 /** 2^17 cycle period */
<> 144:ef7eb2e8f9f7 82 MXC_E_WDT_PERIOD_2_17_CLKS,
<> 144:ef7eb2e8f9f7 83 /** 2^16 cycle period */
<> 144:ef7eb2e8f9f7 84 MXC_E_WDT_PERIOD_2_16_CLKS,
<> 144:ef7eb2e8f9f7 85 } mxc_wdt_period_t;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Offset Register Description
<> 144:ef7eb2e8f9f7 88 ====== ================================================ */
<> 144:ef7eb2e8f9f7 89 typedef struct {
<> 144:ef7eb2e8f9f7 90 __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
<> 144:ef7eb2e8f9f7 91 __IO uint32_t clear; /* 0x0004 Watchdog Clear Register (Feed Dog) */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t int_rst_fl; /* 0x0008 Watchdog Interrupt/Reset Flags */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t int_rst_en; /* 0x000C Interrupt/Reset Enable/Disable Controls */
<> 144:ef7eb2e8f9f7 94 __I uint32_t rsv0010; /* 0x0010 */
<> 144:ef7eb2e8f9f7 95 __IO uint32_t lock_ctrl; /* 0x0014 Lock Register Setting for WDT CTRL */
<> 144:ef7eb2e8f9f7 96 } mxc_wdt_regs_t;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /*
<> 144:ef7eb2e8f9f7 99 Register offsets for module WDT.
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_WDT_OFFS_INT_RST_FL ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_WDT_OFFS_INT_RST_EN ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MXC_V_WDT_WDLOCK_LOCK_KEY ((uint8_t)0x24)
<> 144:ef7eb2e8f9f7 108 #define MXC_V_WDT_WDLOCK_UNLOCK_KEY ((uint8_t)0x42)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /*
<> 144:ef7eb2e8f9f7 112 Field positions and masks for module WDT.
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
<> 144:ef7eb2e8f9f7 115 #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 116 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
<> 144:ef7eb2e8f9f7 117 #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
<> 144:ef7eb2e8f9f7 118 #define MXC_F_WDT_CTRL_EN_TIMER_POS 8
<> 144:ef7eb2e8f9f7 119 #define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
<> 144:ef7eb2e8f9f7 120 #define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
<> 144:ef7eb2e8f9f7 121 #define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
<> 144:ef7eb2e8f9f7 122 #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
<> 144:ef7eb2e8f9f7 123 #define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
<> 144:ef7eb2e8f9f7 126 #define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 127 #define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
<> 144:ef7eb2e8f9f7 128 #define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
<> 144:ef7eb2e8f9f7 129 #define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
<> 144:ef7eb2e8f9f7 130 #define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
<> 144:ef7eb2e8f9f7 133 #define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
<> 144:ef7eb2e8f9f7 134 #define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
<> 144:ef7eb2e8f9f7 135 #define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
<> 144:ef7eb2e8f9f7 136 #define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
<> 144:ef7eb2e8f9f7 137 #define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
<> 144:ef7eb2e8f9f7 140 #define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144 #endif
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #endif /* _MXC_WDT_REGS_H_ */