Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Maxim/TARGET_MAX32610/tmr_regs.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_TMR_REGS_H
<> 144:ef7eb2e8f9f7 35 #define _MXC_TMR_REGS_H
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /**
<> 144:ef7eb2e8f9f7 44 * @file tmr_regs.h
<> 144:ef7eb2e8f9f7 45 * @addtogroup tmr TMR
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**
<> 144:ef7eb2e8f9f7 50 * @brief Defines timer modes for 16 and 32-bit timers
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 typedef enum {
<> 144:ef7eb2e8f9f7 53 /** 32-bit or 16-bit timer one-shot mode */
<> 144:ef7eb2e8f9f7 54 MXC_E_TMR_MODE_ONE_SHOT = 0,
<> 144:ef7eb2e8f9f7 55 /** 32-bit or 16-bit timer one-shot mode */
<> 144:ef7eb2e8f9f7 56 MXC_E_TMR_MODE_CONTINUOUS,
<> 144:ef7eb2e8f9f7 57 /** 32-bit timer counter mode */
<> 144:ef7eb2e8f9f7 58 MXC_E_TMR_MODE_COUNTER,
<> 144:ef7eb2e8f9f7 59 /** 32-bit timer pulse width modulation mode */
<> 144:ef7eb2e8f9f7 60 MXC_E_TMR_MODE_PWM,
<> 144:ef7eb2e8f9f7 61 /** 32-bit timer capture mode */
<> 144:ef7eb2e8f9f7 62 MXC_E_TMR_MODE_CAPTURE,
<> 144:ef7eb2e8f9f7 63 /** 32-bit timer compare mode */
<> 144:ef7eb2e8f9f7 64 MXC_E_TMR_MODE_COMPARE,
<> 144:ef7eb2e8f9f7 65 /** 32-bit timer gated mode */
<> 144:ef7eb2e8f9f7 66 MXC_E_TMR_MODE_GATED,
<> 144:ef7eb2e8f9f7 67 /** 32-bit timer measure mode */
<> 144:ef7eb2e8f9f7 68 MXC_E_TMR_MODE_MEASURE
<> 144:ef7eb2e8f9f7 69 } mxc_tmr_mode_t;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Offset Register Description
<> 144:ef7eb2e8f9f7 72 ====== ============================================== */
<> 144:ef7eb2e8f9f7 73 typedef struct {
<> 144:ef7eb2e8f9f7 74 __IO uint32_t ctrl; /* 0x0000 Timer Control Register */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t count32; /* 0x0004 [32 bit] Current Count Value */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t term_cnt32; /* 0x0008 [32 bit] Terminal Count Setting */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t pwm_cap32; /* 0x000C [32 bit] PWM Compare Setting or Capture/Measure Value */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t count16_0; /* 0x0010 [16 bit] Current Count Value, 16-bit Timer0 */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t term_cnt16_0; /* 0x0014 [16 bit] Terminal Count Setting, 16-bit Timer0 */
<> 144:ef7eb2e8f9f7 80 __IO uint32_t count16_1; /* 0x0018 [16 bit] Current Count Value, 16-bit Timer1 */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t term_cnt16_1; /* 0x001C [16 bit] Terminal Count Setting, 16-bit Timer1 */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t intfl; /* 0x0020 Timer Module Interrupt Flags */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t inten; /* 0x0024 Timer Module Interrupt Enable/Disable Settings */
<> 144:ef7eb2e8f9f7 84 } mxc_tmr_regs_t;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /*
<> 144:ef7eb2e8f9f7 87 Register offsets for module TMR.
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 #define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 90 #define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 91 #define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 93 #define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 94 #define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL)
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /*
<> 144:ef7eb2e8f9f7 101 Field positions and masks for module TMR.
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #define MXC_F_TMR_CTRL_MODE_POS 0
<> 144:ef7eb2e8f9f7 104 #define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
<> 144:ef7eb2e8f9f7 105 #define MXC_F_TMR_CTRL_TMR2X16_POS 3
<> 144:ef7eb2e8f9f7 106 #define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
<> 144:ef7eb2e8f9f7 107 #define MXC_F_TMR_CTRL_PRESCALE_POS 4
<> 144:ef7eb2e8f9f7 108 #define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
<> 144:ef7eb2e8f9f7 109 #define MXC_F_TMR_CTRL_POLARITY_POS 8
<> 144:ef7eb2e8f9f7 110 #define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
<> 144:ef7eb2e8f9f7 111 #define MXC_F_TMR_CTRL_ENABLE0_POS 12
<> 144:ef7eb2e8f9f7 112 #define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
<> 144:ef7eb2e8f9f7 113 #define MXC_F_TMR_CTRL_ENABLE1_POS 13
<> 144:ef7eb2e8f9f7 114 #define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #define MXC_F_TMR_COUNT16_0_VALUE_POS 0
<> 144:ef7eb2e8f9f7 117 #define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0
<> 144:ef7eb2e8f9f7 120 #define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #define MXC_F_TMR_COUNT16_1_VALUE_POS 0
<> 144:ef7eb2e8f9f7 123 #define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0
<> 144:ef7eb2e8f9f7 126 #define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define MXC_F_TMR_INTFL_TIMER0_POS 0
<> 144:ef7eb2e8f9f7 129 #define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
<> 144:ef7eb2e8f9f7 130 #define MXC_F_TMR_INTFL_TIMER1_POS 1
<> 144:ef7eb2e8f9f7 131 #define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 #define MXC_F_TMR_INTEN_TIMER0_POS 0
<> 144:ef7eb2e8f9f7 134 #define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
<> 144:ef7eb2e8f9f7 135 #define MXC_F_TMR_INTEN_TIMER1_POS 1
<> 144:ef7eb2e8f9f7 136 #define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140 #endif
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /**
<> 144:ef7eb2e8f9f7 143 * @}
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #endif /* _MXC_TMR_REGS_H */